IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO.

9, SEPTEMBER 2012

2833

Wideband Inductorless Balun-LNA Employing

Feedback for Low-Power Low-Voltage Applications
Jusung Kim, Member, IEEE, and Jose Silva-Martinez, Fellow, IEEE

AbstractA wideband inductorless low-noise-amplifier (LNA)

with single-to-differential conversion for multistandard radio
applications is proposed. Noise-suppressed current-mirror-based
biasing is utilized to ensure stable operation under process,
voltage, and temperature variations. The inherent gain of the
common-source (CS) stage is re-used to boost the trans-conductance of the common-gate (CG) stage, and hence, a noise- and
power-efficient design is achieved without hurting the noise and
distortion cancellation properties of the CGCS-based balun
topology. The gain and phase balance is improved by employing
an efficient compensation scheme. The prototype was realized in
0.13- m CMOS, operates from 0.1 to 2 GHz, and dissipates 3 mW
from 1.2-V supply while occupying a 0.075-mm active area.
The balun-LNA, including the output buffer, provides 7.6-dB
maximum power gain, 4.15-dB minimum noise figure, better than
without any on-chip
10-dB input matching, and 0.5-dBm
inductor.
Index TermsBalun, CMOS, common-gate (CG) amplifier,
common-source (CS) amplifier, feedback amplifier, low-noise amplifier (LNA), multistandard receiver, multistandard transceiver,
wideband.

I. INTRODUCTION

ECENTLY, multistandard radio receivers have drawn

strong attention because future wireless communication
devices must support multiple standards and features on a single
chip. The low-noise amplifier (LNA), as the first active block
in the receiver chain, must have good impedance matching,
low noise, and high linearity across a wide frequency band.
The conventional solution employs several LC-tuned LNAs
to cover a dedicated small band over the desired frequency
span [1], [2]. The other extreme is a wideband LNA [3] with
more flexibility and better efficiency in terms of form factor,
cost, and power, but its performance must be comparable to
or even better than narrowband tuned LNAs due to concurrent
reception of unfiltered multistandard signals. For instance, a
transmitter (TX) jammer from the frequency-division duplexed
(FDD) system presents the strongest blocker ( 20 dBm) in
the receiver [4], [5]. A wideband LNA cannot handle such a
large blocker without the help of passive filters, such as surface
Manuscript received March 06, 2012; revised June 15, 2012; accepted June
18, 2012. Date of publication July 24, 2012; date of current version August 28,
2012.
J. Kim is with Qualcomm Inc., San Diego, CA 92121 USA (e-mail:
jusungk@qualcomm.com).
J. Silva-Martinez is with the Analog and Mixed Signal Center, Texas A&M
University, College Station, TX 77843 USA (e-mail: jsilva@ece.tamu.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2012.2206825

acoustic wave (SAW) and thin film bulk acoustic resonator

(FBAR) filters. However, passive filters are typically narrowband. Hence, large banks of filters are required for wideband
systems, which are expensive [5].
A balanced and symmetrical architecture is preferred over
an unbalanced one due to its robustness to power-supply and
substrate noise. Second-order distortion in the receive chain is
significantly reduced when differential (balanced) signaling in
the receive chain is adopted. However, antennas and RF filters
typically produce single-ended input/output (I/O), and thus,
at some point in the receiver, single-to-differential circuitry is
required [6], [7]. Passive components have been used to implement the single-to-differential conversion, but this solution is
usually bulky and therefore not suitable for integrated circuits
[8], [9]. A passive-balun is also lossy and narrowband so that
several components dedicated to each frequency band are required for wideband operation, leading to higher costs. Current
state-of-the-art RF systems with high-sensitivity requirements
demand high-performance baluns that have low loss and small
area. An active-balun satisfies these requirements very well
since it provides sufficiently high power gain and low noise
over a wideband. In addition, an active-balun should present
good performance in power supply rejection, output balancing,
and linearity, especially without a pre-filtering stage. Several
topologies exist presently, which are: 1) a single transistor with
common-source (CS) and common-drain (source follower) outputs [6], [10]; 2) a differential pair with a single input ac grounded
[11][13]; and a 3) CS and common-gate (CG) pair [14][16].
In this paper, we present an inductorless balun-LNA based on
the CGCS topology. Previous studies [14], [15] have shown
that CGCS topology with trans-conductance scaling in the CS
stage can achieve a low noise figure (NF) ( 3 dB) with a balanced output and noise and distortion cancellation. However,
the noise and headroom issue due to the biasing of the CG
stage was not fully accounted for, previous studies used either
noisy bias resistor [14] or a noiseless and bulky inductor in
[15]. A passive device used as a current source suffers from
process, voltage, and temperature (PVT) variations, in contrast
with the stable operation if a bias scheme based on currentmirror is employed. The proposed current-mirror biasing with a
PVT insensitive current source (or sink) presents strong immunity to process and temperature variations. The proposed architecture employing negative feedback features lower power and
achieves better bandwidth with minimal noise due to the active
bias current source. The frequency compensation in the CS stage
ensures better gain and phase balance, whereas previous studies
[14], [15] show frequency-response mismatch between CG and
CS stages.

0018-9480/$31.00 2012 IEEE

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 9, SEPTEMBER 2012

Fig. 1. Active-balun topologies. (a) Single transistor topology. (b) Differential

topology with a single input ac grounded. (c) CGCS topology.

This paper is organized as follows. Section II reviews the active-balun topologies and their properties. Section III describes
the proposed inductorless balun-LNA and provides analytical
expressions for input impedance, gain, bandwidth, NF, and
output balancing. Section IV presents measurement results, and
concluding remarks are given in Section V.
II. ACTIVE-BALUN TOPOLOGIES AND THEIR PROPERTIES
Several passive and active differential phase shifters or baluns
exist in the literature. A passive balun, due to its lossy and bulky
nature, is not suitable for integrated circuit operations and thus
is not considered further.
Fig. 1 shows several previously proposed active-balun
topologies [6], [10][16]. The single transistor topology in
Fig. 1(a) with 180 antiphase outputs at drain and source
terminals is probably the simplest implementation of the active-balun. However, the asymmetric source and drain parasitics
at its two outputs causes unequal signal leakage, especially
at high frequency. In order to achieve a good balance at high
frequency ( 1 GHz), a dummy transistor to compensate for
unequal parasitics is deliberately added in [6], but this solution
requires careful simulation and design to ensure sufficient gain
and phase balance. Cross connection of three single transistor
phase shifter is utilized to cancel the imbalance between differential output in [10] at the expense of degradation in other
performances (e.g., noise and linearity).

Fig. 1(b) shows the differential topology where one of the

differential pair inputs is ac grounded. The RF signal is applied
at the gate of one of the differential pair transistors, and ideally
RF current flows through both differential pair branches with
the same magnitude, but opposite direction [17]. Two nonidealities limit the balance of the differential pair topology, which
are finite impedance and feed-forward path mainly due to
of differential pair transistors.
The imbalance due to these effects prevents the use of differential pair topology at high frequency. One solution is to feed
back a fraction of the single-ended output signal to the second
transistor [13]. A feed-forward path from the input node to noninverting output node can also be employed to shift the zero of
the noninverting output node to a lower frequency [17].
The CGCS topology in Fig. 1(c) has drawn significant attention due to its advantageous properties of noise and distortion cancellation [14][16]. Blaakmeer et al. [14] demonstrated
that, by trans-conductance scaling, the CGCS topology can
provide wideband matching, noise and distortion cancellation,
and output balancing. In this study [14], the authors provide the
output balancing condition at low frequency, but do not explicitly show how the differential output can be balanced at high frequency, especially when the trans-conductance of the CS stage
is scaled ( 4 ), although the measurement shows good gain
and phase balance up to 3.5 GHz. In [16], local feedback is utilized to boost the trans-conductance of the CG stage. However,
the feedback signal is accommodated from the cascode node of
the CS stage where low signal swing is desired to minimize the
Miller effect and enhance the frequency response. A resistive
bias is also used for the CG stage susceptible to PVT variations.
The studies in [18] and [19] employed a differential current balancer (DCR) to compensate for gain and phase imbalance and
showed good performance. The DCR can be inserted between
CGCS amplifiers and the load at the expense of voltage headroom [19]. In [18], the DCR is cascaded between the passive
balun and the mixer with a large silicon area. In both these cases,
good gain and phase balance in [18] and [19] are mainly due to
the differential nature of the DCR.
III. WIDEBAND INDUCTORLESS BALUN-LNA
Fig. 2 shows the proposed wideband inductorless
balun-LNA employing negative feedback. The compensation scheme for output balance is not shown here so as not
to clutter the schematic of the proposed balun-LNA. The
impedance-matching device
amplifies the signal and provides the main noninverting signal path in CG configuration.
The CS amplifier due to
ideally shows 180 phase shift
with respect to that of the noninverting CG stage. The inherent
inverting gain of the CS stage is fed back to the gate of
to
boost the trans-conductance of
, and therefore, the required
can be reduced by the loop gain factor of
,
where
is the gain of the CS stage. Both device size and
power consumption in the CG stage is reduced as well; notice
that the reduction factor is design dependent. An additional
benefit due to the feedback is noise suppression of the CG stage
bias transistor
due to the reduced current demanded by

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2835

The input impedance of the balun-LNA in terms of device

parameters can be approximated as
(3)
where
and
are output resistance and capacitance of the
CS stage, respectively, and parasitic capacitor
arises from
the input pad,
,
, and
. The device size in the proposed
architecture is much smaller, and furthermore, the circuitry does
not suffer from the Miller effect due to
of
in contrast to
the architecture in [16].
B. Noise Analysis

Fig. 2. Simplified schematic of inductorless balun-LNA employing feedback.

with minimal voltage headroom allocated for

. With the
given bias current from input match
condition,
the only way to further minimize the noise contribution due to
is to lower its current noise source
at the expense of higher voltage headroom
. Hence,
there is a tradeoff between noise contribution due to the CG
stage bias transistor and its headroom. Low noise design dictates the high voltage supply required and both parameters
cannot be optimized at the same time. Previous works in [14]
and [15] used either noisy resistor bias with large resistance
to minimize noise at the expense of higher voltage
headroom or employed a noiseless and an area-inefficient
inductor. The proposed architecture maintains the noise and
distortion cancellation properties of the original circuit with
lower power and voltage supply. Two frequency compensation
schemes to balance gain and phase of differential outputs are
proposed and will be discussed in Section III-C.

The CGCS topology is a well-known architecture and has

been widely analyzed [22], [23]. The property of noise and distortion cancellation due to the CG stage was not clearly stated
before, and recent works in [14][16] better utilized those properties by scaling trans-conductance
of the CS stage. The
detailed analysis for the NF of previous work without the series-shunt feedback is cumbersome, and thus the final results
are given as follows without a detailed proof:

contribution

contribution

load resistor contribution

(4)
contribution
where

is the differential voltage gain expressed as

(5)

A. Input Match
The input impedance of the inductorless balun-LNA employing negative feedback at low frequency can be easily
evaluated using Blackmans formula [20], [21] as follows:
port short circuited
port open circuited

(1)

where
is the input impedance with the feedback loop
broken. Since the input impedance of the CS stage is capacitive, the real part of input impedance with the feedback loop
open is mainly defined by the
of the CG stage. For the
series-shunt (voltage-voltage) feedback used in the proposed architecture, shorting the port kills the loop gain. Equation (1) can
then be further simplified to
port open circuited

Assuming square-law behavior of the MOS transistor in satu, (4)

ration under impedance match condition
can be rewritten as

(2)

(6)
and
are the overdrive voltage of
and
where
, respectively. It is explicit from (6) that the noise contribution due to current source
has a direct tradeoff with
its voltage headroom
. A similar conclusion can be
drawn if the resistor is used for CG bias [14]. The thermal noise
of the bias resistor
can be reduced if
its value is increased at the expense of additional voltage headroom. For instance, in [14], a 350- resistor was used for CG

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Fig. 3. NF versus
bias for

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 9, SEPTEMBER 2012

scaling with and without noise contribution due to CG

,
, and
.

bias to minimize its noise contribution. RF choke in [15] could

eliminate bias-network noise contribution. Fig. 3 shows the NF
of the CGCS topology without the proposed series-shunt negative feedback. The trans-conductance scaling of the CS stage
is represented by
, and
is set to be
20 mS to ensure ideal input impedance matching with the reactive terms ignored.
is used due to the assumption that both
and
have 0.3 V of overdrive voltage
with 1.2-V supply. From the input impedance match condition
mS ,
requires 0.6 V of voltage
drop assuming the classic square-law behavior of MOS in saturation
. The noise contribution due to current mirror bias with
is appreciable and
should be carefully evaluated. Notice that noise performance
can be enhanced if the voltage headroom due to current mirror
is increased.
scaling denoted as
in addition to
scaling can further improve NF of the active-balun based on
CGCS topology. Fig. 4 clearly shows that only due to the
scaling of both can the conventional CGCS topology achieve
sufficient low NF.
The NF of the architecture employing the proposed feedback
network can be expressed as

Fig. 4. NF versus
.
and

and

Fig. 5. NF versus

at

scaling at

and

where
is the differential voltage gain of the proposed architecture, and
is the
boosting factor expressed as
(8)
(9)

contribution

contribution

load resistor contribution

(7)
contribution

The second term in (7) represents the noise contribution of

transistor
, and its noise is totally cancelled when the outputs are balanced. The third term represents the thermal noise
contribution of the CS transistor
. It is not apparent, but can
be shown that the noise due to
is minimized with larger
loop gain
. The last term accounts for the noise due to
CG stage bias, and its noise is attenuated by the factor,
when compared with the conventional topology [14],
[15]. Fig. 5 shows that, with enough loop gain
,
the proposed architecture can achieve sufficiently low NF even
if
is not scaled.

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2837

Usually the nondominant pole

due to the cascode device is an order of magnitude higher than the dominant pole
at the output of the CS stage and then it is
neglected in the following derivation. Small-signal analysis of
Fig. 6 shows that the high-frequency voltage gain at
yields

(13)
Notice from (12) and (13) that the output balance at low frequency is satisfied when noise and distortion canceling conditions are met. The signal path
generates a pole and zero
pair for the noninverting path in addition to the pole at . Since
the pole at
is common for both CG and CS
stages, the gain and phase imbalance can then be expressed as
Fig. 6. Balun-LNA with parasitic capacitance for gain and phase imbalance
analysis.

C. Gain and Phase Balance and Their Compensation

Since the balun-LNA is typically interfaced with the doublebalanced mixer, the gain and phase balance of the balun-LNA
is critical and determines several of the receiver system performances, such as power supply rejection and LO leakage. For
instance, the phase imbalance must be within 5 to suppress
LO leakage by more than 25 dBc [24]. The transfer function
from
to the noninverting and inverting output is derived to
obtain the gain and phase error of the proposed balun-LNA; the
analysis includes the parasitic capacitance shown in Fig. 6. The
transfer function from the port to
does not incur imbalance,
and thus, not considered in the derivation.
is the total capacitance due to
,
, and
.
is the parastitic effects at the
drain of
and source of
. The approximate capacitance of
and
is given by
(10)

(14)

boosting
Taking into consideration the effect of
and
scaling
, the gain
and phase imbalance due to the zero are negligible. In (14), the
dominant pole is determined by
and the zero is
pushed to high frequency by the factor
.
According to (14), high-frequency gain and phase imbalance
of the proposed architecture are primarily generated by the pole
at the output of CG stage. The capacitor
between CG and CS
stage output shown in Fig. 7 can be included to compensate for
the gain and phase imbalance. With the compensation capacitor
only (i.e.,
), the transfer functions can be derived
as (15), shown at bottom of this page, where and are as
follows:

(11)
where Miller approximation is utilized to capture the capacitance boosting due to feedback. The voltage gain from to the
CS (inverting) stage output is then derived as
(12)

(16)
(17)
Perfect balance in gain and phase can then be achieved by
equating the two transfer functions. Since the natural response
(pole) of the system are equivalent, the condition of equal zeros

(15)

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 9, SEPTEMBER 2012

TABLE I
DEVICE DIMENSION

to balance the balun-LNA. The drawback of this compensation scheme is the noise degradation due to the finite resistance
at the gate of the cascode transistor. At high frequencies, the noise contribution due to
rises considerably; its
noise factor can be expressed as
Fig. 7. Balun-LNA with gain and phase compensation network. (a)
.
(b)

(20)

in inverting and noninverting output paths leads to the following

condition:
(18)
is the ratio of
where
CG and CS amplifier trans-conductance.
The shortcoming of the proposed compensation is the dependency on the parasitic capacitance value of differential outputs
(
and
) and, therefore, the required compensation component can be either capacitive or inductive. The loading due
to the next stage (e.g., mixer) is symmetrical and usually more
dominant than the parasitic of the balun-LNA at the differential
output node in the typical implementation, and therefore,
is
negative (inductive) with
and
.
The alternative compensation scheme employs the gate resistance
in the cascode transistor. The gate resistance of
the cascode transistor is beneficial for both differential output
symmetry (balance) and stability because a capacitively degenerated transistor exhibits negative real impedance in contrast
to the positive real impedance synthesis widely adopted in inductor degenerated LNAs [25], [26]. It is well known that a parasitic inductance at the gate of a cascode transistor can lead to a
Colpitts oscillator. The gate resistance added at the gate of the
cascode transistor acts to de- the resonator and improves the
stability [27]. The voltage gain from
to the CS (inverting)
stage output with
, but
, is now expressed as

(19)
The current transfer due to the cascode transistor is a secondorder function and
is computed to balance the architecture. Without
, the nondominant pole due to the cascode
is much higher frequency than the dominant pole, as seen in
(12), and is negligible.
adds a degree of freedom used

where
is the differential voltage gain of the proposed architecture expressed in (9). A stabilizing and compensating resistor of
is chosen based on the tradeoff between
output symmetry and NF degradation due to
. In simulation, 0.3 dB of the NF increase at the upper 3-dB bandwidth frequency is observed when gate resistance compensation is employed. The design values of the balun-LNA are summarized in
Table I.
IV. MEASUREMENT RESULTS
The balun-LNA was designed in TSMC 0.13- m CMOS technology and encapsulated in a quad flat no-lead (QFN) package.
Fig. 8 shows the die photograph of the balun-LNA with a probe
buffer. The active area of the chip and balun-LNA core are only
250 m 300 m and 170 m 150 m, respectively, since no
on-chip inductor was used. To drive the 50- load (port), a probe
buffer (source follower) is employed to interface the balun-LNA
core and the port. The output impedance
of the
probe buffer is designed to be larger than 50 with smaller parasitics to extend the output matching bandwidth. Since the proposed design provides single-ended input and differential output
in a wideband fashion, a wideband off-chip balun is employed
to convert the differential outputs to the single-ended output for
-parameter, NF, and linearity measurement.
Fig. 9 shows the measured and simulated input impedance
matching
and power gain
of the balun-LNA including the probe buffer. The measured
is below 10 dB
up to 2.7 GHz and matches very well with the simulated results.
The maximum
is 7.6 dB with 3-dB bandwidth at 2 GHz.
Limited
at low frequency is due to the ac coupling capacitors used in the signal path. Bandwidth limitation at high frequency is due to the parasitic capacitors
, ,
, and
,
as well as QFN package, bonding, and printed circuit board
(PCB) parasitics. The package and bonding effects are modeled by an LC network with the assumption of 1 nH inductance
per 1 mm bonding wire length. The measured 3-dB bandwidth
of 2 GHz is lower than simulated 3-dB bandwidth of 3.5 GHz
due to the FR-4 PCB and its trace parasitics. Note that unloaded

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2839

Fig. 10. Measured

and

Fig. 8. Die photograph of the balun-LNA.

Fig. 11. Measured NF and NF of balun-LNA core versus frequency.

Fig. 9. Measured

and

voltage gain of the balun-LNA core is 9 dB higher than measured

with voltage-halving at the matched output and from
50- to 100- conversion of the balun.
Fig. 10 shows the measured and simulated reverse isolation
and output impedance matching
of the
balun-LNA core and the probe buffer. Within the 3-dB bandwidth frequency, measured
and
are better than 35
and 10 dB, respectively.
Fig. 11 shows the measured and simulated NF of the proposed
balun-LNA core and the probe buffer. Minimum NF measured
within amplifiers 3-dB bandwidth is 4.15 dB at 1.5-GHz RF
frequency, whereas the minimum NF simulated is 4.1 dB at the
same frequency. The NF of the probe buffer was not measured
separately. Simulated NF of the probe buffer was de-embedded
from the measured NF of balun-LNA core and the probe buffer.
The procedure is detailed in the Appendix. A minimum NF of
balun-LNA core is 3.8 dB after de-embedding the probe buffer
effect.
The linearity test (
and
) was performed with the
balun-LNA core and the probe buffer, as shown in Figs. 12 and

Fig. 12. Measured

at

GHz with 4-MHz two-tone space.

13. Different two-tone spacing of 4 and 20 MHz were applied

since widely spaced tones from various mobile standards dominate
in wideband systems. The measured
is invariant
to frequency spacing and shows 0 dBm within the amplifiers
3-dB bandwidth. As shown in Fig. 12, the proposed balun-LNA

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 9, SEPTEMBER 2012

TABLE II
COMPARISON TO RECENTLY PUBLISHED STUDIES

Minimum of 3-dB bandwidth and

Voltage gain
Average NF
Active area size
Simulation results with device mismatch
Single-to-differential conversion
Unloaded voltage gain of balun-LNA core
De-embedded NF of balun-LNA core
Simulation results
GHz
GHz

Fig. 13. Measured linearity (

and

dB

) versus frequency.

does not have significant higher order distortion (fifth, seventh,

and higher) up to 10 dBm of input power. For
measurement, one input tone is fixed at 1.4 GHz, while the other tone
was swept from 0.2 to 3 GHz. An
higher than 14 dBm
over the full bandwidth range is achieved. If needed, resistive
calibration to improve
can be deployed to further enhance

Fig. 14. Gain error (in decibels) and phase error (in degrees) of the proposed
balun-LNA.

the second-order distortion performance, as previously used in

the Gilbert-cell mixer [28].
Fig. 14 shows the gain and phase imbalance between noninverting and inverting outputs. The gain and phase imbalance is
within 0.5 dB and 5, respectively, when measured in the

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2841

range from 500 MHz to 2.7 GHz. Below 400 MHz, large mismatch is measured in both gain and phase, whereas this effect
was not present in simulations. We attribute the imbalance to
the unwanted resonance due to asymmetric bypass capacitors
on-chip and bond-wire inductance. The relatively small ac coupling capacitor
used for feedback also degrades the gain
imbalance at low frequency. The measured performance of the
proposed balun-LNA is summarized in Table II. Recently published works in balun-LNAs are compared with the proposed architecture. Competitive performance is obtained with the lowest
power consumption.

is the output-referred noise voltage due to the

where
balun-LNA core and
is the input-referred noise voltage
due to the probe buffer. The denominator in (A.3) is the combined effect of signal loss at the buffer output and the conversion from 50- input to 100- output. The analytical expression, (A.2), is derived at the output of the balun-LNA and the
input of probe buffer, but de-embedding buffers noise can be
applied to (A.2) with
and
at the probe buffer
output.
The NF of the standalone balun-LNA denoted as
can
then be derived from measured
and
, and the
simulated
and
as follows:

V. CONCLUSIONS
This paper has presented a balun-LNA architecture, and
provided a detailed analysis of its performance: gain, NF,
bandwidth, and differential symmetry (balance). The inherent
gain of the CS (inverting) stage is utilized to reduce the power
consumption and improve the balun-LNAs performance, while
noise and linearity cancellation properties of CGCS balun
topology are preserved. A current-mirror based biasing scheme
is used to ensure stable operation over PVT variations. The
noise contribution due to the current source is reduced with
less voltage headroom when the proposed feedback scheme
is employed. In addition, two gain and phase compensation
schemes are introduced in Section III-C.
Measurement results for the proposed balun-LNA realized
in 0.13- m CMOS demonstrate 7.6-dB maximum power gain,
4.15-dB minimum NF, and better than 0.5-dBm IIP3, while dissipating only 3 mA from 1.2-V supply. A comparison of measurement results with the recently published balun-LNAs shows
that the proposed balun-LNA without any inductors on-chip
show very competitive performances with lowest power consumption.
APPENDIX
DE-EMBEDDING NF FOR STANDALONE BALUN-LNA
Since a standalone probe buffer was not included on the measured die, the effect of the probe buffer is de-embedded employing the simulation results of the buffer. The probe buffers
input-referred voltage noise is twice the noise of the sourcefollower, which is computed as follows:
(A.1)
where
and
are the trans-conductance of the sourcefollower device and currentsource device in the probe buffer. The
NF measured in the laboratory includes the noise due to the
balun-LNA and probe buffer as well, which can be expressed
as
(A.2)

(A.3)

(A.4)

ACKNOWLEDGMENT
The authors would like to thank the Taiwan Semiconductor
Manufacturing Company (TSMC), Hsinchu, Taiwan, for support for chip fabrication. The authors would also like to thank
R. Kulkarni, Broadcom Corporation, Sunnyvale, CA, M. Onabajo, Northeastern University, Boston, MA, H. J. Jeon, Texas
A&M University, College Station, J. Wardlaw, Cirrus Logic
Inc., Austin, TX, and E. Pankratz, Silicon Laboratories Inc.,
Austin, TX, for their technical discussions.

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Jusung Kim (S10M12) received the B.S. degree

in electrical engineering (with highest honors) from
Yonsei University, Seoul, Korea, in 2006, and the
Ph.D. degree in electrical engineering from Texas
A&M University, College Station, in 2011.
In the summer of 2008, he was an Analog Integrated Circuit (IC) Design Engineer with Texas
Instruments, Dallas, TX, where he designed an RF
front-end for multistandard analog and digital TV
silicon tuners. Since January 2011, he has been with
Qualcomm Inc., San Diego, CA, where he designs
RF integrated circuit (RFIC) products for third-generation (3G) and fourth-generation (4G) cellular systems. His research interests include transceiver system
and circuit design at RF and millimeter-wave frequencies.

Jose Silva-Martinez (SM98F10) was born in

Tecamachalco, Puebla, Mxico. He received the
M.Sc. degree from the Instituto Nacional de Astrofsica Optica y Electrnica (INAOE), Puebla,
Mxico, in 1981, and the Ph.D. degree from the
Katholieke Univesiteit Leuven, Leuven, Belgium, in
1992.
From 1981 to 1983, he was with the Electrical
Engineering Department, INAOE, where he was
involved with switched-capacitor circuit design.
In 1983, he joined the Department of Electrical
Engineering, Universidad Autnoma de Puebla, where he remained until 1993.
He pioneered the graduate program on opto-electronics in 1992. In 1993, he
rejoined the Electronics Department, INAOE, and from May 1995 to December
1998, was the Head of the Electronics Department. He was a cofounder of the
Ph.D. program on electronics in 1993. He is currently with the Department of
Electrical and Computer Engineering (Analog and Mixed Signal Center), Texas
A&M University, College Station, where he is a Professor. He was the inaugural holder of the Texas Instruments Professorship-I in Analog Engineering,
Texas A&M University (20022008). He has authored or coauthored over 95
and 150 journal and conference papers, respectively, two books, and 11 book
chapters. He currently serves on the Editorial Board of six major journals. His
current research intererts are the design and fabrication of integrated circuits
for communication and biomedical applications.
Dr. Silva-Martinez was the IEEE Circuits and Systems Society (CASS) vice
president of Region 9 (19971998). He was an associate editor for the IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMSPART II: ANALOG AND DIGITAL
SIGNAL PROCESSING (19971998 and 20022003). He was an associate editor
for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSPART I: REGULAR
PAPERS (20042005 and 20072009). He was the recipient of the 2005 Outstanding Professor Award of the Electrical and Computer Engineering (ECE)
Department, Texas A&M University. He was corecipient of the MWCAS-2012
and RF-IC 2003 Best Student Paper Award. He was also the recipient of the
1990 European Solid-State Circuits Conference Best Paper Award.