Beruflich Dokumente
Kultur Dokumente
Data Sheet
FN6441.0
Features
High Efficiency Synchronous Buck Regulator With Up To
95% Efficiency
200ms Reset Timer
2.7V to 5.5V Supply Voltage
3% Output Accuracy Over-Temperature/Load/Line
1.5A Guaranteed Output Current
17A Quiescent Supply Current in PFM Mode
Selectable Forced PWM Mode and PFM Mode
Less Than 1A Logic Controlled Shutdown Current
90% Maximum Duty Cycle for Lowest Dropout at 1.5A
Over-Temperature Protection
ISL8009IRZ-T
PACKAGE
(Pb-free)
PKG.
DWG. #
Enable
Soft Discharge Disable
Small 8 Ld 2mmx3mm DFN
Applications
C/P, FPGA and DSP Power
TEMP.
RANGE
PART
(C)
MARKING
009
Ordering Information
PART NUMBER
(Note)
Pinout
ISL8009
(8 LD DFN)
TOP VIEW
VIN
LX
EN
GND
POR
VFB
SKIP
RSI
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8009
Absolute Maximum Ratings (Reference to GND)
Thermal Information
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See
Tech Brief TB379.
2. JC, case temperature location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the
typical specification are measured at the following conditions: TA = +25C, EN = VIN, RSI = SKIP = 0V,
VIN = 5V, L = 2.2H, C1 = C2 = 20F, IOUT = 0A to 1.5A, unless otherwise noted. See Typical Applications on
page 8.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Rising
2.5
2.7
Falling
2.2
2.4
INPUT SUPPLY
VIN Undervoltage Lockout Threshold
VUVLO
IVIN
17
30
15
3.7
mA
0.1
0.784
0.8
0.816
VFB = 0.75V
0.1
-3
Line Regulation
0.2
%/V
20
A/V
0.12
0.22
0.16
0.27
0.11
0.22
0.15
0.27
1.8
2.1
2.4
1.6
1.75
MHz
70
100
ns
1.1
ms
80
100
120
ISD
OUTPUT REGULATION
VFB Regulation Voltage
VVFB
IVFB
COMPENSATION
Error Amplifier Trans-Conductance
LX
P-Channel MOSFET On-Resistance
IPK
IO = 1.5A
1.35
fS
LX Minimum On Time
90
Soft-Start-Up Time
Soft-Discharge Resistor
Enable = 0
FN6441.0
July 11, 2007
ISL8009
Electrical Specifications
Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the
typical specification are measured at the following conditions: TA = +25C, EN = VIN, RSI = SKIP = 0V,
VIN = 5V, L = 2.2H, C1 = C2 = 20F, IOUT = 0A to 1.5A, unless otherwise noted. See Typical Applications on
page 8. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
0.3
150
200
275
ms
0.01
0.1
1.2
POR
Output Low Voltage
Delay Time
POR Pin Leakage Current
89.5
92
94.5
85
88
91
108
112
114
104
107
110
50
0.4
1.4
0.1
Thermal Shutdown
Pulled up to 5.5V
160
25
Pin Descriptions
VFB
VIN
Input supply voltage. Connect a 10F ceramic capacitor to
power ground.
RSI
EN
Regulator enable pin. Enable the output when driven to high.
Shutdown the chip and discharge output capacitor when driven
to low. Do not leave this pin floating.
POR
200ms timer output. At power-up or EN HI, this output is a
200ms delayed Power-Good signal for the output voltage. This
output can be reset by a low RSI signal. 200ms starts when RSI
goes to high.
SKIP
Mode Selection pin. Connect to logic high or input voltage VIN
for PFM mode; connect to logic low or ground for forced PWM
mode. Do not leave this pin floating.
This input resets the 200ms timer. When the output voltage is
within the PGOOD window, an internal timer is started and
generates a POR signal 200ms later when RSI is low. A high
RSI resets POR and RSI high to low transition restarts the
internal counter if the output voltage is within the window,
otherwise the counter is reset by the output voltage condition.
Exposed Pad
The exposed pad must be connected to the GND pin for proper
electrical performance. The exposed pad must also be
connected to as much as possible for optimal thermal
performance.
LX
Switching node connection. Connect to one terminal of
inductor.
GND
System ground.
FN6441.0
July 11, 2007
ISL8009
Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25C, VVIN = 5V, EN = VIN,
RSI = SKIP = 0V, L = 2.2H, C1 = 20F, C2 = 20F, IOUT = 0A)
100
100
90
90
70
2.5VOUT - PWM
1.5VOUT - PWM
60
EFFICIENCY (%)
EFFICIENCY (%)
80
1.8VOUT - PWM
50
1.2VOUT - PWM
40
30
20
2.5VOUT - PFM
80
1.5VOUT - PFM
1.8VOUT - PFM
70
1.2VOUT - PFM
60
50
10
0
0.00
0.25
0.50
0.75
1.00
1.25
40
0.05
1.50
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
100
100
90
90
70
2.5VOUT - PWM
1.5VOUT - PWM
60
3.3VOUT - PWM
1.8VOUT - PWM
50
EFFICIENCY (%)
EFFICIENCY (%)
80
40
30
1.2VOUT - PWM
20
2.5VOUT - PFM
80
3.3VOUT - PFM
1.5VOUT - PFM
70
1.8VOUT - PFM
60
1.2VOUT - PFM
50
10
0
0.00
0.25
0.50
0.75
1.00
1.25
40
0.05
1.50
0.15
0.25
5VIN - PWM
2.8VIN - PFM
1.24
1.22
1.20
1.18
1.16
1.14
3.3VIN - PFM
2.8VIN - PWM
1.10
0.00
0.25
0.50
0.75
0.75
2.8VIN - PWM
1.52
1.00
5VIN - PWM
2.8VIN - PFM
1.50
1.48
5VIN - PFM
3.3VIN - PWM
1.25
0.65
1.54
5VIN - PFM
1.12
0.55
1.56
3.3VIN - PWM
OUTPUT VOLTAGE (V)
1.26
0.45
1.30
1.28
0.35
1.50
1.46
0.00
0.25
0.50
0.75
1.00
3.3VIN - PFM
1.25
1.50
FN6441.0
July 11, 2007
ISL8009
Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25C, VVIN = 5V, EN = VIN,
1.86
2.60
1.85
2.55
1.84
1.83
2.8VIN - PWM
5VIN - PWM
1.82
2.8VIN - PFM
3.3VIN - PWM
1.81
1.80
1.79
5VIN - PFM
1.78
1.77
0.00
0.25
1.25
2.50
2.45
2.40
3.3VIN - PWM
5VIN - PFM
2.35
2.30
2.20
0.00
1.50
0.25
0.50
0.75
1.00
OUTPUT LOAD (A)
1.25
1.50
3.39
0.7
4VIN - PWM
4VIN - PFM
5.5VIN - PWM
3.37
OUTPUT VOLTAGE (V)
3.3VIN - PFM
2.25
3.3VIN - PFM
0.50
0.75
1.00
OUTPUT LOAD (A)
5VIN - PWM
3.35
3.33
3.31
5VIN - PWM
5.5VIN - PFM
5VIN - PFM
3.29
3.3VIN - PWM
0.6
5VIN - PWM
0.5
2.8VIN - PWM
0.4
2.8VIN - PFM
0.3
0.2
3.3VIN - PFM
0.1
5VIN - PFM
3.27
0.00
0.25
0.50
0.75
1.00
OUTPUT LOAD (A)
1.25
0
0.00
1.50
3.3VIN - PWM
1.50
0.5
2.8VIN - PFM
0.4
2.8VIN - PWM
0.3
5VIN - PWM
3.3VIN - PFM
0.1
3.3VIN - PWM
0.6
POWER DISSIPATION (W)
1.25
0.7
0.6
0.5
2.8VIN - PFM
0.4
2.8VIN - PWM
0.3
0.2
5VIN - PWM
3.3VIN - PFM
0.1
5VIN - PFM
0
0.00
0.50
0.75
1.00
OUTPUT LOAD (A)
0.7
0.2
0.25
0.25
0.50
0.75
1.00
OUTPUT LOAD (A)
5VIN - PFM
1.25
1.50
0
0.00
0.25
0.50
0.75
1.00
OUTPUT LOAD (A)
1.25
1.50
FN6441.0
July 11, 2007
ISL8009
Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25C, VVIN = 5V, EN = VIN,
RSI = SKIP = 0V, L = 2.2H, C1 = 20F, C2 = 20F, IOUT = 0A) (Continued)
0.6
0.6
0.5
2.8VIN - PWM
2.8VIN - PFM
0.4
0.3
3.3VIN - PWM
0.2
5VIN - PWM
5VIN - PFM
0.1
0
0.00
0.4
0.3
0.50
0.75
1.00
OUTPUT LOAD (A)
1.25
0.2
4VIN - PFM
5VIN - PWM
0.1
0
0.00
1.50
0.25
0.50
0.75
1.00
OUTPUT LOAD (A)
1.25
1.50
45
2.5
0.75A LOAD
40
NO LOAD- PWM
35
5.5VIN - PFM
5.5VIN - PWM
5VIN - PFM
3.3VIN
IN - PFM
0.25
4VIN - PWM
0.5
30
25
20
15
NO LOAD - PFM
10
2.0
1.5
1.5A LOAD
1.0
NO LOAD
0.5
5
0
2.75
3.25
3.75
4.25
4.75
0.0
2.0
5.25
VIN (V)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
NO LOAD
1.5
0.75A LOAD
1.0
1.5A LOAD
LX 2V/DIV
0.5
VOUT RIPPLE
20mV/DIV
0.0
-0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
IL 0.2A/DIV
FN6441.0
July 11, 2007
ISL8009
Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25C, VVIN = 5V, EN = VIN,
RSI = SKIP = 0V, L = 2.2H, C1 = 20F, C2 = 20F, IOUT = 0A) (Continued)
LX 2V/DIV
VOUT RIPPLE
20mV/DIV
LX 2V/DIV
IL 0.5A/DIV
VOUT RIPPLE
20mV/DIV
IL 0.2A/DIV
LX 2V/DIV
LX 2V/DIV
VOUT RIPPLE
50mV/DIV
IL 1A/DIV
VOUT RIPPLE
50mV/DIV
IL 1A/DIV
EN 2V/DIV
EN 2V/DIV
VOUT
1V/DIV
1V PRE-BIASED
VOUT
0.5V/DIV
IL 1A/DIV
POR 2V/DIV
IL 1A/DIV
FN6441.0
July 11, 2007
ISL8009
Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25C, VVIN = 5V, EN = VIN,
RSI = SKIP = 0V, L = 2.2H, C1 = 20F, C2 = 20F, IOUT = 0A) (Continued)
EN 2V/DIV
EN 2V/DIV
VOUT 0.5V/DIV
VOUT 1V/DIV
IL 1A/DIV
IL 1A/DIV
POR 1V/DIV
LX 2V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 1A/DIV
IL 1A/DIV
Typical Applications
L
2.2H
OUTPUT
1.8V TO 1.5A
LX
C2
20F
C1
20F
R2
124k
GND
ISL8009
EN
R3
100k
R1
100k
POR
VFB
SKIP
RSI
FN6441.0
July 11, 2007
ISL8009
Block Diagram
SKIP
SOFT- START
BANDGAP
0.8V
3pF
VIN
OSCILLATOR
EAMP
EN
SHUTDOWN
30pF
300k
SHUTDOWN
+
COMP
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
DRIVER
LX
GND
VFB
SLOP
SLOPE
E
COMP
COMP
0.864V
+
CSA1
+
OCP
0.85V
+
0.736V
+
SKIP
POR
200ms
DELAY
0.17V
ZERO - CROSS
SENSING
RSI
0.2V
SCP
+
Theory of Operation
The ISL8009 is a step-down switching regulator optimized
for battery-powered handheld applications. The regulator
operates at 1.6MHz fixed switching frequency under heavy
load condition to allow small external inductor and capacitors
to be used for minimal printed-circuit board (PCB) area. At
light load, the regulator reduces the switching frequency,
unless forced to the fixed frequency to minimize the
switching loss and to maximize the battery life. The
quiescent current when the output is not loaded is typically
only 17A. The supply current is typically only 0.1A when
the regulator is shutdown.
FN6441.0
July 11, 2007
ISL8009
block only affects the operation during the start-up and will
be discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error
signal to a current output. The voltage loop is internally
compensated with the 30pF and 300k RC network. The
maximum EAMP voltage output is precisely clamped to the
bandgap voltage (1.172V).
VEAMP
VCSA1
Duty
DUTY
Cycle
CYCLE
Mode Control
The ISL8009 has a SKIP pin that controls the operation
mode. When the SKIP pin is driven to low or shorted to
ground, the regulator operates in a forced PWM mode. The
forced PWM mode remains the fixed PWM frequency at light
load instead of entering the skip mode.
IL
VOUT
Overcurrent Protection
FIGURE 31. PWM OPERATION WAVEFORMS
SKIP Mode
The ISL8009 enters a pulse-skipping mode at light load to
minimize the switching loss by reducing the switching
frequency. Figure 32 illustrates the skip-mode operation. A
zero-cross sensing circuit shown in Figure 30 monitors the
N-MOSFET current for zero crossing. When 8 consecutive
cycles of the N-MOSFET crossing zero are detected, the
regulator enters the skip mode. During the 8 detecting
cycles, the current in the inductor is allowed to become
negative. The counter is reset to zero when the current in
any cycle does not cross zero.
Once the skip mode is entered, the pulse modulation starts
being controlled by the SKIP comparator shown in Figure 30.
Each pulse cycle is still synchronized by the PWM clock. The
P-MOSFET is turned on at the clock and turned off when its
current reaches 20% of the current limit value (0.2V at the
CSA output). As the average inductor current in each cycle
Short-Circuit Protection
A short-circuit protection SCP comparator monitors the VFB
pin voltage for output short-circuit protection. When the VFB
is lower than 0.2V, the SCP comparator forces the PWM
oscillator frequency to drop to 1/3 of the normal operation
value. This comparator is effective during start-up or an
output short-circuit event.
RSI/POR Function
When powering up, the open-collector Power-On-Reset
output holds low for about 200ms after VO reaches the
preset voltage. When the active-HI reset signal RSI is
issued, POR goes to low immediately and holds for the
CLOCK
Clock
88CYCLES
Cycles
CURRENT
LIMIT
Current Limit
IL
LOAD
LoadCURRENT
Current
0
NOMINAL++1.5%
Nominal
1.5%
VOUT
NOMINAL
Nominal
10
FN6441.0
July 11, 2007
ISL8009
same period of time after RSI comes back to LOW. The
output voltage is unaffected. (Please refer to Figure 33).
When the function is not used, connect RSI to ground and
leave the pull-up resistor, R4, open at the POR pin.
The POR output also serves as a 200ms delayed Power
Good signal when the pull-up resistor, R4, is installed. The
RSI pin needs to be directly (or indirectly through resistor,
R5) connected to ground for this to function properly.
Thermal Shutdown
The ISL8009 has built-in thermal protection. When the
internal temperature reaches +160C, the regulator is
completely shutdown. As the temperature drops to +130C,
the ISL8009 resumes operation by stepping through a softstart-up.
Applications Information
Output Inductor and Capacitor Selection
VO
MIN
25ns
RSI
200ms
200ms
POR
UVLO
When the input voltage is below the under-voltage lock out
(UVLO) threshold, the regulator is disabled.
Soft-Start-Up
The soft start-up eliminates the in-rush current during the
start-up. The soft-start block outputs a ramp reference to
both the voltage loop and the current loop. The two ramps
limit the inductor current rising speed as well as the output
voltage speed so that the output voltage rises in a controlled
fashion. At the very beginning of the start-up, the output
voltage is less than 0.2V; hence the PWM operating
frequency is 1/3 of the normal frequency.
V O 1 ---------
V IN
I = --------------------------------------L fS
(EQ. 1)
Power MOSFETs
VOUT
COUT
0.8V
10F
1.0H~2.2H
1.2V
10F
1.2H~2.2H
Duty Cycle
1.6V
10F
1.8H~2.2H
1.8V
10F
1.8H~3.3H
2.5V
10F
1.8H~3.3H
3.3V
10F
1.8H~4.7H
3.6V
10F
1.8H~4.7H
Enable
The Enable (EN) input allows the user to control the turning on
or off of the regulator for purposes such as power-up
sequencing. When the regulator is enabled, there is typically a
600s delay for waking up the bandgap reference, then the
soft-start-up begins. When the regulator is disabled, the
P-MOSFET and the N-MOSFET are turned off immediately.
The 100 soft discharge resistor from LX to GDN is
activated and pulls the output to 0V.
11
FN6441.0
July 11, 2007
ISL8009
Output Voltage Setting Resistor Selection
Layout Recommendation
R 2
V O = 0.8 1 + -------
R 3
(EQ. 2)
12
FN6441.0
July 11, 2007
ISL8009
Dual Flat No-Lead Plastic Package (DFN)
L8.2x3
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
2X
SYMBOL
0.15 C A
A
2X
0.15 C B
MIN
0.80
0.90
1.00
0.05
0.32
5,8
1.75
7,8
1.90
7,8
0.20 REF
0.20
D
D2
INDEX
AREA
B
0.10
SIDE VIEW
C
SEATING
PLANE
1.65
3.00 BSC
1.65
e
//
0.25
2.00 BSC
1.50
E
E2
TOP VIEW
NOTES
b
E
MAX
A1
A3
NOMINAL
1.80
0.50 BSC
0.20
0.30
0.40
0.50
0.08 C
Nd
A3
2
3
Rev. 0 6/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
D2
(DATUM B)
D2/2
1
6
INDEX
AREA
NX k
(DATUM A)
E2
E2/2
NX L
N N-1
NX b
e
5
0.10
(Nd-1)Xe
REF.
M C A B
BOTTOM VIEW
CL
(A1)
NX (b)
5
SECTION "C-C"
C C
TERMINAL TIP
e
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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13
FN6441.0
July 11, 2007