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AnEnergyEfficientATMSystemUsingAES
Processor
AliNawaz*1,FakirSharifHossain2,KhanMd.Grihan3
DepartmentofElectricalandElectronicEngineering
InternationalIslamicUniversityChittagong,Dhaka,Bangladesh
*1
just.piash@gmail.com;2sharifo16@yahoo.com;3grihankhan@yahoo.com
Abstract
ThispaperpresentsahighlysecuredATMbankingsystem
using an optimized Advanced Encryption Standard (AES)
algorithm. Two levels of security are provided in this
proposed design. Firstly we consider the security level at
the client side by providing biometric authentication
scheme along with a password of 4digit long. Biometric
authentication is achieved by considering the fingerprint
image of the client. Secondly we ensure a secured
communication link between the client machines to the
bank server using an optimize energy efficient AES
processor.Thefingerprintimageisthedataforencryption
processand4digitlongpasswordisthesymmetrickeyfor
the encryption process. To get a low power consuming
ATMmachine,anoptimizedAESalgorithmisproposedin
this paper. In this system biometric and cryptography
techniquesareusedtogetherforpersonauthentication
to improve the security level . The proposed design is
secured against all kinds of attacks. The design of the
processor is simulated on the FPGA platform. Simulation
results ensure its proper functionality. The speed
performance of the processor is also analysed and
compared with that of other researchers in ASIC
technologywhichalsoprovesitssuperiorityoverthem.
Keywords
Biometric; ATM; Fingerprint; Cryptography; AES Processor;
LowPower
Introduction
Nowadays security becomes a great issue in every
part of life. Passing of information faces massive
problems due to various types of attacks into the
communicationlink.Alotofresearchersareworking
inthefieldofcommunicationsecurity.Manysecurity
algorithms are available to protect information from
beinghacked.
The biometric authentication process adds a new
dimension of security for any person sensitive to
authentication.Thispaperpresentsasecuredandan
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ElectricalEngineeringResearch(EER)Volume1Issue2,April2013
FIG.1ACONVENTIONALATMSYSTEM
MixColumns:Thisisasubstitutionthatmakesuseof
arithmetic over GF (28), with the irreducible
polynomialm(x)=x8+x4+x3+x+1.Forencryption
and decryption, this function is indicated by
MixColumns()andInvMixColumns()respectively.
ATMfirstcameintouseinDecember1972intheUK.
IBM 2984 was designed for request of Lloyds Bank.
ATMistypicallyconnecteddirectlytotheirhostsor
ATM Controller via either ADSL or dialup modem
overatelephonelineordirectlyviaaleasedline.For
transaction security all communication traffic
between ATM and transaction process is encrypted
by cryptography. Nowadays, most of ATM uses a
MicrosoftOSprimarilyWindowsXPProfessionalor
WindowsXPEmbeddedorLinux.
Fingerprint
Fingerprint is a characteristic which is unique for
each person. Every fingerprint contain unique
identifiable piece of information. The uniqueness in
eachfingerprintisduetothepeculiargeneticcodeof
DNAineachperson.Ridgesandvalleysaretheparts
of fingerprint that provide friction for the skin. The
FIG.2AESENCRYPTIONANDDECRYPTIONS
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ElectricalEngineeringResearch(EER)Volume1Issue2,April2013
LowPowerDesignofAESProcessor
TogetlowpowerAESprocessorforminimizingthe
overall power consumption of the ATM system, we
proposetheSboximplementationinGaliosField(24)
2 instead of GF (28). Sbox is the most costly
transformation in AES, on the aspect of both time
and area. Rijme one of the references suggested an
alternative approach to calculate multiplicative
inverses in SBox. Since then, the relevant research
has proved that the composite field GF(24) 2 based
arithmetic provides the least gate count and the
shortest critical path for calculating multiplicative
inverseofabyte,whichisthekeystepinSBox.This
conversion involves an isomorphic map function
before and after inversion in each round. In our
designwetake128bitkeyfortheAESprocessor,so
it needs ten map functions for each block (128bit)
from finite field to composite field and ten inverse
mapfunctionsforencryption.Andthekeygenerator,
also has SBoxes, is included, another ten mappings
and ten inverse mappings are needed. Fig.5 shows
themappingofGF(24)2.
FIG.3FINGERPRINTIMAGEANDITSPROCESSINGSTEPS
FIG.5MULTIPLICATIVEINVERSIONMAPPINGINGF(24)2
Tosavetheoverheadcausedbymapping,ourdesign
converts the whole AES algorithm from GF(28) to
GF(24) 2 , which needs only one forward mapping
before the initial round and one backward mapping
after the final round. Only one forward mapping is
neededforthekeyschedule.
Proposed System and Performance
ProposedSystem
FIG.4FINGERPRINTIMAGEPROCESSINGSTEPS
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ElectricalEngineeringResearch(EER)Volume1Issue2,April2013
FIG.7IMAGEACQUISITIONDEVICE
FIG.8ACKNOWLEDGEMENTDEVICE
FIG.6PROPOSEDATMSYSTEM
HardwareImplementation
This proposed system has two hardwires; firstly an
imageacquisitiondevice.Fig.7illustratestheimage
acquisitiondevice.Itconsistsofaprismandwebcam
Performance
The proposed system is one of the fastest and
secured among the worlds existing ATM systems.
There are two reasons; firstly acquisition device
capturesimageaccurately.Theerrorofthedeviceis
negligible. Secondly using AES with low power
consumed high speedy AES processor makes the
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ElectricalEngineeringResearch(EER)Volume1Issue2,April2013
Symposium
Conclusion
IEEEComputerSociety,2005.
on
FieldProgrammable
Custom
K.
study
implementation
of
on
highspeed
cryptographic
hardware
algorithm
Characteristics
of
Cryptographic
REFERENCES
Ali,L.,Roy,N.andFaisal,F.F.DesignofaHighSpeed
and
Low
Latency
Cryptoprocessor
ASIC
Algorithm,FPL2003,LNCS2778,pp.292302,2003.
Satoh et al. A Compact Rijndeal HardWare Architecture
with Sbox Optimization ASIACRYPT 2001, LNCS
SemiconductorElectronics,2008.ICSE2008.
Brian,Milligan(25June2007),Themanwhoinventedthe
cashmachine,BBCNews,Retrieved26April2010.
2248,pp.239154,2001.
Satoh, A., Morioka, S. and Takano, K. et al. A compact
Rijndael
powerthroughput
tradeoff
SchoolofElectricalEngineeringandComputerScience,
AlgorithmInternational
standard
(AES).
Available:
http://csrc.nist.gov/publication/drafts/dfipsAES.pdf.
Gaj, K. and Chodowiec, P. Fast Implementation and Fair
Comparison of the Final Candidates for Advanced
Encryption Standard Using Field Programmable Gate
Arrays,CTRSA2001,LNCS2020,pp.8499,2001.
Hodjat, A., Verbauwhede, I., A 21.54 Gbits/s Fully
Pipelined AES Processor on FPGA, 12th IEEE
46
Journal
of
Computer
Applications(09758887)Volume3No.6,June2010
Standaert et al. Efficient Implementation of Rijndael
EncryptioninReconfigurableHardware:Improvements
and Design Tradeoffs. CHES 2003, LNCS 2779, pp.
USA,Availableonline16December2009.
(FIPS PUB) 197, National Institute of Standards and
SBox
WashingtonStateUniversity,Pullman,WA991642752,
Federal Information Processing Standards Publication
with
in
executingtheAdvancedEncryptionStandardalgorithm
architecture
optimization,InProc.
hardware
334350,2003.
ElectricalEngineeringResearch(EER)Volume1Issue2,April2013
Cryptography,RenewableEnergy,NetworkSecurity,VLSI
andEmbeddedsystemdesign.
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