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inverter logic

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You are on page 1of 34

Dinesh Sharma

Microelectronics Group, EE Department

IIT Bombay, Mumbai

A simple model

1.4

Vg = 3.5

1.2

1.0

3.0

2

Ids = K (Vgs VT )Vds 12 Vds

0.8

0.6

2.5

0.4

2.0

0.2

0.0 0.5

1.5

1.0

1.0 1.5 2.0 2.5 3.0 3.5

Drain Voltage (V)

4.0 4.5

Ids = K

(Vgs VT )2

2

saturation region.

(This is somewhat oversimplified.)

1.4 1.6

0.6

0.8 1.0 1.2

s

define Vdss

0.0

0.2

0.4

0.0

1.0

2.0

3.0

4.0

Drain Voltage (V)

5.0

and Idss

for Vgs > VT and Vds > Vdss Ids =

2(V

V

)

gs

T

1

VE 1 +

VE

Vgs VT

(Vgs VT ) 1

2VE

1 2

K (Vgs VT )Vdss Vdss

2

1 2

K (Vgs VT )Vds Vds

2

V + VE

Idss d

Vdss + VE

controlled by input signals.

and vice versa.

simultaneously, there is no static power consumption.

CMOS Inverter

The simplest of CMOS logic structure is the inverter.

Vdd

Vi

mapping them to an equivalent inverter.

made equivalent to the pMOS of the

inverter.

made equivalent to the nMOS of the

inverter.

geometries of the pull up and pull down

networks to single transistors.

Vo

Static Characteristics

The range of input voltages can be divided into

several regions.

VOH

VOL

V

iL

iH

VOH

VOL

V

iL

iH

output voltage = Vdd .

with input = 0 and output = 1.

VOH

VOL

V

iL

iH

enough so that the n channel transistor is

in saturation, and the p channel transistor

is in the linear regime.

adjust itself such that the currents through

the n and p channel transistors are equal.

channel transistor is Vdd - Vi , and therefore the over

voltage on its gate is Vdd - Vi - VTp .

value Vdd -Vo .

Therefore,

Id

=

1

Vo ) (Vdd Vo )2

2

Kn

(Vi VTn )2

2

Then we can solve the quadratic equation:

1

2

Id = Kp (Vdd Vi VTp )(Vdd Vo ) (Vdd Vo )

2

Kn

=

(V VTn )2

2 i

q

So Vo = Vi + VTp + (Vdd Vi VTp )2 (Vi VTn )2

If Kn = Kp ; ( = 1),

q

Vo = (Vi + VTp ) + (Vdd VTn VTp )(Vdd 2Vi + VTn VTp )

for Vi

2

when the input voltage is at

Vi =

1+

Vdd

Vi

Vo

3.0

independent of their drain voltages.

equating drain currents.

Vo in the range

VoH

Output Voltage

2.5

2.0

1.5

V +V

Tn Tp

1.0

0.5

VoL

0.0

0.0

0.5

1.0

1.5

2.0

ViL

ViH

Input Voltage

2.5

3.0

Vi VTn Vo Vi + VTp

when

Vi =

Vdd +

VTn VTp

1+

exactly,

output voltages in the range

Vi VTn Vo Vi + VTp

Thus the transfer curve of an inverter shows a drop of VTn + VTp

at a voltage near Vdd /2.

As we increase Vi further, so that

1+

both transistors are still on, but nMOS enters the linear regime

while pMOS is saturated. Equating currents in this condition,

Id

Kp

(V Vi VTp )2

2 dd

1 2

= Kn (Vi VTn )Vo Vo

2

(Vdd Vi VTp )2

1 2

Vo (Vi VTn )Vo +

=0

2

2

(Vdd Vi VTp )2

1 2

Vo (Vi VTn )Vo +

=0

2

2

This has solutions

Vo = (Vi VTn )

(Vi VTn )2

(Vdd Vi VTp )2

q

Vo = (Vi VTn ) (Vdd VTn VTp )(2Vi Vdd VTn + VTp )

VOH

VOL

V

iL

iH

Vdd - VTp , the p channel transistor turns

off, while the n channel conducts

strongly.

with input = 1 and output = 0.

Noise Margins

correctly at the input of next stage even in the presence of

noise.

For the high level, we require that the output of one stage

should still be interpreted as high at the input of the next

gate even when pulled down a little due to noise.

VoH ViH is the high noise level.

Logic Levels

insensitive to the exact analog voltage at the input.

small) are suitable for digital logic.

o

( V

Vi ) is -1.0.

(ViL ,VoH ) and (ViH ,VoL ).

The region to the left of ViL and to the right of ViH has

o

| V

Vi | < 1, and is suitable for digital operation.

Vo

Vi

is

Vdd

Vi

Vo

we shall use the expressions derived for

= 1 to keep the algebra simple.

n channel transistor is saturated and the p

channel transistor is in its linear regime.

low, the n channel transistor is in its linear

regime, while the p channel transistor is

saturated.

for (ViL ,VoH ), n channel transistor is saturated, while the p

channel transistor is in its linear regime.

q

Vo = (Vi + VTp ) + (Vdd VTn VTp )(Vdd + VTn VTp 2Vi )

From this, we evaluate

Vo

Vi

Vo

= 1 = 1

Vi

Vdd + VTn VTp 2Vi

This gives

ViL =

VoH

8

7Vdd + VTn + VTp

Vdd VTn VTp

= Vdd

8

8

When the input is high, we should use the equation for nMOS

linear and pMOS saturated.

q

Vo = (Vi VTn ) (Vdd VTn VTp )(2Vi Vdd VTn + VTp )

Differentiating with respect to Vi gives

s

Vdd VTn VTp

Vo

= 1 = 1

Vi

2Vi Vdd VTn + VTp

ViH

VoL =

8

Vdd VTn VTp

8

VoH ViH =

4

ViL VoL =

4

values for VTn and VTp .

Dynamic Characteristics

that only one of the two transistors in the inverter is on.

calculated by slope considerations.

of this lecture.

Rise time

Vdd

is off, while the p channel transistor is on.

From Kirchoffs current law at the output node,

ViL

Idp = C

Vo

so,

dVo

dt

dt

dVo

=

C

Idp

rise

=

C

VoH

dVo

Idp

rise

=

C

VoH

dVo

Idp

saturation.

if VoH > ViL + VTp (which is normally the case), the integration

range can be broken into saturation and linear regimes. Thus

rise

C

ViL +VTp

dVo

Kp

2 (Vdd

0

VoH

ViL +VTp

Kp (Vdd

ViL VTp )2

dVo

ViL VTp )(Vdd Vo ) 21 (Vdd Vo )2

rise =

+

2C(ViL + VTp )

Kp (Vdd ViL VTp )2

Vdd + VoH 2ViL 2VTp

C

ln

Kp (Vdd ViL VTp )

Vdd VoH

load capacitor.

its linear range.

have taken a charge time of

= RC ln

Vdd VoH

Fall Time

Vo

Vi H

is off, while the n channel transistor is on.

From Kirchoffs current law at the output node,

dVo

dt

Separating variables and integrating from the initial voltage

(= Vdd ) to some terminal voltage VoL gives

Idn = C

fall

=

C

voL

Vdd

dVo

Idn

Fall time

fall

=

C

voL

Vdd

dVo

Idn

to Vi - VTn . Below this, the transistor will be in its linear regime.

We can divide the integration range in two parts.

fall

C

=

=

Vi VTn

Vdd

Vdd

Vi VTn

Vi VTn

VoL

dVo

Idn

VoL

Vi VTn

dVo

Kn

2

2 (Vi VTn )

dVo

Idn

dVo

Kn [(Vi VTn )Vo 21 Vo2

Fall time

V Vi + VTn

2(Vi VTn ) VoL

fall

1

= Kdd

ln

+

n

2

C

K

(V

V

)

VoL

n

i

Tn

2 (Vi VTn )

The first term represents the time taken to discharge at

constant current in the saturation regime, whereas the second

term is the quasi-resistive discharge in the linear regime.

Noise margins are given by

VoH ViH

ViL VoL =

4

Vdd + 3VTn VTp

4

consumption. However, the noise margin becomes worse.

higher threshold voltages. However, this will reduce

speeds.

dissipation.

margins.

discharge behaviour and equal noise margins for high and

low logic values.

values of VTn and VTp .

transistor geometries if speed requirements and

technological parameters are given.

loading can become significant.

capacitance as

CLoad = Cext + Kn

where we have assumed that = Kn /Kp is constant. is a

technological constant.

voltages. Once these values are calculated, the geometry

can be determined.

load capacitance, K/C becomes constant and becomes

geometry independent. There is no advantage in using

wider transistors in this regime to increase the speed. It is

better to use multi-stage logic with tapered buffers in this

regime.

Once the basic CMOS inverter is designed, other logic gates

can be derived from it. The logic has to be put in a canonical

form which is a sum of products with a bar (inversion) on top.

channel transistors in series and the corresponding p

channel transistors in parallel.

and the p channel transistors in series.

(n or p) put in series.

parallel.

Vdd

A

pair is in parallel with C which is in series

with a parallel combination of D and E.

pair is in series with C which is in parallel

with a series combination of D and E.

D

C

E

Out

CMOS summary

Vdd

Vi

design style.

n pull down network as well as to the p

pull up network.

high.

p channel transistors cannot be placed

close together as these are in different

wells which have to be kept well separated

in order to avoid latchup.

Vo

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