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BSNL
TTA | JE 2016 Microprocessors Test Paper
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BSNL
TTA | JE 2016 - Microprocessors - Test Paper
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1 points

1. Question
Which stack in 8085?
1.

FILO

2.

LILO

3.

FIFO

4.

LIFO
1 points

2. Question
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The mcs 51 architecture supports_______

1.

transmission and reception of data using serial communication interface

2.

serial transmission and reception

3.

simultaneous transmission and reception

4.

all of the mentioned

1 points

3. Question
The instruction that subtracts 1 from the contents of the specied register/memory location is
1.

SUBB

2.

SUB

3.

DEC

4.

INC
1 points

4. Question
Which of the processors stack does not contain the top-down data structure?
1.

8086

2.

8051

3.

80286

4.

80386
1 points

5. Question
The 8288 bus controller chip derives the signals____
1.

DEN

2.

ALE

3.

DT/R(active low)

4.

all of the mentioned

1 points

6. Question
In a typical microcomputer data transfer takes place between____
1.

memory and I/O devices

2.

P and I/O devices

3.

all of the mentioned

4.

P and memory
1 points

7. Question
The unit that predicts the locations from where the next instruction bytes are fetched is ______
1.

execution module

2.

trace cache

3.

front end branch predictor

4.

instruction decoder

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1 points

8. Question
Which processor structure is pipelined_______
1.

All x 85 processor

2.

Aii x80 processor

3.

Pentium

4.

All x 86 processor
1 points

9. Question
8088 diers 8086 in
1.

Supports of max/min mode

2.

Address capability

3.

Data width on the output

4.

Supports of Co processor
1 points

10. Question
The master processor stores the result buers on to the hard disk with the lename as
1.

.OBJ le

2.

.EXE le

3.

.OBJ le with extension .RES

4.

.EXE le with extension .RES

1 points

11. Question
The unit that is needed for virtual mode 80386, only to run the 8086 programs, which require more than 1 Mbyte of memory for
memory management functions, is_____
1.

execution unit

2.

paging unit

3.

central processing unit

4.

segmentation unit
1 points

12. Question
The pin of minimum mode AD0-AD15 has ____________ address
1.

4 bit

2.

16 bit

3.

20 bit

4.

32 bit
1 points

13. Question
Acess time is faster for_______
1.

SRAM

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2.

ROM

3.

DRAM

4.

EPROM
1 points

14. Question
In complex instructions, when the instruction needs to be translated into more than 4 micro-operations, then the decoder
transfers the task to _______
1.

trace cache

2.

front end branch predictor

3.

none

4.

microcode ROM
1 points

15. Question
8086 is interfaced to two 8259s (programmable Interval Timer) .If 8259s are in master slave conguration , the number of
interrupts available to the 8086 microprocessor is______
1.

15

2.

3.

64

4.

16
1 points

16. Question
Which interrupts has highest Priority
1.

RST 7.5

2.

RST6.5

3.

INTR

4.

TRAP
1 points

17. Question
The receive buer of serial data buer is a
1.

serial-in parallel-out register

2.

parallel-in serial-out register

3.

serial-in serial-out register

4.

parallel-in parallel-out register

1 points

18. Question
Trace cache can store the micro-ops upto a range of ______
1.

6 K decoded micro-ops

2.

8 K decoded micro-ops

3.

12 K decoded micro-ops

4.

10 K decoded micro-ops

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1 points

19. Question
If a 1M1 DRAM requires 4 ms for a refresh and has 256 rows to be refreshed, no
more than __________ of time must pass before another row is refreshe
1.

64 ms

2.

15.625 s

3.

4 ns

4.

0.5 ns.
1 points

20. Question
The register that provides control and status information about serial port is______
1.

IE

2.

PCON and SCON

3.

IP

4.

TSCON
1 points

21. Question
BURST refresh in DRAM is also called as____
1.

Distributed Refresh

2.

Concentrated Refresh

3.

Hidden Refresh

4.

None
1 points

22. Question
The register that can be used as a scratch pad is
1.

B register

2.

Accumulator

3.

Data register

4.

Accumulator and B register

1 points

23. Question
The high level language program before ready to be executed must go through various process except
1.

Linking

2.

Translation

3.

Controlling

4.

Loading
1 points

24. Question
In 8086 the following has the higest priority among all the interrupts____
1.

OVER FLOW

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2.

DIV

3.

NMI

4.

TYPE 255
1 points

25. Question
The number of bits transmitted or received per second is dened as_______.
1.

transmission rate

2.

reception rate

3.

transceiver rate

4.

baud rate
1 points

26. Question
DS directive in 8085
1.

forces the assembler to reserve one byte of memory

2.

forces the assembler to reserve a specied number of consecutive bytes in the memory

3.

forces the assembler to reserve a specied number of bytes in the memory

4.

none of the above

1 points

27. Question
When was the rst 8-bit microprocessor introduced?
1.

1974

2.

1969

3.

1979

4.

1985
1 points

28. Question
To inform 80387 that the CPU wants to communicate with NPS1, the NPS1 line is directly connected to________
1.

A31

2.

A30

3.

M/IO

4.

D31
1 points

29. Question
.Microprocessor is the ______ of the computer and it perform all the computational tasks
1.

main

2.

important

3.

simple

4.

heart
1 points

30. Question
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If the microcontroller is expected to communicate in multiprocessor system, then the required condition is_________
1.

SM1 is set

2.

REN is setc

3.

SM0 is set

4.

SM2 is set

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