TCAM BIST

Overview

March Test

Avago Technologies provides a BIST solution with various

TCAM and BCAM offerings. The nature of the CAMs makes
BIST a necessity as the macros cannot be tested using
standard stuck-at scan test methodology. The purpose of
BIST is to put the CAM arrays through a series of tests that
will determine if a manufacturing flaw is present in the die
being tested. The BIST tests for a range of static and
dynamic faults including back to back reads and back to
back writes.

The first part of the BIST is the March Test. March testing is
done to determine if a manufacturing defect is present
within the array. The March tests treat the TCAM as it would
a standard memory. There are no compare operations
performed during the March test. Only read and write
operations are allowed. Using industry standard notation,
the March algorithm is:

March patterns

Cell

Pattern

Data (even)

w0r0r0w0w1r1r1w1w0r0w1r1r1w1w0r0r0w0w1r1r1w0r0

Care (even)

w1r1r1w1w0r0r0w0w1r1w0r0r0w0w1r1r1w1w0r0r0w1r1

Data (odd)

w1r1r1w1w0r0r0w0w1r1w0r0r0w0w1r1r1w1w0r0r0w1r1

Care (odd)

w0r0r0w0w1r1r1w1w0r0w1r1r1w1w0r0r0w0w1r1r1w0r0

Table 2

Detailed March algorithm

Cell

Pattern

wd0wc1
rd0rd0wd0wd1rd1rd1wd1wd0rc1rc1wc1wc0rc0rc0wc0wc1
rd0wd1rc1wc0
Even addresses

rd1rd1wd1wd0rd0rd0wd0wd1rc1rc1wc1wc0rc0rc0wc0wc1
?rd1rc0
?rd1wd0rc0wc1
?rd0rc1

This translates as ascending write 0 to every address,

ascending read 0 read 0 write 1 read 1 read 1 write 0 to every
address, ascending read 0 write 1 to every address,
descending read 1 read 1 write 0 read 0 read 0 write 1 to
every address, ascending read 1 from every address (data
retention test), ascending read 1 write 0 to every address,
descending read 0 from every address (data retention test).
Given the nature of the TCAMs and the layout of the bit cell,
there are some modifications to this algorithm. First,
anytime a value is written to the Data array, the opposite
value is written to the Care array at that location. Likewise,
nearest addresses are opposite as well. The reason for this is
to maximize the number of aggressor nodes on a victim
node, for example, surrounding a 1 with 0s on all four sides.
Table 1 describes in more detail what the March pattern
looks like.
In order to make testing as extensive as possible, data and
care tests are interleaved. For each address, the March
function will be performed on the Data value and then the
inverse will be performed on the Care value. For example,
the third test, described above as r0w1 would be better
described as rd0wd1rc1wc0, which is translated as read
data 0, write data 1, read care 1, write care 0. Following that
naming scheme, the overall pattern looks more like the
description in Table 2.

?wd1wc0
?rd1rd1wd1wd0rd0rd0wd0wd1rc0rc0wc0wc1rc1rc1wc1wc0
?rd1wd0rc0wc1
Odd addresses

?rd0rd0wd0wd1rd1rd1wd1wd0rc1rc1wc1wc0rc0rc0wc0wc1
?rd0rc1
?rd0wd1rc1wc0
?rd1rc0

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C O N F I D E N T I A L

Table 1

w0r0r0w0w1r1r1w1w0r0w1r1r1w1w0r0r0w0w1r1r1w0r0

A V A G O

P R E L I M I N A R Y

Datasheet

TCAM BIST

TCAM BIST

Functional Tests
In addition to the March test, several functional tests are
required to ensure that the CAMs are operating correctly.
There are six main functional tests in the TCAM BIST.

Functional Test 1: Test the compare operation

Fill Data array with 1s. Fill Care array with 1s. Compare
against 1s expect all matches. Compare against 0s
expect all misses. Write all 0s to Data array. Compare against
1s expect all misses. Compare against 0s expect all
matches.
This test ensures that a compare operation will behave as
expected and none of the pull down FETs in a matchline are
shorted or open. This test bypasses the Care array by
keeping all bits in a care state. This is required to fully test
the compare logic in a care state.

P R E L I M I N A R Y

Functional Test 2: Test the care bits ability to mask

Write 0s to Care array. Compare against 1s expect all
matches. Compare against 0s expect all matches.
Invalidate the array. Compare against 1s expect all misses.
Compare against 0s expect all misses. Write 1s to Data
array. Compare against 1s expect all matches. Compare
against 0s expect all matches. Invalidate the array.
Compare against 1s expect all misses. Compare against 0s
expect all misses.
This test performs two functions. First it tests the TCAMs
ability to match during a dont care situation. Regardless
of whether the Data value matches the compare value,
having the Care array set to dont care should ensure a
match. The other function of this test is to make sure that
setting the global invalidate_all bit will, in fact, invalidate
each address. Given that the entire array is in a matching
state at this point, it is a good place to test this functionality.

Functional test 3: Test against a 1-bit mismatch (worst case)

Write 1s to Care array. Walk a 0 across Compare input bus.
Expect all misses. Write 0s to Data array. Walk a 1 across
Compare input bus. Expect all misses.
The worst case mismatch for the TCAM is when the
Data/Care combination mismatches the compare value by
one bit. Under this condition, the single bit that is
mismatching must be able to pull down the entire
matchline within the allocated period. Functional test 3 will
test each bit by walking a mismatch across the compare
value. In order to reduce capacitance on the global
matchline, local matchlines are used in large TCAMs. Each
local matchline will have the ability to pull down the global
matchline should a miss be found. The worst case for a
mismatch, then, would be when a one bit mismatch
immediately follows a match. For this reason, TCAM BIST will
inject a match once every two compares during Functional
Test 3.

Functional Test 4: Test the write mask

Write 1s to Data array while Write Mask=0. Compare against
1s expect all misses. Write 1s to Data array with Write
Mask = 1.Write 0s to Data array with Write Mask = 0.
Compare against 0s expect all misses. Write 0s to Data
array with Write Mask = 10 (every other bit a 1). Compare
against 01 (opposite of write mask) expect all matches.
Write 0s to Data array while Write Mask = 01. Compare
against 0s expect all matches.
Functional Test 4 will extensively test the write masking
abilities of the TCAM. The first part of the test will check that
the write mask is capable of completely blocking a write to
the array. Next, the test will put the write mask in to a
1010 and then 0101 state to ensure that no shorts exist
between neighbors.

Functional test 5: Test the compare column mask

Compare against 1s with Comp Mask = 0 expect all
matches. Write 01s to Data array. Compare against 0s with
Comp Mask = 10 expect all matches. Write 10s to Data
array. Compare against 0s with Comp Mask = 01 expect all
matches. Write 1s to Data array. Compare against 0s with
Comp Mask = 0 expect all matches.
Functional test 5 operates similarly to Functional Test 4,
except it is used to perform masking during compare
operations. During compare operations, the mask operates
as a global dont care as opposed to the local dont care
that exists in the care array. Similarly to Functional Test 4,
Functional Test 5 first tests that the entire word can be
masked off. Next, the mask is set to 1010 and then 0101
to test for nearest neighbor shorting.

Functional test 6: Test Row Invalidate

Compare against 1s with Row Invalidate = 0 expect all
misses. Write 0s to even Data array addresses. Compare
against 1s with Row Invalidate = 01 expect all misses.
Compare against 1s with Row Invalidate = 10 expect all
misses.
Row Invalidate gives the TCAMs the ability to invalidate any
row in the array during a compare without having to write
the valid bit for that address. This feature is tested by first
invalidating all rows and comparing against a value (1s) that
would normally match. Next, 0s are written to even
addresses (Data array) while 1s are left in odd addresses
(Data array). A compare is done that would normally match
on odd addresses, but with the odd addresses invalidated
with Row Invalidate. Finally, a compare is done that would
normally match on even address, but with all even
addresses invalidated with Row Invalidate. In both cases, a
miss is expected.

Avago Technologies

TCAM BIST

TCAM BIST

Functional test 7

Initiating a TCAM BIST

Test individual valid bits. Write 1s to Data array with valid bit
= 0. Compare against 1s expect all misses. Previously, the
BIST has tested the Row Invalidate inputs and the global
Invalidate signal.

To initiate TCAM BIST, the start_bist input must transition

from a 0 to a 1. After the transition, there is a single cycle of
latency before BIST begins. This is to allow start_bist to fully
transition to a 1 for all of the TCAM instances that are being
tested. In most cases, it is suggested that a synchronizing
register be used in the surrounding logic to account for any
clock crossing issues between the domain initiating the
BIST and the TCAM clock domain, should they be different.

Functional Test 7 tests each individual valid bit by writing to

the entire array and then comparing against what would
match if the valid bits were asserted.

Functional test 8

Functional Test 8 verifies that valid mask can be disserted

when necessary. A checkerboard pattern is written to the
array to allow for static current tests to be done following a
TCAM BIST.

The duration of TCAM BIST will depend greatly on the width

and depth of the TCAM being tested. The equation to
determine BIST length is T = 69.5*Depth + 3.75 * Width +
602. Once BIST has completed, two signals will be asserted
high. If the BIST passes, bist_done and bist_pass will both
transition from a 0 to a 1. If BIST completes, but does not
pass, bist_done will transition from a 0 to a 1, but bist_pass
will remain at 0. This is most likely to happen prior to the
length of time determined by T above. If the TCAM BIST fails,
a fail code will be output on the fail_state bus. Table 3
describes the potential fail states.

C O N F I D E N T I A L

Table 3

Results from TCAM BIST

TCAM BIST error code list

Code

Name

Description

6b000000

FAIL_M2_read_d0a

March Test M2 failed on the first read even data 0

6b000001

FAIL_M2_read_d0b

March Test M2 failed on the second read even data 0

6b000010

FAIL_M2_read_d1a

March Test M2 failed on the first read even data 1

6b000011

FAIL_M2_read_d1b

March Test M2 failed on the second read even data 1

6b000100

FAIL_M2_read_c0a

March Test M2 failed on the first read even care 0

6b000101

FAIL_M2_read_c0b

March Test M2 failed on the second read even care 0

6b000110

FAIL_M2_read_c1a

March Test M2 failed on the first read even care 1

6b000111

FAIL_M2_read_c1b

March Test M2 failed on the second read even care 1

6b001000

FAIL_M2_read_d0c

March Test M2 failed on the first read odd data 0

6b001001

FAIL_M2_read_d0d

March Test M2 failed on the second read odd data 0

6b001010

FAIL_M2_read_d1c

March Test M2 failed on the first read odd data 1

6b001011

FAIL_M2_read_d1d

March Test M2 failed on the second read odd data 1

6b001100

FAIL_M2_read_c0c

March Test M2 failed on the fist read odd care 0

6b001101

FAIL_M2_read_c0d

March Test M2 failed on the second read odd care 0

6b001110

FAIL_M2_read_c1c

March Test M2 failed on the fist read odd care 1

6b001111

FAIL_M2_read_c1d

March Test M2 failed on the second read odd care 1

6b010000

FAIL_M3_read_d0

March Test M3 failed during read even data 0

6b010001

FAIL_M3_read_c1

March Test M3 failed during read even care 1

6b010010

FAIL_M3_read_d1

March Test M3 failed during read odd data 1

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A V A G O

Test valid_mask bit. Write checkerboard pattern to array

(0101, 1010), Compare against 0101 expect all
misses, Compare against 1010 expect all misses. The
write mask bus includes a bit used to mask the valid bit
during writing.

TCAM BIST

P R E L I M I N A R Y

Table 3

TCAM BIST

TCAM BIST error code list (continued)

Code

Name

Description

6b010011

FAIL_M3_read_c0

March Test M3 failed during read odd care 0

6b010100

FAIL_M4_read_d1a

March Test M4 failed on the first read even data 1

6b010101

FAIL_M4_read_d1b

March Test M4 failed on the second read even data 1

6b010110

FAIL_M4_read_d0a

March Test M4 failed on the first read even data 0

6b010111

FAIL_M4_read_d0b

March Test M4 failed on the second read even data 0

6b011000

FAIL_M4_read_c1a

March Test M4 failed on the fist read even care 1

6b011001

FAIL_M4_read_c1b

March Test M4 failed on the second read even care 1

6b011010

FAIL_M4_read_c0a

March Test M4 failed on the fist read even care 0

6b011011

FAIL_M4_read_c0b

March Test M4 failed on the second read even care 0

6b011100

FAIL_M4_read_d1c

March Test M4 failed on the first read odd data 1

6b011101

FAIL_M4_read_d1d

March Test M4 failed on the second read odd data 1

6b011110

FAIL_M4_read_d0c

March Test M4 failed on the first read odd data 0

6b011111

FAIL_M4_read_d0d

March Test M4 failed on the second read odd data 0

6b100000

FAIL_M4_read_c1c

March Test M4 failed on the first read odd care 1

6b100001

FAIL_M4_read_c1d

March Test M4 failed on the second read odd care 1

6b100010

FAIL_M4_read_c0c

March Test M4 failed on the first read odd care 0

6b100011

FAIL_M4_read_c0d

March Test M4 failed on the second read odd care 0

6b100100

FAIL_M6_read_d1

March Test M6 failed during read even data 1

6b100101

FAIL_M6_read_c0

March Test M6 failed during read even care 0

6b100110

FAIL_M6_read_d0

March Test M6 failed during read odd data 0

6b100111

FAIL_M6_read_c1

March Test M6 failed during read odd care 1

6b101000

FAIL_M7_read_d1

March Test M7 failed during read even data 1

6b101001

FAIL_M7_read_c0

March Test M7 failed during read even care 0

6b101010

FAIL_M7_read_d0

March Test M7 failed during read odd data 0

6b101011

FAIL_M7_read_c1

March Test M7 failed during read odd care 1

6b101100

FAIL_M9_read_d0

March Test M9 failed during read even data 0

6b101101

FAIL_M9_read_c1

March Test M9 failed during read even care 1

6b101110

FAIL_M9_read_d1

March Test M9 failed during read odd data 1

6b101111

FAIL_M9_read_c0

March Test M9 failed during read odd care 0

6b110000

FAIL_F1_match

Functional Test F1 failed to match

6b110001

FAIL_F1_miss

Functional Test F1 failed to miss

6b110010

FAIL_F2_match

Functional Test F2 failed to match

6b110011

FAIL_F2_invalid

Functional Test F2 failed to invalidate

6b110100

FAIL_F2_miss

Functional Test F2 failed to miss

Avago Technologies

TCAM BIST

Table 3

TCAM BIST

TCAM BIST error code list (continued)

Name

Description

6b110110

FAIL_F3_miss1

Functional Test F3 failed to miss 1s

6b110111

FAIL_F3_miss0

Functional Test F3 failed to miss 0s

6b111000

FAIL_F3_match

Functional Test F3 failed to match

6b111001

FAIL_F4_wm_miss

Functional Test F4 failed to miss on mask

6b110101

FAIL_F4_wm_match

Functional Test F4 failed to match on mask

6b111010

FAIL_F5_match

Functional Test F5 failed to match

6b111100

FAIL_F6_row_inv

Functional Test F6 failed to invalidate

6b111110

FAIL_F7_11_invalid

Functional Test F7 failed to invalidate all matches

6b111111

FAIL_F7_10_invalid

Functional Test F7 failed to invalidate neighbor matches

6b111011

FAIL_F8

Functional Test F8 failed to mask valid bits

A V A G O

Code

TCAM BIST Connectivity

In many cases, multiple instances of a TCAM may be

required to meet a customers needs. In these cases, it is
possible to share a TCAM BIST state machine among any
number of equally sized instances. Each instance will need

Table 4

to have a dedicated subblock. All like subblocks will be

controlled in parallel by the state machine. The outputs of
the subblocks must be ANDed together. For example the
subblock outputs a signal called dout_match that indicates
that a read operation matched the expected value. A
mismatch on any subblock will cause the BIST to fail and
report the failure as a read error. Table 4 and Table 5 give
more detail about the signals into and out of the TCAM BIST
state machine and subblocks.

TCAM BIST state machine port descriptions

Port

Direction

Description

clk

input

clock input port - should be same clock as TCAM instance

start_bist

input

start_bist initiates a TCAM BIST on the rising edge. There are two cycles of latency before anything actually happens so that the
start_bist signal will be asserted at the TCAM instance as well.

bist_pass

output

bist_pass indicates that the BIST has passed all of the tests. This signal should never be high while bist_done is low.
If bist_done is a 1 and bist_pass is a 0, then the BIST has failed.

bist_done

output

bist_done indicates that the BIST has completed all of the tests.

fail_state

output

fail_state consists of six coded bits that can be used to determine the nature of a failure.

match_all

input

match_all is a signal that is returned from the BIST subblock indicating that a compare operation matched on all of the addresses.

miss_all

input

miss_all is a signal that is returned from the BIST subblock indicating that a compare operation missed on all of the addresses.

din_walk_done

input

din_walk_done is a signal indicating that the walking 1 or walking 0 functional test is complete.

dout_match

input

dout_match indicates that a read done from the TCAM has matched the expected value.

din_walk_reset

output

din_walk_reset is a signal from the state machine to the subblock that resets the shift register used for the walking 1 and
walking 0 functional tests.

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C O N F I D E N T I A L

The TCAM BIST consists of two parts, the state machine and
the subblock. The state machine outputs a number of
control signals that the subblock decodes to control the
TCAM. The subblock also reads out the resulting return from
the TCAM and does some data analysis before sending a
return code back to the state machine.

TCAM BIST

P R E L I M I N A R Y

Table 4

TCAM BIST

TCAM BIST state machine port descriptions (continued)

Port

Direction

Description

din_walk_inc

output

din_walk_inc is a signal from the state machine to the subblock that increments the shift register used for walking 1 and
walking 0 functional tests.

inv_din_walk

output

inv_din_walk is a signal from the state machine to the subblock that determines whether a walking test is a walking 1 or a walking 0.

valid

output

valid is a signal from the state machine to the subblock that controls the valid bit of the din bus.

din_sel

output

din_sel is a 3-bit bus that determines the pattern being written to the TCAM. Bits 1:0 will be one of the four patterns written
and read during the March tests. Bit 2 will be zero except when doing a walking 1 or walking 0 functional test.

expected_value

output

expected_value is a 2-bit bus from the state machine to the subblock that indicates what is the expected value of a read operation.

dnc_en

output

dnc_en is a signal from the state machine to the TCAM choosing data or care array.

cmp_en

output

cmp_en is a signal from the state machine to the TCAM enabling compare.

read

output

read is a signal from the state machine to the TCAM enabling read.

write

output

write is a signal from the state machine to the TCAM enabling write.

all_invalidate

output

all_invalidate is a signal from the state machine to the TCAM resetting all of the valid bits.

addr

output

addr is a bus from the state machine to the TCAM that chooses which address to read from or write to.

mask_sel

output

mask_sel is a 2-bit bus from the state machine to the TCAM that will be used to set and test the write/compare mask.

mask_valid

output

mask_valid is a signal from the state machine to the TCAM that will set and test the valid bit on the write/compare mask.

Table 5

TCAM BIST subblock port descriptions

Port

Direction

Description

clk

input

clock input port - should be same clock as TCAM instance and state machine

matchout

input

matchout is a bus from the TCAM instance to the subblock that indicates which addresses of the TCAM have matched a compare input.

dout

input

dout is a bus from the TCAM instance to the subblock that contains the results of a read operation.

din_walk_reset

input

din_walk_reset is a signal from the state machine to the subblock that resets the shift register used for walking 1 and walking 0
functional tests.

din_walk_inc

input

din_walk_inc is a signal from the state machine to the subblock that increments the shift register used in walking 1 and
walking 0 functional tests.

inv_din_walk

input

inv_din_walk is a signal from the state machine to the subblock that chooses whether a walking functional test is a walking 1
or a walking 0.

valid

input

valid is a signal from the state machine that determines whether the valid bit should be set during a write operation.

din_sel

input

din_sel is a 3-bit bus from the state machine that determines what the din bus will consist of during a write or compare operation.

expected_value

input

expected_value is a 2-bit bus from the state machine that contains the expected value of a read operation.

din

output

din is an output from the subblock to the TCAM instance that contains the decoded write or compare value from the state machine.

match_all

output

match_all is an output from the subblock to the state machine that indicates a compare operation matched on all addresses.

miss_all

output

miss_all is an output from the subblock to the state machine that indicates a compare operation missed on all addresses.

din_walk_done

output

din_walk_done is a signal from the subblock to the state machine that indicates the shift register used in a walking 1 or
walking 0 functional test has completed its iterations.

dout_match

output

dout_match is a signal from the subblock to the state machine indicating that a read operation matched the expected value.

Avago Technologies

TCAM BIST

TCAM BIST

Figure 1 shows a schematic of how the TCAM BIST state

machine and subblocks should be connected when one
instance is being tested. Figure 2 shows how the TCAM BIST
state machine and sub blocks should be connected when
two instances are being tested in parallel using a common
state machine.

There is no limit to how many instances can be tested in

parallel using one state machine. Timing from the subblocks
to the state machine must be taken into account when
determining how to effectively share the state machine
among subblocks. It is also possible to use one subblock
across multiple TCAM instances if that should be necessary.
This method may be used to save gatecount and possibly
improve worst case power during testing, but it will result in
a longer run time for the BIST.
BIST_PASS

A V A G O

BIST_DONE
FAIL_STATE[5:0]

mask_sel[1:0]
mask_valid
clk
all_invalidate
start_bist
addr[n:0]
dout_match
cmp_en
din_walk_done
read
match_all
write
miss_all
dnc_sel

BIST Subblock
clk
din_walk_reset
din_walk_inc
dout_match
inv_din_walk din_walk_done
din_sel[2:0]
match_all
valid
miss_all
expected_value[1:0]
din[n:0]
dout[n:0]
matchout[n:0]

C O N F I D E N T I A L

BIST State Machine

bist_pass
bist_done
fail_state[5:0]
din_walk_reset
din_walk_inc
inv_din_walk
din_sel[2:0]
valid
expected_value[1:0]

TCAM Instance
(BIST ports shown)
clk
BIST_EN
BIST_MSK
BIST_MSK_VLD
BIST_VLD_RST
BIST_ADDR[N:0]
BIST_CMP
BIST_READ
BIST_WRITE
BIST_DNC
BIST_DIN
d_out
match_o

START_BIST

Figure 1

TCAM BIST schematic for one TCAM instance

Avago Technologies

TCAM BIST

TCAM BIST
BIST_PASS
BIST_DONE
FAIL_STATE[5:0]

START_BIST
BIST State Machine
bist_pass
bist_done
fail_state[5:0]
din_walk_reset
din_walk_inc
inv_din_walk
din_sel[2:0]
valid
expected_value[1:0]

BIST Subblock
clk
din_walk_reset
din_walk_inc
dout_match
inv_din_walk din_walk_done
din_sel[2:0]
match_all
valid
miss_all
expected_value[1:0]
din[n:0]
dout[n:0]
matchout[n:0]

d_out
match_o

mask_sel[1:0]
mask_valid
clk
all_invalidate
start_bist
addr[n:0]
dout_match
cmp_en
din_walk_done
read
match_all
write
miss_all
dnc_sel

P R E L I M I N A R Y

TCAM Instance
(BIST ports shown)
clk
BIST_EN
BIST_MSK
BIST_MSK_VLD
BIST_VLD_RST
BIST_ADDR[N:0]
BIST_CMP
BIST_READ
BIST_WRITE
BIST_DNC
BIST_DIN

BIST Subblock
clk
din_walk_reset
din_walk_inc
dout_match
inv_din_walk din_walk_done
din_sel[2:0]
match_all
valid
miss_all
expected_value[1:0]
din[n:0]
dout[n:0]
matchout[n:0]

TCAM Instance
(BIST ports shown)
clk
BIST_EN
BIST_MSK
BIST_MSK_VLD
BIST_VLD_RST
BIST_ADDR[N:0]
BIST_CMP
BIST_READ
BIST_WRITE
BIST_DNC
BIST_DIN
d_out
match_o

Figure 2

TCAM BIST schematic for two TCAM instances (same size)

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TCAM BIST

TCAM BIST

A V A G O
C O N F I D E N T I A L

This page is intentionally left blank.

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In This Datasheet:
Overview 1
Functional Tests 2
TCAM BIST Connectivity 5

For product information, please go to our web site:

www.avagotech.com
For technical assistance call:
Americas/Canada: +1 (800) 235-0312 or (916) 788-6763
Europe: +49 (0) 6441 92460
China: 10800 650 0017
Hong Kong: (65) 6756 2394
India, Australia, New Zealand: (65) 6755 1939
Japan: (+81 3) 3335-8152 (Domestic/International), or 0120-61-1280 (Domestic only)
Korea: (65) 6755-1989
Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (65) 6755 2044
Taiwan: (65) 6755 1843
Data Subject to change
Version 1.0, January 2007

C O N F I D E N T I A L

P R E L I M I N A R Y

A V A G O

Avago Technologies, Inc. January 2007