DIGITAL DESIGN ON DIGITAL WORKS

CONTENT1) BOOLEAN DESIGN

2) MINIMIZATION PROBLEM
3) HALF ADDER
4) FULL ADDER
5) MULTIPLEXER
6) BOOLEAN FUNCTION IMPLIMENTATION WITH MULTIPLEXER
7) ENCODER
8) DECODER
9) BOOLEAN FUNCTION IMPLIMENTATION WITH DECODER
10)

RS LATCH (NAND,NOR)

11)

RS FLIP FLOP(NAND,NOR)

12)

D FLIP FLOP

13)

J-K FLIP FLOP

14)

T FLIP FLOP

15)

MASTER SLAVE JK FLIP FLOP

16)

SHIFT REGISTER

17)

PARALLEL IN SERIAL OUT SHIFT REGISTER

18)

COUNTER ASYNCHRONOUS (UP / DOWN)

19)

COUNTER SYNCHRONUS(UP / DOWN)

20)

LOGIC HISTORY

21)

TEMPLATE EDITOR

22)

AIRTHMATIC LOGIC UNIT (AND, OR, XOR)

23)

BCD TO SEVEN SEGMENT

MINIMIZATION OF BOOLEAN FUNCTION

(a+a) = 1
(a.a) = 1
Sum of product (a+a=1)
Example -Abc +abc = ab(c+c) = ab

Product of sumExample -(a+b+c)(a+b+c) = (aa) + (ab) + (ac) + (ba) + (bb) + (bc) + (ca)
+ (cb) + (cc)

Que- Find the minimum cost sop and pos form for the function (a,b,c) =
(0,3,4,7) with circuit diagram?

Ans=(abc+abc+abc+abc)
=(abc+abc)+(abc+abc)
=bc(a+a) + bc(a+a)
=(bc)+(bc)

minterm

abc

abc

abc

abc

abc

abc

abc

abc

Product of sum-(a.a=0)
= [(a+b+c)(a+b+c)][(a+b+c)(a+b+c)]
= bc+cb+bc+cb
=bc+cb

maxterm

abc

abc

0
0
1

1
1
0

abc

abc

abc

abc

abc

abc

BOOLEAN FUNCTION IMPLIMENTATION WITH MUTIPLEXER

A multiplexer has a number of data input, one or more select line and one
output.

S1

S0

I0

I1

I2

I3

Y= (S0 S1 I0 + S1S0 I1 + S1 S0 I2 + S0 S1 I3)

BOOLEAN FUNCTION IMPLIMENTATION WITH DECODER

Decoder circuit are used to decode the encoded information. A binary decoder is
a logic circuit with n inputs and 2^n outputs. Only one output is asserted at a
time and each output corresponds to one valuation of the inputs. The decoder
has an enable input En, that is used to disable the output ; if En=0, then none of
the decoder outputs is asserted. If En=1 the valuation of Wn-1..w1 w0
determines which of decoder outputs is asserted.
TRUTH TABLE
S1
0

S0

Y3

Y2

1
0

Y1

Y0

0
0
0

HALF ADDER

CIRCUIT DIAGRAM OF HALF

ADDER
-It consist of an AND gate and XOR gate .
-It has two input which is x1 and x1 and two output which named is SUM and
CARRY.
-Both the gate connected to the same inputs.

TRUTH TABLE
X1

X2

SUM

CARRY

ENCODER

CIRCUIT DIAGRAM OF
ENCODER
-An encoder perform the opposite function of decoder.
-It encodes given information into more compact form.
-It has 2^n inputs and n outputs.

TRUTH TABLE
I3
0

I2

I1
0

I0
1

Y0

Y1

DECODER

CIRCUIT DIAGRAM OF DECODER

-Decoder circuit are used to decode encoded information.
-The logic circuit with n inputs and 2^n output.
-The decoder also has an enable input called it EN, that is disable the outputs ; if
EN =o then none of the
Decoder outputs is asserted.
-If EN=1 the valuation of Wn-1w1,w0 determines which of the outputs is
asserted.

TRUTH TABLE
S0
0

S1
0

Y3
0

Y2 Y1 Y1
0

0
1

0
1
0

1
0
0

0
1
0

MULTIPLEXER-

MULTIPLEXER

CIRCUIT DIAGRAM OF
MULTIPLEXER
-A multiplexer circuit has a number of inputs, one or more select input and only
one output.
-It passes the signal value on one of the data input to the output.
-The data input is selected by the values of the select the input.
-

TRUTH TABLE
S
1
2

Y
X0
X1

D-FLIP FLOP-

D FLIP FLOP

CIRCUIT DIAGRAM OF D-FLIP FLOP

D-FLIP FLOP----It store only one bit information.
-This gate is useful for many application.
-It has single data called D flip flop and it store the value on this input, under
the control of a clock signal.It is called D flip flop.

CHARACTERISTIC TABLE

CLK

Q(t+1)

Q(t)

J-K FLIP FLOP-

J-K FLIP FLOP

CIRCUIT DIAGRAM OF J-K FLIP

FLOP
-

D=JQ+KQ
The jk flip flop is a versatile circuit.
It can be used straight storage purpose, just like the D and SR flip flop.
It can also serve as a T flip flop connecting the j and k inputs together.

CHARACTERISTIC TABLE

Q(t+1)

0
0
1
1

0
1
0
1

Q(t)
0
1
Q(t)

MASTER SLAVE FLIP FLOP-

MASTER SLAVE FLIP FLOP

CIRCUIT DAIGRAM OF MASTER

SLAVE FLIP FLOP
-It consist of two D flip flop , The first one is master and the another one is
called slave.
-The first called master , changes its state while clock = 1. The second called
slave,changes
Its state while clock = 0.

-When clock is high, the master tracks the value of the D input signal and slave
does not change.
-When clock is low , the slave tracks the value of the D input signal and master
does not change.

SHIFT REGISTER-

SHIFT REGISTER

CIRCUIT DIAGRAM OF SHIFT

REGISTER
-A flip flop store one bit information. When a set n flip flop used is used to store n
bit of information,
Such as an n-bit number, then these flip flop as a Register.
-A common clock is used for each flip flop on a register.

-A register that provides the ability to shift its content is called a shift register.

PARALLEL IN SERIAL OUT SHIFT REGISTER-

PARALLEL IN SERIAL OUT SHIFT

REGISTER

CIRCUIT DIAGRAM OF PARALLEL

IN SERIAL OUT SHIFT REGISTER

BCD TO SEVEN SEGMENT-

BCD TO 7 SEGMENT

CIRCUIT DIAGRAM OF BCD TO

7SEGMENT
-

BCD input is represented by the four-bit signal named bcd.

The seven output are the seven-bit signal named leds.

a
g
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1

AIRTHMATIC LOGIC UNIT-

AIRTHMATIC LOGIC UNIT

1
0

1
1

CIRCUIT DIAGRAM OF AIRTHMATIC

LOGIC UNIT

T-FLIP FLOP
-D flip flop is a versatile storage element that can be used for many purpose. By
including some simple logic circuitry to drive its inputs, the D flip flop May appear
to be a different types of storage element.

-This circuit uses a positive edge triggered D flip flop.

-The name T flip flop derives from the behaviour of the circuit, which toggles
its state when T=1.
-The feature makes the t flip flop a useful element for building counter circuit.

TRUTH TABLE
T
1
2

Q(t+1)
Q(t)
Q(t)

RS LATCH (NAND, OR)

WITH NAND-In this circuit, the clock is gated by NAND gates, rather than by AND gate.

-When both the S and R 0. It changes its state in response to change in the
signal on these inputs.
The state changes occur at the time when the changes in the signal occur.
-It has two state Enable and Disable mode, when Enable mode the system by
mean control the input and when Disable mode changing the SET input from 0
to 1 would not cause the alarm to turn on.
-In this situation latch cannot provide the desired operation. But the latch circuit
can be modified to respond to the input signal S and R only when Enable =1.
TRUTH TABLE
CLK

Q(t) no change

Q(t) no change

0
1

Q(tt+1)

WITH NOR LATCH

TRUTH TABLE
S

ACTION

0
0

0
1

HOLD STATE

RESET
SET

NOT ALLOWED

COUNTERCounter circuit are used in digital system for many purpose. They may count the
number of occurrence of certain event, generate timing interval for control of
various tasks and so on. Counter can be implemented using the adder and
subtractor circuit since we only need to change the content of a counter 1.

ASYNCHRONUS COUNTER
The simple counter circuit can be built using T flip flop because of toggle
feature.
UP COUNTER
A THREE BIT UP COUNTER
The clock input is connected in cascade form. The T input of each flip flop is
connected to a constant 1, which means that state of the flip flop will be
reversed at each positive edge of its clock. The clk input of the first flip flop is
connected to the clk line. The other flip flop have their clk inputs driven by the Q
output of the preceding flip flop. Hence they toggle their state whenever the
preceding flip flop changes its state from 0 to 1 which result is a positive edge of
the Q signal.
DOWN COUNTER
The only difference is that a clock input of the second and third flip flop are
driven by the Q output of the preceding stages rather than by the Q output. It
counts in the downward direction we say it down bit counter.

ASYNCHRONOUS DOWN COUNTER

ASYNCHRONOUS UP COUNTER
SYNCHRONOUS COUNTERIf a counter with a larger number of bits is constructed in this manner , then
delay caused by the cascaded clocking scheme may become too long to meet
the desired performance requirement. We can build a faster counter by clocking
all flip flop at the same time.

UP AND DOWN SYNCHRONOUS COUNTER

The pattern of bits in each row of the table, it is apparent that bit Q0 changes on
each clock cyle. Bit Q1 changes only when Q0=1. Bit Q2 changes only when
both Q1 and Q0 are equal to 1. In general, for an n- bit up counter , a given flip
flop changes its state only when all the preceding flip flop are in the state Q=1.

clock cycle

Q2 Q1 Q0

1
0

1
0

-All flip flop changes their state after a propogation delay from the positive edge
of the clock.

SYNCHRONOUS UP COUNTER

SYNCHRONUS DOWN COUNTER

LOGIC HISTORY OF D-FLIP FLOP

To understand how the logic history work and what is the function of logic
history.
As we take the example of D flip flop to understand in better way.
Make the circuit of D flip flop , when you complete the circuit of D flip flop
then

Then all the input and output added in logic history.

TEMPLATE

EDITOR

Click on the template editor

After that you complete your template then you save that template in
digital works that is the path centre where you fetch the circuit and put
in the digital works and you connect the input and output.