Use the FPGA as a PIO.

This application note describes how to use the DragonEngines onboard FPGA as a
PIO chip. The design implements 48 programmable input/output pins that are bit
programmable. The 48 ports are divided over three 16-bit ports. The two remaining
FPGA pins are used as PWM outputs.
The design is written in VHDL, and consists of 4 files and a constraint file:
drenpio.vhd
port.vhd
pwm.vhd
resetgen.vhd
pio.ucf
The drengpio.vhd file contains the processor interface. It basically interfaces the
PIO/PWM registers to the processor host bus. The port.vhd files contains the
actual I/O port. This part interfaces the registers to the actual I/O pins. The pwm.vhd
file is a PWM building block. The resetgen.vhd file contains a reset generator
circuit. The FPGA is configured after the processor has been started up, this means
that it has not been reset into a known state. Once the configuration has been loaded
into the FPGA this simple circuit will reset the flip-flops into a known state. The
pio.ucf file is file that is used by the Xilinx FPGA tools and holds timing and
location constraints. In this case it is only used to lock the FPGAs pin locations.
The PIO has three input/output ports (ports A, B, and C) each 16 bits wide. Each port
has a data direction register (DDR) for selecting the input or output direction (0=
Output, 1=Input), an output data register (ODR) for storing output data, and an input
register (IDR) for reading data from the input. When the data direction register (DDR)
is programmed as output, the input data register (IDR) serves as a read back for the
data register. The
Each of the two PWM generators are controlled by two 16 bit registers, called
PWMXA and PWMXB (X represents the PWM port number). The outputs of the two
PWM modulators are available on the dedicated output ports PD0 and PD1. The
PWMXA register specifies the time at which value the PWM counter is cleared. At
the same time the PWM output is set to 1. The PWMXB register specifies the time
at which the PWM output changes from 1 to 0. The clock source of counter is
taken from the processors CLKO signal.

The following figure shows the relation between the PWM counter value, PWMXA,
PWMXB registers and the PWM output.
PWM Counter value

PWM XA

PWM XB

t
PWM Output

Fig A-1.

An impression of the routed PIO design on a Xilinx X2S50 FPGA chip:

Fig A-2.

The Xilinx implementation tools generate a .bit file which contains the actual
configuration information to be send towards the FPGA chip. Unfortunately the .bit
output format is rather difficult to handle with trgular tools. Therefore a small utility
program (called fpga2c) has been written that converts the .bit or .exo file into a
regular C file.
The fpga2c program needs a couple of parameters. The first parameter is the input
file, it can eater be a .bit file out of the Xilinx implementation software or a .exo
file out of the Xilinx PROM File Formatter program (the fpga2c program will
automatically recognize the input format by means of the extension). The second
parameter is the name of the C output file. Optionally a -v can be given to show
the processing information.

fpga2c drengpio.bit fpgadata.c v

/* This is a Xilinx FPGA configuration data file. */
const char fpgadatabits[69900]=
{
0xFF,0xFF,0xFF,0xFF,0x55,0x99,0xAA,0x66,0x0C,0x00,
0x01,0x80,0x00,0x00,0x00,0xE0,0x0C,0x80,0x06,0x80,
.
.
.
0x00,0x00,0x84,0x7A,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
};
struct fpgadatatype fpgadata =
{
"drenpio",
"x2s50tq144",
69900,
(char *) fpgadatabits
};

Table A-3 : Example of a FPGA configuration file transformed into a C file.

Table A-3 shows an example of the C output file. This C output file contains just a
large array with all the FPGA configuration data, and an initialization information
structure. This C output file can then be compiled as part project. To initialize the
FPGA simply call the initfpga() function with a pointer to the initialization
information structure.
#include fpga.h
main()
{
int result;

result = initfpga(fpgadata);
if (result != 0)
{
error handling comes here !
}

The initfpga() function returns a zero integer if the FPGA was successfully
configured. A no-zero integer return indicates that there was an error during the
configuration. Once the FPGA is configured it can be used.
Address:
FPGA Base + 0x00
FPGA Base +0x02
FPGA Base +0x04
FPGA Base +0x06
FPGA Base +0x08
FPGA Base +0x0A
FPGA Base +0x0C
FPGA Base +0x0E
FPGA Base + 0x10
FPGA Base + 0x12

Write:
DDR Port A
ODR Port A
DDR Port B
ODR Port B
DDR Port C
ODR Port C
PWM1A
PWM1B
PWM2A
PWM2B

Read:
DDR Port A
IDR Port A
DDR Port B
IDR Port B
DDR Port C
IDR Port C
PWM1A
PWM1B
PWM2A
PWM2B

Table A-2 : Registers and there addresses.

Programming the PIO port:

Basically we have to program the DDR (Data Direction Register) according to the
way we want to use the port. If we want a particular port pin to be programmed as
output, we write a 0 the corresponding bin in the DDR. If we want an output, a 1 is
written to the corresponding bit in the DDR.
If the pin is programmed as output, the ODR (Output Data Register) bit will be copied
to the corresponding output pin.
If the pin is programmed as input, the IRD (Input Data Register) will reflect the state
of the input pin.
The output state on the pin will be reflected into the corresponding IDR bit even if the
port was programmed as output. This can be used to use and/or functions to set and or
reset individual bits.