Lab 2 Report

Design of a Three Stage BJT Amplifier

Kevin Bradshaw & Kai Qin
ECEN 326-502
Instructor: Sebastian Hoyos
Date Performed: February 11, 2016

Objectives
Understand the characteristics of a three stage BJT Amplifier.
Design and analyze a common-emitter, common-base, and emitter follower
configuration meeting certain constraints.
Evaluate the DC operating point of a cascode transistor amplifier and a transistor
current source
Procedure
In this lab, the BJT circuit designed from the pre-lab was constructed. The amplifier was
designed to fit the constraints shown in Figure 1:
Figure 1: BJT Amplifier Design Constraints

Using a chosen value for the emitter voltage of the first stage and a Q2N2222 BJT, this
circuit was designed with by finding the minimum and maximum values of the collector
resistance. Choosing a collector resistance between these range of values, the collector
current could easily be found by using the common topology formulas. Then, the rest of
the resistances of this stage of the circuit were calculated using these currents. The
other emitter voltages VE2, VE3, and VE4 were found with the voltages from the first
stage. Lastly, the resistor ratio for each base impedance was calculated with these
voltages. Figure 2 shows the resulting circuit designed and Table 1 shows the actual
values used in the circuit. These values were adjusted after construction in order to get
an optimum gain with no clipping in the voltage swing.

Figure 2: Three Stage BJT Amplifier

After the circuit was adjusted, the operating currents and voltages (including the
maximum unclipped output signal voltage amplitude) were measured and can be seen
in Table 2. Furthermore, the input resistance, output resistance, current supply, and gain
were measured and can also be seen in Table 3. The overall gain of this circuit to
achieve a output swing greater than 1.5 V can be seen in Figure 3. The maximum
output voltage swing can be seen in Figure 4. Lastly, to obtain the total harmonic
distortion (THD) of less than 5%, a signal of 40 mV was placed at the input and an
output of approximately 1.24 V was obtained. Figure 5 shows the THD achieved.
Figure 3: Overall BJT Amplifier Gain

Figure 4: Maximum Output Voltage Swing

Figure 5: Total Harmonic Distortion Analysis

Data Tables
Table 1: Final Design Circuit Parameters
Parameter

Value

Base Resistor 1 (RB1)

66.79 k

Base Resistor 2 (RB2)

45 k

Base Resistor 3 (RB3)

57 k

Base Resistor 4 (RB4)

45 k

Base Resistor 5 (RB5)

18 k

Base Resistor 6 (RB6)

36 k

Collector Resistor (RC)

3.298 k

Emitter Resistor 1( RE)

2.369 k

Load Resistor (RL)

100

Emitter Resistor 2 (RG)

22

Emitter Resistor 3 (RE3)

20

Capacitors 1, 2, 3, 4 (C)

10 F
Table 2: Operating Bias Points

Q1

Q2

Q3

Q4

Collector
Current (IC)

0.607 mA

0.65 mA

21.0 mA

20.7 mA

Collector
Voltage (VC)

1.450 V

2.287V

4.914 V

1.912 V

Base Voltage
(VB)

1.992 V

2.08 V

2.49 V

1.189 V

Emitter
Voltage (VE)

1.352 V

1.451 V

1.919 V

0.508

Table 3: Measured Circuit Values

Parameter

Value

Supply Current

22.84 mA

Gain

31.7

Input Resistance

13.33 k

Output Resistance

490

Maximum Unclipped Out Signal

Amplitude

Approximately 2.78 V

Discussion

The overall gain of input peak to peak voltage 58 mV was 31.38 which meets the Av =
30 requirement. However, when the input peak to peak voltage reaches 130 mV, the
gain decreased to 23.23. During the lab time, the max unclipped output signal peak to
peak value is 2.78 V which is less than the specs value 3 V, when the input pk-pk is 90
mV.
The problem we encountered was that the circuit built using the pre-lab parameters
cannot meet the specs requirement of the pk-pk unclipped swing 3V. To solve this
problem, we connected pots to first and last stage for changing DC bias points. At last,
we reached the highest unclipped swing by increasing the first stage base resistance
Rb1 from 57 k to 66.79k.
Conclusion
From this lab we have a better understanding of the characteristics of a three stage BJT
Amplifier, and we become more familiar with the procedures how to design and analyze
a common-emitter, common-base, and emitter follower configuration meeting certain
constraints. When the pre-lab design cannot meet given constraints, we inspected
output signals from every stage.