ISBN-13: 978-1537313573

Proceedings of ICTPRE-2016

HIGH EFFICIENT CARRY SKIP ADDER IN

VARIOUS MULTIPLIER STRUCTURES
Arun Sekar.R #1, Naveen Balaji.G #2, A.Gautami #3, B.Sivasankari #4
#

Assistant Professor, Department of Electronics and communication Engineering,

SNS College of Technology, Coimbatore, India
1rarunsekar007@gmail.com
2yoursgnb@gmail.com,

Researcher ID: B-9448-2016

Abstract Carry Skip Adder (CSKA) structure has a high speed and lower energy intake compared with the conventional structure.
The speed improvement is attained by applying concatenation and incrementation systems to improve the performance of the
predictable CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the structure made use of AND-ORInvert (AOI) and OR-AND-Invert (OAI) complex gates for the skip logic. The structure may be made with both xed stage size and
variable stage size styles, wherein the later further improves the speed and energy constraints of the adder. And the link of area,
delay, power and the energy are made. The Carry skip adder structure is applied to multiplier and the multiplier includes
comparison of Wallace tree multiplier and the Baugh-wooley multiplier. The area, power depletion, energy comparison and delay are
done for Baugh-Wooley Multiplier and Wallace tree Multiplier.
Keywords Carry skip adder (CSKA), energy efficient, high performance, Baugh-Wooley Multiplier, Wallace Tree Multiplier

I. INTRODUCTION
A low power arithmetic circuit has become very significant in many VLSI industries. Adder circuit is the main
building block in various DSP mainframes. Adder is the foremost component of arithmetic unit. Addition has an important
process for various digital systems, digital signal processing or control system. The fast and accurate procedure of a digital
system is being prejudiced by the efficiency of the adders. Adders are also very significant component in digital systems
because of their larger use in other basic digital processes such as multiplication, subtraction and division. Hence, the improving
performance of the digital adder would greatly advance the execution of binary operations inside a circuit involving of such
blocks. The presence of a digital circuit block is obtained by recitation its power dissipation, area and its operating speed. There
are numerous works on the subject of enhancing the speed and power of these unit, which have been described in [2][9].
Apparently, it is particularly famous to achieve developed speeds at low-power/energy consumptions, which is a dare for the
inventors of general purpose processors.
In existing method, we are using multiplexer logic in which the amount of gate count is more. The power consumed by
the carry skip adder using multiplexer logic is more and critical path delay is high. The ripple carry adder is accumulated by
cascading full adders (FA) blocks in series. One full adder is accountable for the addition of two binary digits at any phase of
the ripple carry. The carryout of one stage is fed directly to the carry-in of the subsequent stage. A number of full adders may be
added to the ripple carry adder or else ripple carry adders of unlike sizes may be cascaded in order to accommodate binary
vector strings of greater sizes. For an n-bit parallel adder, it needs n computational elements (FA). The carry is scattered in a
serial computation. Hence, delay is more as the amount of bits is greater than before in RCA.

The rest of this paper is prepared as follows. Section II converses related work on the recommended
CSKA structure for improving the speed and for increasing the efficiency of adders. In Section III, ripple
carry structure is explained. The incrementation block structure is suggested in Section IV. The section V
describes the Baugh-Wooley Multiplier, while section VI describes the Wallace Tree Multiplier. The
results and discussion are made in Section VII. Finally, the conclusion is given in section VIII.
II. PROPOSED WORK

The effort of this paper is on rapidity of the carry skip adder structure and the lessening in the critical
path Delay. The projected system comprises the ripple carry adder structure through the AOI and OAI
compound gates for skip logic. The skip logic decreases the number of gate amount in the structure. The
structure speed is achieved by using skip logic and the delay is reduced. The predictable structure of the

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ISBN-13: 978-1537313573

Proceedings of ICTPRE-2016

CSKA involves of stages containing chain of full adders and 2:1 multiplexer. The RCA blocks are linked
to each other through 2:1 multiplexers, which can be placed into one or more level structures.
The CSKA conguration (i.e., the number of the FAs per stage) has a great impression on the speed of
this type of adder. Many approaches have been recommended for nding the optimal number of the FAs.
Figure 1 expressions the adder comprises two N bits inputs, A and B, and Q stages. Every stage contains
of an RCA block with the size of Mj (j = 1,...,Q). In this structure, the carry input of all the RCA blocks,
excluding for the rst block which is Ci, is zero i.e the concatenation of the RCA blocks. Consequently,
hence all the blocks of the structure and perform their jobs instantaneously.
In arithmetic and logic units adders are a key constructing block. Later increasing their speed and
reducing their power/energy consumption intensely affect the speed and power consumption of processors.
There are several works on the subject of improving the speed and power of these elements, which have
been described. Evidently, it is highly desirable to achieve higher speeds at low-power/energy
consumptions, which is a encounter for the designers of common purpose processors.

Fig.1. Proposed Structure Of CSKA

In this assembly, when the rst block calculates the summation of its consistent input bits (i.e., SM1,...,S1 ) and C1, the
additional blocks promptly compute the in-between results and also Cj signals. In the future structure, the rst stage has only
one block, which is RCA. The phases 2 to Q consist of two blocks of RCA and incrementation.
The incrementation block customs the intermediate outcomes created by the RCA block and the carry output of the earlier
stage to compute the nal summation of the stage.

All the RCA blocks, except for the 1st block partaking zero as carry input. Output carries of the RCA
blocks are intended in parallel. The skip logic comprises the OAI (OR AND Invert) and AOI (AND OR
Invert) complex gates for skip logic. The gates, which involve of fewer transistors, have lower delay, area,
and smaller power consumption likened with those of the 2:1 multiplexer. In this structure, as the carry
proliferates through the skip logics, it converts complemented.
III. RIPPLE CARRY ADDER
The ripple carry adder is formed by cascading full adders blocks in sequences. One full adder is accountable for the addition
of two binary digits at several stage of the ripple carry. The carry out of one stage is fed conventional to the carry-in of the next
stage. An amount of full adders may be added to the ripple carry adder or ripple carry adders of dissimilar sizes may be dropped
in order to accommodate binary vector strings of greater sizes. On behalf of an n-bit parallel adder, it needs n computational
elements (Full Adder).
The worst-case delay of the RCA is once a carry signal transition ripples through entire stages of adder sequence from the
slightest significant bit to the maximum significant bit, which is approximated by:

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IIRDEM 2016

ISBN-13: 978-1537313573

Proceedings of ICTPRE-2016
T = (n-1) tc+ ts

where the tc is the delay through the carry stage of a full adder. It is the delay to calculate the sum of the
last stage is shown in equation 1.
IV. INCREMENTATION SCHEMES
The interior structure of the incrementation block, which comprises a sequence of half-adders (HAs), is shown in Figure 3.
In addition, note that, to reduce the delay significantly, for calculating the carry output of the stage, the carry output of the
incrementation block is not used. The incrementation contains AND gate and EX-OR gate. The carry input is fed into the
structure and it performs the operation like the half adder.

ZKj+Mj

ZKj+Mj-1

..............

Half
Adder

EXOR

ZKj+2

ZKj+1

Half
Adder

Half
Adder

CO,j
-1

\
SKj+Mj

SKj+Mj-1

SKj+2

SKj+1

Fig.2.

V. BAUGH-WOOLEY MULTIPLIER

In retained multiplication the period of the partial products and the number of partial products will be
very high. So an algorithm was presented for sign multiplication
named as Baugh Wooley algorithm. The
.
Baugh-Wooley multiplication is one among the cost-effective ways to embrace the sign bits. This
technique has been established so as to style regular multipliers, suited to 2's compliment figures. BaughWooley multiplier hardware building is shown in figure 3. It follow left shift algorithm. MUX can choose
which bit will multiply. The carry skip adder construction is implementer to the multiplier and their
comparison is made.
A=a3 a2 a1 a0
B=b3 b2 b1 b0
1

a3b0 a2b0 a1b0 a0b0

a3b1 a2b1 a1b1 a0b1

a3b2 a2b2 a1b2 a0b2
1 a3b3 a2b3 a1b3 a0b3
p7

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p6

p5

p4

p3

p2

p1

p0

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IIRDEM 2016

ISBN-13: 978-1537313573

Proceedings of ICTPRE-2016

Fig.3. Structure of BAUGH-WOOLEY Multiplier

VI. WALLACE TREE MULTIPLIER

Wallace Tree Multiplier has an effective multiplication algorithm, which has a compact delay in order of O (log n) . The
logarithmic rise in delay with respect to operand size offers speed gain above array multiplier which has a linear rise in delay.
In this multiplier construction all the bits of all the incomplete products in a column are added composed in parallel without the
propagation of several carries. The procedure is repetitive till there is only two rows of the matrix is left, the two rows are then
added by a fast adder. Now a 3:2 compressor is used which is created on carry skip adder. The matrix for every stage through its
height for a 8X8 wallace tree multiplier is shown Figure 4.

Fig.4. Structure of 8*8 Wallace Tree Multiplier

VII.

RESULT AND DISCUSSION

The design proposed in this paper has been developed using MODEL SIMULATOR. The comparison of area, delay,
power and energy are obtained for 16 bit adder and a 32 bit adder. The adder structure was performed using an fixed stage size
and an variable stage size method. The carry skip adder is applied to an multiplier structure and its area, delay, power and
energy are compared.

TABLE I
COMPARISON OF AREA, DELAY, POWER AND ENERGY OF CSKA STRUCTURE

EXISTING METHOD

16 BIT

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PROPOSED METHOD

FIXED STAGE
SIZE

VARIABLE
STAGE SIZE

FIXED STAGE
SIZE

VARIABLE
STAGE SIZE

AREA
(GATE COUNT)

240

318

276

300

DELAY

33.221nsec

31.988nsec

23.882nsec

22.456nsec

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ISBN-13: 978-1537313573

32 BIT

Proceedings of ICTPRE-2016

POWER

23.95mW

24.60mW

22.46mW

22.52mW

ENERGY

795.65

797.15

536.38

505.70

AREA
(GATE COUNT)

623

678

600

660

DELAY

40.48nsec

39.478nsec

38.682nsec

30.927nsec

POWER

24.72mW

24.74mW

23.31mW

23.37mW

ENERGY

1000.66

976.68

901.67

722.76

TABLE III
COMPARISON OF AREA, DELAY, POWER AND ENERGY OF MULTIPLIERS

EXISTING SYSTEM

PROPOSED SYSTEM

MULTI
-PLIERS

AREA
(GATE
COUNT)

DELAY
(nsec)

POWER
(mW)

ENERGY

AREA
(GATE
COUNT)

DELAY
(nsec)

POWER
(mW)

ENERGY

BAUGHWOOLEY

1342

51.72

23.72

1226.79

1164

48.60

21.34

1037.12

WALLACE
TREE

5230

7.327

27.44

201.05

4940

5.347

25.32

135.38

VIII.

CONCLUSION

In this paper, Carry Skip Adder (CSKA) structure was suggested, which shows a lower energy
consumption and higher speed likened with the conventional structure. The speed is concluded the
concatenation and efficiency by the incrementation procedures. In addition, AOI and OAI compound gates
were exploited for the carry skip logics. The competence of the proposed structure for both VSS and FSS
was studied. The consequences also suggested that the CSKA structure is a very good adder for the
applications where both the speed and energy ingesting are critical. In accumulation, a hybrid variable
latency extension of the construction was proposed which decreases the power without upsetting the speed
of the structures.
REFERENCES
[1]
[2]
[3]
[4]
[5]

Koren, Computer Arithmetic Algorithms, 2nd ed. Natick, MA, USA: A K Peters, Ltd., 2002.
R. Zlatanovici, S. Kao, and B. Nikolic and koren ,Energydelay optimization of 64-bit carry-lookahead adders with a 240 ps 90 nm CMOS design
example, IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 569583, Feb. 2009.
S. K. Mathew, M. A. Anders, B. Bloechel, T. Nguyen, R. K. Krishnamurthy, and S. Borkar, A 4-GHz 300-mW 64-bit integer execution ALU with dual
supply voltages in 90-nm CMOS, IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 4451, Jan. 2005.
V. G. Oklobdzija, B. R. Zeydel, H. Q. Dao, S. Mathew, and R. Krishnamurthy, Comparison of high-performance VLSI adders in the energy-delay
space, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 754758, Jun. 2005.
B. Ramkumar and H. M. Kittur, Low-power and area-efcient carry select adder, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2, pp.
371375, Feb. 2012.

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[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]

Proceedings of ICTPRE-2016

M. Vratonjic, B. R. Zeydel, and V. G. Oklobdzija, Low- and ultra low-power arithmetic units: Design and comparison, in Proc. IEEE Int. Conf.
Comput. Design, VLSI Comput. Process. (ICCD), Oct. 2005, pp. 249252.
C. Nagendra, M. J. Irwin, and R. M. Owens, Area-time-power tradeoffs in parallel adders, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.,
vol. 43, no. 10, pp. 689702, Oct. 1996.
Y. He and C.-H. Chang, A power-delay efcient hybrid carry- lookahead/carry-select based redundant binary to twos complement converter, IEEE
Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 1, pp. 336346, Feb. 2008.
C.-H. Chang, J. Gu, and M. Zhang, A review of 0.18 m full adder performances for tree structured arithmetic circuits, IEEE Trans. Very Large Scale
Integr. (VLSI) Syst., vol. 13, no. 6, pp. 686695, Jun. 2005.
D. Markovic, C. C. Wang, L. P. Alarcon, T.-T. Liu, and J. M. Rabaey, Ultralow-power design in near-threshold region, Proc. IEEE, vol. 98, no. 2, pp.
237252, Feb. 2010.
R. G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge, Near-threshold computing: Reclaiming Moores law through energy efcient
integrated circuits, Proc. IEEE, vol. 98, no. 2, pp. 253266, Feb. 2010.
S. Jain et al., A 280 mV-to-1.2 V wide-operating-range IA-32 processor in 32 nm CMOS, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers
(ISSCC), Feb. 2012, pp. 6668.
R. Zimmermann, Binary adder architectures for cell-based VLSI and their synthesis, Ph.D. dissertation, Dept. Inf. Technol. Elect. Eng., Swiss Federal
Inst. Technol. (ETH), Zrich, Switzerland, 1998.
D. Harris, A taxonomy of parallel prex networks, in Proc. IEEE Conf. Rec. 37th Asilomar Conf. Signals, Syst., Comput., vol. 2. Nov. 2003, pp.
22132217.
P. M. Kogge and H. S. Stone, A parallel algorithm for the efcient solution of a general class of recurrence equations, IEEE Trans. Comput., vol. C-22,
no. 8, pp. 786793, Aug. 1973.

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