CAIRO UNIVERSITY

FACULTY OF ENGINEERING
Electronics and Communications. DEPT.
Fourth Year

Elective Course :VLSI Design

Dr. Serag Habib
Jan 2010
Time : two hours

Final Exam Solution

Use the process data given at the end of the exam sheet for all problems.
Prob. 1 :
i) Draw the Gajski Y chart. Hence identify, on this chart, how the design is
mapped from high level behavioral description to the final layout
representation if an FPGA design approach is used. Assume that high level
synthesis is carried out manually. Assume that you have a logic level
synthesis tool and a layout synthesis tool.
High level synthesis is done manually from the algorithmic behavioral
level to the RTL behavioral level
Logic synthesis is done using the tool from the behavioral RTL level to
the structural gate level.
Layout synthesis is done using the tool from the gate level netlist to the
cell based layout.

ii) Give two advantages and one disadvantage of SOI CMOS processes relative
to bulk CMOS processes.
Advantages:
Reduce the parasitic capacitance and the power dissipation
Reduce the area (n-well is not required)
Disadvantage:
Higher cost

iii) Complete each of the following statements

a ) Tightening the Design rules reduce the chip area and reduce the
process yield.
b ) STI is commonly used in current CMOS processes as it reduces
the latch-up problems and reduce the area

1/4

Prob. 2 :
a ) Fig. P2 shows a layout of a NOR gate implemented in a two metal layers
N well CMOS process. The layout is drawn on a (1 ) grid and it has
several errors. Identify the errors on the layout and illustrate it below.
(Note the DRC table at end of exam sheet)

1
2

Poly

Active

M1

M2

N Well

N select

P select

contact

M1-M2
Via

Fig. P2
1)

The n-well must extend out of active by 5

2)

Active without select

3)

Via exact width and length must be 2 x 2

4)

Poly extension out of active must be 2

5)

No n-well plug

2/4

Prob. 4 :
i ) An output pad with an equivalent capacitance CL = 1000 ( 2Cg) is
drived by the circuit shown in Fig. P4. find the optimum transistor sizes
for inverters A and B so that the total propagation delay is minimum.
Assume n and p transistors of inverter C are minimum size. Assume
n/up = 2. What is the attained minimum delay.
B

CL

Fig. P4
Let the width of the nmos and pmos of inverter B = 1 2
The load capacitance of inverter B will be multiplied by M1
And the on-resistance of inverter B will be devided by M1
Let the width of the nmos and pmos of inverter A = 2 2
The load capacitance of inverter A will be multiplied by M2
And the on-resistance of inverter A will be devided by M2
= ,
8
=
3
Inverter C:
= 21 = 21
16
= 21 =

3 1
16
21 + 1 11
3
1 =
=

2
3 1
Inverter B:

22
22 =

1
1

162
=
22 =

1
31
112
2 =

31

3/4

Inverter C:

2000
2000 =

2
2

16000
=
2000 =

2
32
11000
3 =

32

Total delay:
= 1 + 2 + 3
2 1000
11
= 1 +
+

1
2
3

2 11
= 1 2
= 0 2 = 12
1
1 3

1
1000 11
=

= 0 22 = 10001
2
2
1
3
2
3
1 = 1000
1 = 10 & 2 = 100
ii ) Derive the scaling law for the power dissipation per unit area of a
static CMOS circuit if a generalized scaling law is used if:.
a) The frequency of operation is kept constant between technology
nodes. Assume that the voltage is scaled as 1/ ( is the length
scaling factor)
2

1
=

1
1 2

=
= 2
1

=1

b) If sub-threshold conduction and threshold control problems

require that the voltage be scaled as slow as 0.25 , find out how the
frequency of operation should be scaled between the technology
nodes if the power dissipation per unit area should be kept constant.
= 0.25
= 0.5
= 0.5
Comment on your results:
In order to keep the power dissipation per unit area constant, the
frequency should be reduced by 0.5
4/4