GOODLUCKTOEVERYONE!

Sosoonbeforethefinal,Ihavedisablededitingandenabledcommenting/viewingonly.
cTHANKYOU!)
ADDEDSOMEDATAPATHSNEARTHEEND.Hopethathelps.

1.WhatisthedecimalequivalentoftheIEEE754floatingpointnumber:
11000000010010000000000000000000
Wehavetosubtract127fromittogetthenumberoftimestheoriginalbinarynumberwas
shiftedbasedonitspower.So128127=1.Now,wejustshifttheexponenttotherightonce.So
wegotfrom1.1001to11.001,ignorethe0sintheexponentwhenshifting.
]
Wenowhave11.001
Soweturnthefirst11intodecwhichis3.
Thanweturnthelast001intoa1indechoweverwehavetodividethat1byhalfacertain
numberoftimesbasedonthebitsthereareinthefractionpart,inthiscase3:001
So=.5>.5/2=.25>.25/2=.125Wedivided3times
Sotheansweris3.125
2.Convertthedecimalnumber#476toa12bittwo'scomplementbinarynumber,and
representtheresultashexadecimal
a.x1BCb.x1BDc.x1DCd.xE23e.xE24f.xE44
First,represent+476asa12bittwoscomplementbinarynumber:
(ex.000000000000correspondsto0*2^11+0*2^10+0*2^9+0*2^8+0*2^7+0*2^6+0
*2^5+0*2^4+0*2^3+0*2^2+0*2^1+0*2^0)
Nowfor476:
2^11=2048>476>0*2^11
2^10=1024>476>0*2^10
2^9=578>476>0*2^9
2^8=256<476>1*2^8
476256=220
2^7=128<220>1*2^7
220128=92
2^6=64<92>1*2^6
9264=28
2^5=32>28>0*2^5
2^4=16<28>1*2^4
2816=12

2^3=8<12>1*2^3
128=4
2^2=4=4>1*2^2
44=0
2^1=2>0>0*2^1
2^0=1>0>0*2^0
So+476asa12bitbinarynumber:000111011100
TwosComplement12bitbinarynumber:NOT+476,thenadd+1:
111000100011+000000000001=111000100100
(finally!)converttohexadecimal:
1110=2^3+2^2+2^1+0*2^0=14=E
0010=0*2^3+0*2^2+2^1+0*2^0=2
0100=0*2^3+2^2+0*2^1+0*2^0=4
SotheanswerisxE24
3.Giventheinstruction(locatedataddressx3500)
x3500LDIR1,label1
andgiven:
label1translatestoaddressx35A0,whichcontainsthevaluexC000
memorylocationxC000containsthevaluexD000
memorylocationxD000containsthevaluexFFFF
WhatvaluewillR1containaftertheinstructionexecutes?
a.x3500
b.xC000
c.35A0
d.xD000
e.xFFFF
LDIisessentiallyapointertoapointertoavalue.Thatis,label1isattheaddressx35A0and
holdsxC000,whichisthenusedasanaddresstofindthevalue,xD000.
Mem[Mem[Label]]<shortexplanationofldi
Mem[Mem[x35A0]]=Mem[xC000]=xD000
4.SimplifytheBooleanexpression:
a.b.c.d+a.b.c.d+a.b.c.d+a.b.c.d+a.b.c.d
a.a.b.c+a.b.d+b.c.d
b.a.d+a.b.c
c.a.c+a.b.d
d.a.c.d+a.b
e.a.c+b.d+b.c

f.cantbesimplified
a.b.c.d+a.b.c.d=a.b.d
a.b.c.d+a.b.c.d=a.b.d
a.b.c.d+a.b.c.d=a.b.c
a.b.d+a.b.d=a.d
a.d+a.b.c
Rememberingthatwecanoranextraterm
a.b.c.dwithoutalteringthevalue(sincex+x=x)
thisiswhatthetutorialstates

5.Howmanymemorylocationscanbeaddressedbyamicroprocessorthatuses24bit
addressing?
2^24=2^4*2^20=16M
a.16k
b.512k
c.16M
d.2G
e.4G
f.noneoftheabove
6.Howmanyselectlinesdoesan8inputmultiplexerhave?
2^3=8,so3selectlines
a.1b.2c.3d.8e.64f.256
7.Howmanyinputlinesdoesan8inputmultiplexerhave?
8inputslines...becausetheres8inputs.Weirdquestion
a.1b.2c.3d.8e.64f.256
8.Howmanyoutputlinesdoesan8inputmultiplexerhave?
Remembermultiplexersonlyhave1output!
a.1b.2c.3d.8e.64f.256

9.Howmanyinputsdoesafulladdercircuithave?
Fulladderhas3inputsA,B,andtheCarry
a.1b.2c.3d.4
e.Itdependsonthenumberofbitsinthenumbersbeingadded
Rememberthatafulladdercircuithas2outputsdontgettricked!

10.Agatedelaycanbedescribedasthetimeneededfortheoutputofagatetosettle

toitscorrectlevelafteroneofitsinputshasbeenchanged.Thefulladdercircuitwe
havedesignedwouldthereforeresultinagatedelayof2units.
Howmanyunitsofgatedelaywoulda4bitrippleadderdisplay?
a.2b.4c.8d.16e.32
Foreachbitoftherippleadderdisplay,thereisacircuitthatcarriestheum,electricsignal?
throughit.Andforeachcircuitthatitiscarriedthrough(4circuitsinthiscase),thereisagate
delayofnunits(2inthiscase).2+2+2+2or2*4=8
Juantoldmethis,Ihave(misguided?)faithinhim!

11.Howdoweturn8separategatedDlatchesintoasingle8bitregister?
(WE="WriteEnable")
a.connecttheWEofeachoneseparatelytoanoutputofa3bitdecoder,andmultiplextheir
outputswith
thesamedecoder
b.connecttheinputsofeachoneseparatelytoanoutputofa3bitdecoder,andmultiplextheir
WEswiththesamedecoder
c.Usea3bitdecoderasaselector,multiplextheirWEs
d.connecttheirWElinestogethertoasingleexternalWE
e.supergluethemtogether
12.Howdoweturn8separategatedDlatchesinto8addressableregisters,each1bit
wide?
a.connecttheWEofeachoneseparatelytoanoutputofa3bitdecoder,andmultiplextheir
outputswiththesamedecoder
b.connecttheinputsofeachoneseparatelytoanoutputofa3bitdecoder,andmultiplextheir
WEswiththesamedecoder
c.Usea3bitdecoderasaselector,multiplextheirWEs
d.connecttheirWElinestogethertoasingleexternalWE
e.supergluethemtogether

13.Thefollowingverycomplexsubroutinemovesthecursordowntothenextline.
What,ifanything,iswrongwithit?
.ORIGx4000
NEWLINELDR0,CRLF
OUT
RET
CRLF.FILLx0A
Needtobackuptheregistersyouuse,inthiscase,R0becauseitischangedandalwaysR7
a.Nothingit'sfineasitis

b.x4000isnotavalidstartingaddressforasubroutine
c.itshouldsaveandrestorethecontentsofR0
d.itshouldsaveandrestorethecontentsofR7
e.bothc)andd)
14.Asubroutinewascalledusingaconditionalbranch(BR)instruction.Thesubroutine
ends,asusual,withaRETinstruction.Whatwillhappenwhenthesubroutine
terminates?
a.ControlwillreturntotheoriginalBRinstruction
b.ControlwillreturntotheinstructionfollowingtheBRinstruction
c.Controlwillreturntoanunknowninstruction,eithercrashingtheprogramorproducing
unpredictableresults.
d.ItwilldependonwhichoftheNZPconditioncodestheBRinstructiontested
TheproblemhereisthatBRdoesnotstoretheoriginalPCinR7likeJSRorJSRRwould.
InsteaditoverwritesthePCwiththelabelintheinstructioniftheconditionsmeetandjumps
there.SowhenRETdecidestotrytojumpbacktoanaddressstoredinR7,itwillcause
unpredictableresultsbecausetheoriginallocationwasneversavedproperlybeforeinR7soR7
holdsjunk.
Thenextthreequestionsrefertothefollowingscenario:
Considerthecontrollerofanelevatorthatconnectsthe1st,2nd,3rd&4thfloorsofabuildingas
anexampleofafinitestatemachine.
ThestatesofthisFSMcorrespondtotheelevatorstoppedateachofthefourfloors,eitherwith
thedoorsclosed,orwiththedoorsopen(i.e."doorsopen"and"doorsclosed"areseparate
states).
Transitionsbetweenstateswillthuscorrespondtotheelevatormovingbetweenfloors,
includingexpresstransitionsbetweennonadjacentfloors,andopeningandclosingdoorswhile
stoppedatanygivenfloor(obviously,theelevatorcanmoveonlyifthedoorsareclosed)
Externalinputsaredeterminedbytheelevatorcallbuttons.
15.Howmanyseparatestatesdoesthisfinitestatemachinehave?
Sincetheres4floors,andeachhas2states(openorclosed),4*2=8totalseperatestates
a.4
b.6
c.8
d.12
e.16
f.32
16.Howmanydistincttransitionsaretherebetweenstates(notincludingnull
transitions,i.e.transitionsfromastatebacktoitself)?
SincewearenotcountingtheNULLtransitionwewillhave3transitionstootherfloorsinsteadof

4becauseeachfloorcanonlygotootherfloorsnotthecurrentflooritisat.So4floorsand3
transitionseach.4*3=12.Plusthe8totalseperatestates.12+8=20distincttransitions
a.8
b.12
c.16
d.20
e.24
f.insufficientinformation
17.HowmanybitswouldtheStorageLogiccomponentofthefsmhavetostore?
a.1
b.2
c.3
d.4
e.5
f.huh??
weneed3bitstorepresent8
18.Acomputersystemhasawordaddressablememory.Eachwordis32bits(4bytes)
wide.Thereare24memoryaddresslines.Whatisthemaximumavailablesystem
memory?
Addressspace*Adressability(inbytes)=TOTALMEMORY
16M(AddressSpace)*4bytes(Addressability)=64Mbytes
a.64kbytes
b.16Mbytes
c.64Mbytes
d.256Mbytes
e.4Gbytes
f.16Gbytes
19.Howmanydatalinesarerequiredforthesysteminthepreviousquestion?
Datalinesareprettymuchtheamountoflinesthatareneededforeachbitinaword.Inthiscase
ourwordis32bits,sowewillneed1datalineforeachbitoftheword.
a.8
b.16
c.24
d.26
e.28
f.32
Isupposeiftheaddressabilityis32bits,thenthissystemisa32bitsystemright?Thenat
maximumtherewouldbe32circuits?and32decodersetc.todoallthecontrolandprocessing
tasksinthecomputersystem.DatalinesIguessarereferringtothenecessary32linesunder

thehoodthatproduces1sand0sforalltheprocessesinthecomputer.
20.Ifthesysteminthepreviousquestionswereinsteadbyteaddressable,andwereto
retainthesametotalnumberofbytesofmemory,howmanyaddresslineswouldit
require?
Beforeitwas:
4byte(addressability)*16M(addressspace)=64Mbytestotalavailablememory
Butnowwithbyteaddressability:
1byte(addressability)*x(addressspace)=64Mbytestotalavailablememory
x(addressspace)=64M
64M(addressspace)=2^20+2^6=2^26
a.8
b.16
c.24
d.26
e.28
f.32
21.Givenaverypeculiarmemorysystemthatuses22bitaddressing,andis"threebit"
addressable(i.e.eachlocationinmemorystores3bits),howmanybitsofstoragedoes
thememorycontainintotal?
a.88bits
b.64kbits
c.1Mbits
d.12Mbits
e.16Mbits
f.64Mbits
22bits=4M*3bits=12Mbits
TheprefixMtakesontheunitMbitsinsteadofMbyteswhenyoumultiplyby3bits.

22.ThecentralideainthevonNeumannmodelisthattheprogramanddatabothreside
in:
Moreofadefinitionquestion
a.multiplexers
b.decoders
c.adders
d.memory
e.switches

f.models
Thenextthreequestionsrefertothefollowingsystem:
AcertainISAhasa32bitwordsize,usessingleword(32bit)instructions,has60opcodes,32
registers,and4Gbyteofbyteaddressablememory.
OnegroupofinstructionsinthisISAtakestheform:
OPCODE|DESTINATIONREGISTER|SOURCEREG.|Flag|IMMEDIATEVALUE
Or
OPCODE|DESTINATIONREGISTER|SOURCEREG.1|Flag|SOURCEREG.2
Asinglebitintheinstruction("Flag")isusedtodifferentiatethesetwoaddressingmodes.
Anothergroupofinstructionstakestheform
OPCODE|SOURCE/DESTINATIONREGISTER|PCOFFSET
WherePCOffsetisthe2scomplement"distance"fromthecurrentPCtothelabelledlocation.
60Opcodes=6bits
32Registers=5bits
23.WhatistherangeofvaluesthatcanbestoredintheImmediatefield(asa2s
complementvalue)?
Use
OPCODE|DESTINATIONREGISTER|SOURCEREG.|Flag|IMMEDIATEVALUE
32(wordsize)6(opcode)5(Register)5(Register)1(Flag)=15bitsfortheimmediate
2^15=32K=(16)to+(16k1)
a.16to+15
b.0to(64k1)
c.16kto+(16k1)
d.32kto+(32k1)
e.64kto+(64k1)
24.Howmanybitsarerequiredforaddressing(i.e.whatisthesizeinbitsofan
address)?
a.16
b.24
c.32
d.48
e.4G
4G=2^32so32bits
poop

25.Howfar(inmemorylocations)canthelabelbefromaninstructionthatreferences
thelabel,usingthe<opcode|register|pcoffset>addressingmode?
Youmayassumethatinthisassemblylanguage,eachlineofsourcecodeassemblestoa

singleoneword(32bit)instruction.
OPCODE|SOURCE/DESTINATIONREGISTER|PCOFFSET
32(wordsize)6(opcode)5(Reg)=21
21bits=2M=+/1M
a.+/32k
b.+/64k
c.+/128k
d.+/256k
e.+/512k
f.+/1M
26.AnISAspecifiesawordsizeof8byteswordaddressabilityandanaddressspaceof
4Gitusessinglewordinstructions(i.e.eachinstructionisasingle8byteword).
WhatarethesizesofthePCandtheIR?
a.both24bits
b.both32bits
c.both64bits
d.PC:24bitsIR:64bits
e.PC:64bitsIR:32bits
f.PC:32bitsIR:64bits
27.Forthesysteminthepreviousquestion:WhatarethesizesoftheMDRandthe
MAR?
a.both24bits
b.both32bits
c.both64bits
d.MAR:32bitsMDR:64bits
e.MAR:64bitsMDR:32bits
f.MAR:24bitsMDR:64bits
RecalltheFetchmicroinstructionsinCh4Slide#14or#31ofthispdf:
BoththeMARandthePChavetodowithaddressspace,whichis4G=2^32=32bits.
BoththeMDRandtheIRhavetodowiththeinstructionsandwordsize,whichis8bytes=32
bits.SinceLC3uses2wordinstructions,youneed2*32bits=64bits.Im100%positivethat
thisistrue,butcansomeonebackitupwithsomesortofproperexplanation?lol
^^WearenottalkingabouttheLC3intheseseriesofquestions.TheISAwasdefinedwithan8
byteword.Thismeansthatasinglewordis8*8bits=64bits.Sowhatthismeansisthatthere
are4Glocationsandeachlocationpointsto64bits.Nowthinkofalabelforthismachinealabel
namesanaddresslocationandsowhatcanthelabelstore?Thelabelsdatawouldbelimitedto
thewordsize.ThuswearedealingwithDatathatis64bitslongandtheMDRshouldbethat
size.

^imgladpeoplearestillawake
28.ConsiderthefollowingLC3codefragment(thehexvaluesinthefirstcolumngive
theaddresstowhichthecorrespondinginstructionisloaded):
x34FEloop1ADDR4,R5,R6
.....
x35A0BRnploop1NOTETHETESTIS"np"
Given:theBRopcodeis0000NZP
Whatdoestheinstructionatx35A0assembleto?(Remembertoaccountforthecurrent
valueofthePCwhentheBRinstructionisbeingexecuted,andthedirectionofthe
"jump",andtheconditioncodestobetested)
a.x0B5D
b.x0B5E
c.x0B5F
d.x0AA1
e.x0AA2
f.x0AA3
Thisquestionisbasicallyaskingforthehexadecimalrepresentationforthe16bitbinary
instructionBR(np)fromalocationx35A0tolocationx34FE.Todothis,onecanrememberfrom
classorfromtheendofthelab08pdfthatthebinaryinstructionforBRlookslike:
0000101xxxxxxxxx
opcodenzpPCOffset9
Theopcodeisthe4bitcodecorrespondingtowhichinstruction(eg.ST,LD,BR,Trap)the
binaryisreferringto.Inthiscase,0000istheopcodeforBR.
Thethreebitsdenotingnzpindicatewhichcasesarebeingtestedforinthisexamplenandp
arebeingtestedfor,sothosebitsare1swhilethezbitisa0.
PCOffset9meansthe9bit2scomplementpcoffsetvaluetothelabel.ThewayPCoffset
worksisyoufindthedistancebetweenthelocationofPC(thelineaftertheinstructionlineyou
arelookingat),andtheaddressofthememoryyouaretryingtobranchto.x35A0isthelocation
oftheBRinstructionsothelocationofthePCisx35A1.
ThedistanceforthePCOffsetisx35A1x34FE=x00A3
Letmeexplainthissubtractionrealquick:
x35A1x34FEifyouweretotrytosubtractitthewayyoudowithdecimalnumbers,butusinga
baseof16insteadof10,youwouldneedtoborrowdigits,justlikewithregularsubtraction,
right?Soafterborrowingdigitsthedigits/subtractionwouldlooklikethis:
x3|4|(19)|(11)inhexadecimal

x3|4|F|E
_____________
x0|0|A|3
=x00A3
Inthiscase,BRisjumpingtoalocationbackwardsinmemory,sothePCoffsetisconsidered
negative.ThismeanswehavetodothetwoscomplementofxA3beforewecanuseitinthe
binaryform[opcode][n][z][p][PCOffset9].
x00A3=xA3(candropthefirst2hexadecimaldigitstheyhavetobe0anywaysb/cthePC
offsetis+/2^8,anymorewouldcauseoverflow!)
xA3=010100011>NOT>101011100>ADDx1=101011101=x5D
opcodenzpPCOffset9
SothisBRinstructionhasthebinaryform0000101101011101whichinhexadecimalis:
x0B5D
29.Howmanyseparatedecodersarethereforthegeneralpurposeregisterbankinthe
LC3?
a.1b.2c.3d.4e.8
f.Theregisterbankdoesnotrequiredecoders
8registersneed3bitsfor2^3registers.Eachbituses1decoderforaddressing.

30.IntheIndirectmodeofmemoryaddressingintheLC3(e.g.theinstructionsLDIand
STI),theEffectiveAddressiscalculatedby:
RememberitsapointersoMem[PC+SEXT(IR[8:0])]
a.(BaseReg)+SEXT(IR[5:0])
b.(PC)+SEXT(IR[8:0])
c.Mem[(PC)+SEXT(IR[5:0])]
d.Mem[(PC)+SEXT(IR[8:0])]
e.(IR)+SEXT(PC[5:0])
f.Mem[(IR)+SEXT(PC[8:0])]

31.Whatarethe"microinstructions"thatcomprisetheFetchphaseoftheInstruction
cycle?
a.IR<(PC)MAR<(IR)PC<Mem[MDR]PC<(PC)+1
b.PC<(MDR)+1MAR<Mem[PC]IR<(MDR)
c.MAR<(PC)+1MDR<Mem[IR]IR<(MAR)
d.MAR<(PC)PC<(PC)+1MDR<Mem[MAR]IR<(MDR)
e.MDR<(PC)PC<(PC)+1MAR<Mem[MDR]IR<(PC)

32.HowdoesthecontrolunitdecidewhethertotakethebranchpointedtoinaBR
instruction?
(n,z&prepresentIR[11:9]N,Z&Prepresentthevaluesoftheconditioncode
registers)
IfyoufollowthedatapathoftheBRinstructionneartheendofthedatapathwhenitLD.PC,it
checksif(n.N+z.Z+p.P)=1,andWEthePC
a.if(n.N+z.Z+p.P)=1,theMARiswriteenabled
b.if(n.N+z.Z+p.P)=1,thePCiswriteenabled
c.if(n.N+z.Z+p.P)=1,theEAcorrespondingtothelabeliscalculated
d.if((n+N).(z+Z).(p+P))=1,theMARiswriteenabled
e.if((n+N).(z+Z).(p+P))=1,thePCiswriteenabled
f.if((n+N).(z+Z).(p+P))=1,theEAcorrespondingtothelabeliscalculated
33.AllcontrolinstructionsintheLC3haveonemainstepincommon:
a.Theyallreconstructtherequiredmemoryaddressinthesameway
b.TheyallusetheALUinreconstructingtherequiredmemoryaddress
c.TheyallwritetotheIRintheexecutionphaseoftheinstructioncycle
d.TheyallwritetothePCintheexecutionphaseoftheinstructioncycle
e.TheyallwritetotheMDRintheexecutionphaseoftheinstructioncycle
f.TheyallwritetotheGPRbankintheexecutionphaseoftheinstructioncycle
ControlinstructionsalwayschangethePC
34.TheLC3instructioncycleconsistsof6phases.Whatdoesthismean?
a.6instructionsrequire1cycle,whiletheotherinstructionsmayrequiremore
b.Eachinstructionconsistsofupto6steps
c.Theexecutestagehas6possibleoperations
d.6ofthe16bitsofaninstructionarededicatedtoopcode
e.Theprocessorhas6mainparts,includingtheALU,registerfile,etc.
35.OneofthefourcontrolsignalstotheLC3ALUis"passthroughinputA"i.e.inputA
isconnecteddirectlytotheoutput.
Whichofthefollowinginstructionswouldusethiscontrolsignal?
ST,STI,andSTRallpassthroughtheALUKaccordingtotheirdatapaths
a.NOT
b.LD,LDI&LDI
c.ST,STI&STR
d.BR&JMP
e.JSR/JSRR
f.TRAP
36.IntheLC3,theDRdecoderinputcomesfromtheDRMUX.Whataretwoofthe

inputstotheDRMUX?(Hint:thinkabouttheJSRandTRAPinstructions)
Wasoneofthequestionsinourquiz.AlsoinJSRitselectsthe[111]butImnotsurewhy...
JSRselects[111]becausethatisthebinaryrepresentationofR7.Iremembertheprofessor
sayingthatR7ishardcodedasoneoftheinputstotheDRMUXtoholdthereturnaddress.
ThatiswhyifR7isnotbackedupwhenyoucallJSR,yoursubroutinedoesnotknowwhereto
returnto.IftheinstructionTRAPiscalledandyouhappentobeusingR7inyourcalculations,
youwillnoticethatR7willbeoverwrittenassoonastheTrapinstructionisexecuted.Thatis
whyIthink,intheverybeginningofthequarteritwasadvisedthatR7isleftalone.Hopethis
helps.
a.IR[2:0],IR[86]andIR[11:9]
b.IR[8:6]andIR[11:9]
c.[111]andIR[11:9]
d.ThesystembusandIR[11:9]
e.(PC)andIR[11:9]
f.PC[2:0]andIR[11:9]

37.IntheLC3,theSR1decoderinputcomesfromtheSR1MUX.Whataretwoofthe
inputstotheSR1MUX?(Hint:thinkabouttheloadandstoreinstructions)
a.IR[2:0],IR[8:6]andIR[11:9]
b.IR[8:6]andIR[11:9]
c.[111]andIR[11:9]
d.ThesystembusandIR[11:9]
e.(PC)andIR[11:9]
f.PC[2:0]andIR[11:9]
WHY??
ADD/AND/NOT/LD/LDI/LDRhaveSR1in[8:6]andST/STI/STRhaveSR1in[11:9]
SeeLab08(veryend)andthatshouldhelp
38.IntheLC3(andmostISAs),theSystemControlBlock,orTrapVectorTable,
contains:
a.thecompleteTrapServiceRoutines
b.the9bitPCoffsetsoftheTrapServiceRoutineaddresses
c.the8bitentrypointintotheTrapVectorTable
d.thestartingaddressesoftheTrapServiceRoutines
e.thereturnaddressestobeusedafterreturningfromaTrapServiceRoutine
39.Whatisthemainpurposeofthefirstpassofatwopassassembler?
a.todetermineifthecodewillfitintoavailablememory
b.toproducethemachinelanguageequivalentoftheassemblylanguageinstructions

c.tolinkotherpossibleobjectfilesinordertocreatetheexecutable
d.toremoveallpseudoopsfromthecodebeforeitisassembled
e.tobuildasymboltablerelatinglabelstomemoryaddresses
Cananyonetellmethesecondpass?
^thiswasalsome
40.Inacputhatusesthetechniqueofmemorymappingtoaddressports(registersthat
interfacebetweenthecpuandperipherals),howmusttheportsactuallybeaccessed?
a.viadedicatedi/oinstructions.
b.viainterrupts
c.viapolling
d.viastandardLoad/Storeinstructions
e.eithera)ord)
f.noneoftheabove
41.Whatcomponentofthecpugets"interrupted"byanInterruptsignal?(i.e.where
doestheInterruptsignalgoto?)
a.ThePCt
b.ThePCMUX
c.TheMARMUX
d.Theglobalbus
e.TheFSM
f.TheMemoryMappinglogic
42.InInterruptprocessing,whatisthepurposeoftheIACKsignal?<Whereisthisin
theslides/book?
a.Italertsacollectionofperipheralsthatthecpuisavailableandwillserviceinterrupts
b.Itpollsmultipleperipheralstofindwhichinitiatedaninterrupt
c.Itisusedbythecputoflagtoaperipheralthatithascompletedservicingitsinterrupt
d.Itisusedbyaperipheraltoflagtotothecputhatitnolongerrequiresservicing
e.Itisusedbyaperipheralto"lock"thebusonceitsinterrupthasbeenacknowledgedbythe
cpu
43.IntheLC3,theTRAPinstructionandtheinterrupthandlerbothmanagethe
invocationofserviceroutinesinasimilarfashion.Specifically,bothuse:
a.pollingofstatusregisterstodecidewhentoreadfrom/writetoaport
b.atrap/interruptvectorasanentrypointintoatableofserviceroutineaddresses
c.anIACKsignaltodeterminewhichserviceroutineisrequested
d.astacktostoreinformationrequiredforthereturn,allowingnestedcalls
e.asystemoftaskprioritycomparisonstodeterminewhethertoinvoketheserviceroutine
(SeePage260,lastparagraph)
44.WhatsystemstateinformationhastobesavedbeforeaninterruptenabledLC3can

proceedwithservicinganinterrupt?
a.thevalueofeverycontrolsignalproducedbythefinitestatemachine
b.thevalueofeverycontrolsignalproducedbythefinitestatemachine,plusthecontentsofall
Registers
(GPRs,PC,conditioncodes,etc.)excepttheIR
c.thePC
d.thePCandalltheGeneralPurposeRegisters
e.thePC,andthePSR(ProcessorStatusRegister,containingtheNZPconditioncodes,the
Privilegelevel,andthecurrenttaskpriority)Ijustmemorizedthis.
f.thePCandtheMCR(MachineControlRegister)
45.Atwhatpointintheinstructioncycleisaninterrupthandled?
a.atanytimeduringtheentirecycletheinterruptisjustoneofseveralexternalinputstothe
FSM
b.atanytimeduringthefetchinstructionphase
c.onlyattheverystartofthefetchinstructionphase
d.atanytimeduringthelastphase(store)
46.Thedataprotocolofastackdatastructureisknownas
Usefulinnestedloops
a.LIFO(LastIn,FirstOut)
b.FIFO(FirstIn,FirstOut)

47.ThetwomainapproachestoconvertingaHLLsourcecodetoML(Machine
Language)are:
a.directandindirect
b.memorymappingandpollingvergas
c.assemblyanddisassembly
d.interpretingandcompilingJustlookeditup.
e.compilingandlinking
48.ThestructurewhichallowsHigherLevelLanguagestomakenestedfunctioncallsis:
a.Activationrecordsstoredontheruntimestack(FromCS12)
b.Thesymboltable
c.Theframepointer
d.TheProcessorStatusRegister
e.TheMachineControlRegister
49.WhichLC3assemblylanguageinstructionismostlikelytobeusedtocompileaHLL
(HigherLevelLanguage)accesstoalocalvariable:
LDRbecauseitisusedmorelikeapointerinC++.CorrectmeifIamwrong.Youareright.
a.LDRb.LDIc.LDd.TRAPe.JSR

50.WhichregisterismostlikelytobeusedastheBaseRegisterinaccessingthe
variable,inthesituationdescribedinthepreviousquestion?
a.Framepointer(R5intheLC3)Ijustmemorizedthis.Hementionedthisinclassonthur
b.TopofStack(R6intheLC3)
c.ProgramCounter(R7intheLC3)
d.ProcessorStatusRegister

^iuhhavenoideawhataframepointeris.anyone?

SectionII:Writtenanswers
1.15points
Designadigitalcombinationallogiccircuitwithfourinputs:a,b,c&d,where(a,b)
representsone2bitunsignedbinarynumberA{1:0]and(c,d)representsanother2bit
unsignedbinarynumberB[1:0](i.e.bothAandBareintherange0to3).
Thecircuithas4outputs(oryoucanregarditasbeing4distinctcircuits,eachwithasingle
bitoutput)inotherwords,thetruthtablewillhave4inputcolumnsand4outputcolumns.
Theseoutputcolumnstogetherrepesentthe4bitproductY[3:0]
Y=A*B
Forinstance,inputscorrespondingto"3,2"wouldoutputbitscorrespondingto6
Startbydrawingupthetruthtable(6points)(showonlythoserowswhichproducea1in
anyoftheoutputcolumns)
Makesureyoulabelyourinputandoutputcolumnscorrectlyeverythingelse
dependsongettingthetableright!
thenderivethealgebraicexpressionforthethirdbitoftheoutput,Y[2](3points)
andsimplifyit(3points)
Finally,drawtheresultingcircuit(3points)
(Eachpartis"allornothing"nopartialcredit)

Seeproblem3.28inbookandthesolutioninHW4onilearn.

Ithinkthisishowyoudoit...
Mytruthtableisreallymessy/unorganizedbutIthinkyallgettheidea.Sowehave2bitsfromAB
and2bitsfromCD.Wewanttomultiplythe2bitsABandCDandgettheoutputY.Sointhefirst
lineofthetruthtableAB(1inbinary)*CD(1inbinary)=0001=1=Y.ThesecondlineisAB(2)*
CD(2)=0100=4=Y.Andsoon.

TruthTable:
A
0
1
1
1

B
C
1| 0
0|0
0| 1
1| 1

DAB*CD
1
|
1
|
0
|
0
|

O3
0
0
0
0

O2
0
0
1
1

O1
0
1
0
1

O0
1
0
0
0

=Y
=1
=2
=4
=6

Thiscangoonlonger,idkiflinardwantsustoputallpossiblecombinations.

Ithink4and6aretheonlyoneswith1inthe3rdbitintherangeofa2bitproduct,sotheboolean
expressionwouldbesomethinglike:
A.B.C.D+A.B.C.D
Simplified:
A.C.D
Thisshouldbethecircuitforbit3

2.15points
GiventhedatapathoftheLC3(providedbelow),giveacompletedescriptionofthe
STOREDIRECTinstruction(STSR,label),asfollows:
a)GivetheRT(RegisterTransfer)specificationoftheinstruction(4points)
b)Listthedataappliedtoallrelevantcircuitsinthedatapath(i.e.justthosecircuits
relevanttotheSTinstruction)andlist,inthecorrectsequence,everycontrolsignalsetby
theFSMtoimplementthisinstruction.(11points)
Rememberthatnoteverytristatedevicemaybeactuallydepictedontheschematicbut
youmuststillspecifythecontrolsignalifitisinvolved(makeupdescriptivenamesforany
controlsignalsthatarenotshownontheschematic).Likewise,theSRMUXisnotshown,
butyoumuststillincludethecorrectselectcontrolsignalanddatainputforit.
Formultibitcontrolsignals,youmustspecifytheactualvaluewherepossible:
e.g.ifthecontrolsignalisa2bitMUXselector,selectingfortheinputthatisthirdfromthe
right,thenyoumustspecifythevalue10
||||
_|___|__|___|_
|11100100|
|___________|
Ifseveralcontrolsignalsactatthesametime,indicatethatfactotherwiselistthemin
sequence.

btw,thiswasaHWproblem,onHW7(notthatanyonehasdoneanyofthem)
a)STRTN:Mem[(PC)+SEXT(IR[8:0])]SR
Imnotsureaboutwhichcontrolsignalsareturnedonorturnedoffinthiscase.Ifanybodycould
specifyit,thatwouldbegreat.ThisisjustthegeneralpathofST
b)1.SelectSR1MUX:IR[11:9]
2.ALUPassthroughALUK
3.Gate.ALU
4.LD.MDR
5.a.ADDR1MUX:SelectPC,selectsbit0
b.ADDR2MUX:SelectSEXT(IR[8:0]),selectsbit10
6.MARMUX,selectsbit0
7.LD.MAR
8.Memory:Memoryenabledforwritting

3.15points
ConstructtheFiniteStateMachinerepresentationforacounterwithacyclelengthof4i.e.
acircuitthatcounts0123(outputasabinaryvalue,obviously)withsuccessiveclock
pulses,andthenstartsover.
Theexternaloutputisthe2bitcount.
TheonlyexternalinputisR,aresetpulse:whenR=1itresetsthenextcountto0,nomatter
whatthecurrentstatewhenR=0itkeepscounting(i.e.thesystemtransitionstothenext
stateinsequence).
Thenconstructthecompletetruthtable(s)forthedevice,showing
theinputs:"currentstate"labels(ie.thestatewearetransitiongfrom),andR
theoutputs:"nextstate"labels(i.e.thestatewearetransitioningto),andthe2bitcount
associatedwiththatstate.
(Hint:ifyouchoosethestatelabelssensibly,theywillbeidenticaltotheoutput)
Finally,deriveandsimplifythealgebraicexpressionforbit0oftheoutput.
IthinkforthisproblemitismuchlikethedetourrepresentationoftheFSMwedidinlecture,
wherewehavethe4circleseachpointingtothenext,somethinglikethis:

IfRequalsto1atanypointtheFSMgoestothestartingpoint.IfRjustequalsto0itcontinues
counting.
TruthTable:
Cisthecurrentstate,Ristheinputpassedin,Nisthenextstate,andCntisthe2bitcount.
C0
0
0
0
0
1
1
1
1

C1
0
0
1
1
0
0
1
1

R
0
1
0
1
0
1
0
1

|
|
|
|
|
|
|
|
|

N1
0
0
1
0
1
0
0
0

N0
1
0
0
0
1
0
0
0

Cnt
1
0
2
0
3
0
0
0

YoucanseethatwhenevertheRis1,deviceresetsbackto0,butifitis0,thedevicecontinues
countingunlessitisonthelastdevicewhereitwouldalsoreset.
Booleanexpressionforthe0thbit:

C0.C1.R+C0.C1.R
Simplified:
C1.R
IfC1andRareboth0,weknowthatthe0thbitwillbe1

4.5points
AnumberofLC3instructionshavean"evaluateaddress"stepintheinstructioncycle,in
whicha16bitaddressisconstructedandwrittentotheMemoryAddressRegisterviathe
MARMUX.
ListallLC3instructionsthatwritetotheMARduringtheevaluateaddressphaseofthe
instructioncycle,withtheRegisterTransferdescriptionofeach.
ImguessingthesearetheonesthatgothroughtheMARMUXwhenyouwalkthroughthedata
pathsofeachoftheseintructions.Allofthesearedatamov.withtheexceptionoftheTRAP
whichisadatacontrol.CorrectmeifIamwrong.
LDIRTN:DR<Mem[Mem[(PC)+SEXT(IR[8:0])]]
STIRTN:Mem[Mem[(PC)+SEXT(IR[8:0])]]<(SR)
LDRRTN:DR<Mem[(BaseReg)+SEXT(IR[5:0])]
STRRTN:Mem[(BaseReg)+SEXT(IR[5:0])]<(SR)
LDRTN:DR<Mem[(PC)+SEXT(IR[8:0])]
STRTN:Mem[(PC)+SEXT(IR[8:0])]<(SR)
TRAPRTN:R7<(PC),
MARMUXZEXT(IR[7:0])

JSRRTN:R7<(PC)PC<SEXT(IR[10:0])

JSRRRTN:R7<(PC)PC<(BaseReg)(whereBaseRegisIR[8:6])
dothesetwogothroughtheMARMUX?
No,becauserememberJSR/JSRRdonotgoanywhereneartheMARMUXwhenitgetstothe
evaluatephase,whichiswhenADDR1/ADDR2meet,itgoestothePCinsteadoftheMARMUX.
correctmeifimwrongbutiwouldliketocheckuponmyadd
ADDRTN:DR<mem[SEXT(IR[8:6]+SEXT(IR[0:2])]maybetotallyoff
or
ADDRTN:DR<Mem[SEXT(IR[8:6]+SEXT(IR[4:0])]siono?

DATAPATHS
Ifanyarewrongpleasecorrectthem!
LD
1.ADDR1:SelectPC,selectsbit0
ADDR2:SelectsSEXT(IR[8:0]),selectsbit10
2.MARMUXselectsbit0
3.Gate.MARMUX<selects1.ithinkhewantsustospecifywhentheyopenespeciallyfor
gates
4.LD.MDR<LD.MAR
5.Mem,En/W<MEM.EN/R
6.LD.MAR<LD.MDR
(7)*GateMDR
(8)7.LD.REG
LDI
1.ADDR1:SelectPC,selectsbit0
ADDR2:SelectsSEXT(IR[8:0]),selectsbit10
2.MARMUXselectsbit0
3.Gate.MARMUX
4.LD.MDR
5.Mem,En/W
6.LD.MAR
7.LD.MDR
8.Mem,En/W
9.LD.MAR
10.LD.REG
LDR

1.SR1MUX:SelectsIR[8:6]
2.ADDR1MUX:SelectsSR1,bit1
ADDR2MUX:SelectsSEXT(IR[5:0]),bit01
3.MARMUX,bit0
4.GATE.MARMUX
5.LD.MDR
6.MEMEn/W
7.LD.MAR
8.LD.REG

STI
1.ADDR1SelectsSEXT(IR[8:0]),bit10
ADDR2SelectsPC,bit0
2.MARMUX,bit0
3.GATE.MARMUX
4.LD.MDR
5.Do14again.
6.SR1MUX:SelectsIR[11:9]
7.ALU>PassthroughALUK
8.LD.MDR
9.MEMEn/W

STR
1.SR1MUXSelectsIR[8:6]Basereg
2.ADDR1MUXSelectsSR1MUX,bit1
ADDR2MUXSelectsSEXT(IR[8:6]),bit10
3.MARMUX,bit0
4.GATE.MARMUX
5.LD.MDR
6.SR1MUX:Selects[11:9]
7.ALU>ALUK:Passthrough
8.Gate.ALU
9.LD.MAR
JSR
1.ADDR1SelectPC,bit0
2.ADDR2SelectSEXT(IR[10:0]),bit11
3.PCMUX,selectbit10
4.LD.PC

JSRR
1.GATE.PCsomeoneexplainthisplease.where/whythisgate?
2.DRMUXSelectsIR[111]
3.SR1MUXSelectIR[8:6]
4.ADDR1SelectSR1,bit1
5.ADDR2Selects0,bit0
6.PCMUX,selectbit10
7.LD.PC
JMP
1.SR1MUXSelectIR[8:6]
2.ADDR1MUXSelectSR1,bit1
ADDR2MUXSelects0,bit00
3.PCMUX,bit01
4.LD.PC
BR
1.ADDR1MUXSelectPC,bit0
ADDR2MUXSelectSEXT(IR[8:0]),bit10
3.PCMUX,bit01
4.if(n.N+z.Z+p.P)
5.LD.PC

ADD
1.someone
2.please
3.fill
4.me
5.out
6.forboth(2registers)and(registerandhardcode)