Beruflich Dokumente
Kultur Dokumente
1. General description
The HEF4081B is a quad 2-input AND gate. The outputs are fully buffered for highest
noise immunity and pattern insensitivity to output impedance variations.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
3. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +125 C.
Type number
Package
Name
Description
Version
HEF4081BP
DIP14
SOT27-1
HEF4081BT
SO14
SOT108-1
4. Functional diagram
1
2
1A
1B
2A
2B
3A
3B
12
4A
13
4B
1Y
2Y
3Y
10
4Y
11
nA
nB
001aai139
Fig 1.
Functional diagram
nY
001aag180
Fig 2.
HEF4081B
NXP Semiconductors
5. Pinning information
5.1 Pinning
1A
14 VDD
1B
13 4B
1Y
12 4A
2Y
2A
2B
VSS
HEF4081B
11 4Y
10 3Y
9
3B
3A
001aag178
Fig 3.
Pin configuration
Pin description
Symbol
Pin
Description
1A to 4A
1, 5, 8, 12
input
1B to 4B
2, 6, 9, 13
input
1Y to 4Y
3, 4, 10, 11
output
VSS
ground (0 V)
VDD
14
supply voltage
6. Functional description
Table 3.
Function table[1]
Input
Output
nA
nB
nY
[1]
HEF4081B
2 of 12
HEF4081B
NXP Semiconductors
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
Parameter
VDD
supply voltage
IIK
VI
input voltage
IOK
II/O
input/output current
IDD
supply current
50
mA
Tstg
storage temperature
65
+150
Tamb
ambient temperature
40
+125
Ptot
Conditions
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
Min
Max
Unit
0.5
+18
10
mA
0.5
VDD + 0.5
10
mA
10
mA
Tamb = 40 C to + 125 C
power dissipation
DIP14
[1]
750
mW
SO14
[2]
500
mW
100
mW
per output
[1]
For DIP14 packages: above Tamb = 70 C, Ptot derates linearly with 12 mW/K.
[2]
For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K.
Symbol
Parameter
Min
Max
Unit
VDD
supply voltage
Conditions
15
VI
input voltage
VDD
Tamb
ambient temperature
in free air
40
+125
t/V
VDD = 5 V
3.75
s/V
VDD = 10 V
0.5
s/V
VDD = 15 V
0.08
s/V
9. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
VIH
VIL
HIGH-level
input voltage
LOW-level
input voltage
HEF4081B
Conditions
IO < 1 A
IO < 1 A
VDD
Max
Min
Max
Min
Max
Min
Max
5V
3.5
3.5
3.5
3.5
10 V
7.0
7.0
7.0
7.0
15 V
11.0
11.0
11.0
11.0
5V
1.5
1.5
1.5
1.5
10 V
3.0
3.0
3.0
3.0
15 V
4.0
4.0
4.0
4.0
3 of 12
HEF4081B
NXP Semiconductors
Table 6.
Static characteristics continued
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
VOH
VOL
IOH
IOL
HIGH-level
output voltage
IO < 1 A
VDD
Max
Min
Max
Min
Max
Min
Max
4.95
4.95
4.95
4.95
10 V
9.95
9.95
9.95
9.95
15 V
14.95
14.95
14.95
14.95
5V
0.05
0.05
0.05
0.05
10 V
0.05
0.05
0.05
0.05
5V
LOW-level
output voltage
IO < 1 A
15 V
0.05
0.05
0.05
0.05
HIGH-level
output current
VO = 2.5 V
5V
1.7
1.4
1.1
1.1
mA
VO = 4.6 V
5V
0.64
0.5
0.36
0.36
mA
VO = 9.5 V
10 V
1.6
1.3
0.9
0.9
mA
LOW-level
output current
II
input leakage
current
IDD
supply current
CI
Conditions
input
capacitance
HEF4081B
VO = 13.5 V
15 V
4.2
3.4
2.4
2.4
mA
VO = 0.4 V
5V
0.64
0.5
0.36
0.36
mA
VO = 0.5 V
10 V
1.6
1.3
0.9
0.9
mA
VO = 1.5 V
15 V
4.2
3.4
2.4
2.4
mA
15 V
0.1
0.1
1.0
1.0
5V
all valid input
combinations; 10 V
IO = 0 A
15 V
0.25
0.25
7.5
7.5
0.5
0.5
15.0
15.0
1.0
1.0
30.0
30.0
7.5
pF
4 of 12
HEF4081B
NXP Semiconductors
tPHL
LOW to HIGH
propagation delay
tPLH
Conditions
VDD
nA or nB to nY
nA or nB to nY
Extrapolation formula
Min
Typ
Max
Unit
5V
28 ns + (0.55 ns/pF)CL
55
110
ns
10 V
15 V
14 ns + (0.23 ns/pF)CL
25
50
ns
12 ns + (0.16 ns/pF)CL
20
40
ns
5V
18 ns + (0.55 ns/pF)CL
45
90
ns
10 V
9 ns + (0.23 ns/pF)CL
20
40
ns
7 ns + (0.16 ns/pF)CL
15
30
ns
60
120
ns
15 V
HIGH to LOW output
transition time
tTHL
tTLH
[1]
5V
10 ns + (1.0 ns/pF)CL
10 V
9 ns + (0.42 ns/pF)CL
30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
20
40
ns
5V
10 ns + (1.00 ns/pF)CL
60
120
ns
10 V
9 ns + (0.42 ns/pF)CL
30
60
ns
15 V
6 ns + (0.28 ns/pF)CL
20
40
ns
The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).
Table 8.
Dynamic power dissipation
VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
PD
VDD
Typical formula
where:
HEF4081B
5 of 12
HEF4081B
NXP Semiconductors
11. Waveforms
tr
VI
tf
90 %
nA, nB input
VM
0V
10 %
tPLH
VOH
tPHL
90 %
nY output
VM
VOL
10 %
tTLH
tTHL
001aai140
Fig 4.
Table 9.
Measurement points
Supply voltage
Input
Output
VDD
VM
VM
5 V to 15 V
0.5VDD
0.5VDD
VDD
VI
VO
DUT
CL
RT
001aag182
Fig 5.
Test circuit
Table 10.
Test data
Supply voltage
Input
VDD
VI
tr, tf
CL
5 V to 15 V
VSS or VDD
20 ns
50 pF
HEF4081B
Load
6 of 12
HEF4081B
NXP Semiconductors
SOT27-1
ME
seating plane
A2
A1
c
e
w M
b1
(e 1)
b
MH
14
pin 1 index
E
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b1
D (1)
E (1)
e1
ME
MH
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
2.2
inches
0.17
0.02
0.13
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.1
0.3
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
Fig 6.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT27-1
050G04
MO-001
SC-501-14
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
HEF4081B
7 of 12
HEF4081B
NXP Semiconductors
SOT108-1
A
X
c
y
HE
v M A
Z
8
14
Q
A2
(A 3)
A1
pin 1 index
Lp
1
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
D (1)
E (1)
HE
Lp
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.16
0.15
0.010 0.057
inches 0.069
0.004 0.049
0.05
0.244
0.039
0.041
0.228
0.016
0.028
0.024
0.01
0.01
0.028
0.004
0.012
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig 7.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
HEF4081B
8 of 12
HEF4081B
NXP Semiconductors
Revision history
Document ID
Release date
Change notice
Supersedes
HEF4081B v.7
20111116
HEF4081B v.6
Modifications:
HEF4081B v.6
20091202
HEF4081B v.5
HEF4081B v.5
20090629
HEF4081B v.4
HEF4081B v.4
20080526
HEF4081B_CNV v.3
HEF4081B_CNV v.3
19950101
Product specification
HEF4081B_CNV v.2
HEF4081B_CNV v.2
19950101
Product specification
HEF4081B
9 of 12
HEF4081B
NXP Semiconductors
Product status[3]
Definition
Development
This document contains data from the objective specification for product development.
Qualification
Production
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warranty and liability Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
HEF4081B
10 of 12
HEF4081B
NXP Semiconductors
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
HEF4081B
11 of 12
HEF4081B
NXP Semiconductors
16. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
14.1
14.2
14.3
14.4
15
16
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional description . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 3
Static characteristics. . . . . . . . . . . . . . . . . . . . . 3
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9
Legal information. . . . . . . . . . . . . . . . . . . . . . . 10
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Contact information. . . . . . . . . . . . . . . . . . . . . 11
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.