Apr. 2009, Volume 6, No.4 (Serial No.

53)

Journal of Communication and Computer, ISSN 1548-7709, USA

Range-Doppler image processing in linear FMCW radar and

FPGA based real-time implementation
WANG Zong-bo1, Javier Carretero Moya2, Alvaro Blanco del Campo2, Javier Gismero Menoyo2, GAO Mei-guo1
(1. Department of Electronic Engineering, Beijing Institute of Technology, Beijing 100081, China;
2. Department of Signals, Systems and Radio Communications, Universidad Politecnica de Madrid, 28040 Spain)
Abstract: The paper introduces an FPGA based signal
processing system to perform Range-Doppler processing in
real-time for Linear FMCW (frequency Modulated Continuous
Wave) radar systems. Novel design architecture in FPGA is
proposed and experimental results indicate that the design can
verify the correct operation of the processing flow. The
Ping-Pang architecture in FPGA saves the resources in chip and
the system has been designed so as to allow future addition of
complex target detection algorithms.
Key words: FPGA implementation; real-time system; Doppler
process; LFMCW radar

1.
Linear
FMCW
radar
range-Doppler image processing

integration of several frequency sweepings.

Range-Doppler images can be used later for
identification and classification algorithms[3].
f

fb

and

Tm
Fig. 1

Linear FMCW radars obtain target information

by continuously transmitting Linear Frequency
sweeps and mixing the delayed echoes from targets
with a sample of the transmitted signal. The target
range information can be extracted from the
spectrum of this mixed signal (Fig. 1). Because of
the wide-spectrum and the narrow beam width that
can be easily achieved, this kind of radar can work
with high resolution and small size[1-2]. The
Range-Doppler Image can be obtained after coherent

Transmit and echo signals of linear FMCW

radar in the frequency-time domain

As illustrated in Fig. 1, f is the transmitted

signal bandwidth, Tm is the period of the modulator
signal, the echo of the target at range R cause a delayed
version of the transmitted signal (dotted line), f b is the
frequency difference of the echo and the transmitter,
called beat frequency. c is the propagation velocity.
The range information can obviously get from f b by
the formula:

R=
WANG Zong-bo, Ph.D. candidate; research fields: radar
signal processing and real-time digital signal processing
systems.
Javier Carretero Moya, Ph.D. candidate; research fields:
statistical signal processing and detection theory.
Alvaro Blanco del Campo, Ph.D.; research fields: ISAR
signal processing and CWLFM radar systems.
Javier Gismero Menoyo, professor; research fields: high
frequency device modeling, microwave circuits design, and
radar systems.
GAO Mei-guo, professor; research fields: radar
countermeasure, radar signal processing and radar systems.

fb * Tm * c
2* f

So the basic signal processing of Linear FMCW

radar is to get the beat frequency. The target's
movement would provoke the delay of the echo signal
not to be constant, but if the delay change is slow
enough only the phase of the video signal would be
changed (Doppler Frequency), so the Doppler

55

Range-Doppler image processing in linear FMCW radar and FPGA based real-time implementation

information from the cross range by Doppler

processing, the Range-Doppler Image can get after the
range-Doppler processing[4].
The common method for Doppler processing is
the Fourier Transform[5], according to Linear FMCW
radar, the Range-Doppler processing can be achieved
by two-dimension FFT, so the tasks that need to be
performed are two FFTs: the first one to the samples of
each frequency sweep to get a range profile, and the
second one to the samples of the same range cell from
consecutive frequency sweeps to extract Doppler
information.

Range

(1,1)

(1,2)

....

(1,N-1)

(1,N)

(2,1)

(2,2)

...

(2,N-1)

(2,N)

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

(M-1,1)

(M-1,2)

...

(M-1,N-1)

(M-1,N)

(M,1)

(M,2)

...

(M,N-1)

(M,N)

...

1st F F T

ADC data

...
Range-Time Matrix

Time
2nd F F T

Range
...

2. Implementation of range-Doppler
image processing in FPGA

(1,1)

(1,2)

....

(1,N-1)

(1,N)

(2,1)

(2,2)

...

(2,N-1)

(2,N)

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

(M-1,1)

(M-1,2)

...

(M-1,N-1)

(M-1,N)

(M,1)

(M,2)

...

(M,N-1)

(M,N)

Range-Doppler Matrix
Doppler

2.1 FFT based Range-Doppler process general

The radar we have developed uses the homodyne
scheme, the receiver mixes an attenuated copy of the
transmitted signal with the echoes, to get video
signal[6-7].The Range-Doppler processing using FFT is
shown in Fig. 2: The video signals are sampled
synchronously and convert into processible digitalize
signal. When finished sampling of one sweeping cycle
with N points, the first FFT should be done to get the
spectrum of this sweep, the result of the first FFT(N
points) containing all the range information is recorded
in each row of the matrix. After accumulation of M
times of sweeps, one M*N matrix with Range-Time
information is created. Then the second FFT for the
Doppler information should be finished from the
cross-range direction, the input data for the second FFT
should be fetched out from each column of the matrix,
after doing N times second FFT ,the M*N matrix of
Range-Doppler is created.
2.2 The architecture design in FPGA
There are several important aspects should be
taken into account when implementing the process
illustrated in Fig. 2 in FPGA based system application.

Fig. 2

Rang-Doppler image processing in

linear FMCW radar

(1) Before getting the Range-Doppler matrix, the

Range-Time matrix should be stored as the temp
resource for the 2nd FFT. In discuss, the FFT result
contains both real part and image part and with the
scale schedule to keep the same bits width of the input
data, the AD converter has the bits accuracy of K bits,
so the memory capacity for the temp data should be at
least M*N*2*Kbits. In our case, the ADC converter we
are using has 14 bits accuracy, and 8192 points are
sampled in each sweep (N=8192), 256 points are
accumulated for the Doppler information (M=256), the
memory capacity we need is around 64Mbits, it is quite
large compared with the memory capacity inside
FPGA, so memory banks outside FPGA must be used
for the temp store of data.
(2) The data read direction is orthogonal with the
write direction for the memory. We can first think the
memory address space is linear and the write sequence
of the 1st FFT result into the memory is continuously,
one write address contain one point of the 1st FFT's
result(compact),then the N points write address should
generated as:
(m * N , m * N + 1, m * N + 2,K , m * N + N 1), m = 0,1, 2,K , M .

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Range-Doppler image processing in linear FMCW radar and FPGA based real-time implementation

The M points read address should be generated as:

(0* N + m,1* N + m,K , ( M 1) * N + m), n = 0,1, 2,K , N .

(3) For this 2-step's process, we do not want to

lose data of the first step when doing the second step
process, so a special Ping-Pang architecture is designed
to make sure the whole process can be finished with the
continuous input data flow.

We use one chip of FPGA (Xilinx VirtexII)

together with SDRAM to finish the process, 2 banks of
SDRAM each with 32bits width are used for the store
of the temp matrix data. In actually design, we use
N=8192, M=256, the next discuss are based on these
parameters. Fig. 3 shows the detailed block gram
design (FPGA inside the dotted line).

DDR SDRAM

DDR SDRAM
Controller(Pang)

OUTPUT_FIFO
(Ping)

OUTPUT_FIFO
(Pang)

OUTPUT Switcher

ADC input

1st F F T

INPUTSwitcher

INPUT_FIFO

DDR SDRAM
Controller(Ping)

2nd FFT
Data output

DDR SDRAM

Fig. 3

Architecture design of FPGA

The whole system is contributed by the following

modules listed by process sequence:
(1) INPUT_FIFO: In a heterodyne scheme, the beat
frequency containing range information is in relatively
low frequency, so the ADC sample rate does not need to
be very high. For real-time processing and the new
FPGA technique, the main process can be done at several
hundred mega Hz, so an INPUT_FIFO is included in
front of the main process to solve the problem of
cross-time region design in FPGA. The wr_clk of the
INPUT_FIFO is the same with the sample rate of ADC
(10Mhz), the rd_clk is connected the high speed
(100Mhz) clock for the main process. The length of the
FIFO is exactly the same with the points of the 1st FFT.
(2) 1st FFT: The function of the 1st FFT module is
getting the spectrum of the video signal. The FFT
module here uses the Cooley-Turkey algorithm for
computing, with the transform size of 8192, the output
of the FFT module is complex number in natural output
order.

(3) INPUT SWITCHER: The switcher is used to

select the data flow direction, the results of the 1st FFT
are send to the DDR SDRAM controller which at the
time is working at the write mode.
(4) DDR SDRAM CONTROLLER: The same ddr
sdram controller is duplicated to form architecture of
Ping Pang, each controller can work independently at
write mode and read mode. While one controller is
working at read mode to read data from DDR SDRAM
for the next step's process, the other must work at write
mode to write the data into another bank of DDR
SDRAM to make sure no data lost.
(5) OUTPUT FIFO: Because the access to the
DDR SDRAM is burst oriented, and in the case of
Doppler processing, the address for the read from DDR
SDRAM is discontinous, another FIFO must be added
to store the data read from DDR SDRAM, and the
length of this FIFO is 256, the same with the transform
size of the 2nd FFT.

57

Range-Doppler image processing in linear FMCW radar and FPGA based real-time implementation

(6) OUTPUT SWITCHER: This switcher has

similar function with the previous one, the 2nd FFT
module loads data from the output FIFO which the
DDR SDRAM controller at this side is working at the
read mode.
(7) 2nd FFT: The 2nd FFT is used to get the
Doppler information from the cross-range, it is
designed with the same architecture of the 1st FFT
module, but with the transform size of 256, the output of
the 2nd FFT is one column of the Rang-Doppler matrix,
and then send to PC through PCI bus. One
Range-Doppler image with full range scale can get after
gathering 8192 columns data from the 2nd FFT module.
2.3 Signal processing in FPGA
In this section, the signal processing flow and the
control methods together with time analyses are
discussed in detail.
ADC sample rate is 10Mhz, and the Tm in our
design is 0.9ms,9000 points can be sampled in one
sweep while we use 8192 points among 9000 points for
process. This is done by the control of the
INPUT_FIFO write enable signal. The length of the
INPUT_FIFO wr_en is 819.2 us and the wr_en
becomes active at the exactly same point of each sweep
to make sure synchronize sample between sweeps. The
start signal of the 1st FFT module is triggered by the
full signal of the INPUT_FIFO, after the start pulse, the

rd_en signal for the INPUT_FIFO become active, the

FFT module begins the data load from INPUT_FIFO at
100Mhz.After the data frame with 8192 points is
loaded, the FFT module will process the transform and
then output the results.
After getting one sweep's spectrum data, the next
step is to accumulate the spectrum data of 256 sweeps
to form a Range-Time matrix, this matrix is
alternatively stored in two banks of DDR SDRAM, the
write address is generated as discussed in section 1.At
the beginning of the process, the first matrix is stored in
the ping bank of DDR SDRAM and during all the first
256 sweeps, the DDR SDRAM CONTROLLER PING
works at write mode to finish first matrix. A counter is
used to count the times written into DDR
SDRAM,after writing 256 times, the DDR SDRAM
CONTROLLER PING change the work mode from
write to read, while the DDR SDRAM CONTROLLER
PANG's work mode changes from idle to write to start
the writing of the second matrix into pang bank of
DDR SDRAM.The DDR SDRAM CONTROLLER
PING changing into read mode starts reading from the
DDR SDRAM with the discontinuous addresses
discussed in section 1.The read-write changes at the
point of one matrix of Range-Time accumulation
finished. This process continues while one side of DDR
SDRAM is working at read mode, another is working
at write mode. This changing is illustrated in Fig. 4.

DDR SDRAM CONTROLLER PING Writing

DDR SDRAM CONTROLLER PING Reading

DDR SDRAM CONTROLLER PANG Reading

DDR SDRAM CONTROLLER PANG Writing

.........

.........

256 sweeps
Fig. 4

256 sweeps

Ping-Pang switch time diagram

The data read from DDR SDRAM fill into the

OUTPUT_FIFO and the full signal of OUTPUT_FIFO
triggers the start pulse of the 2nd FFT, the source of the

58

.........

2nd FFT module is selected by the switcher, the data

loading by the 2nd FFT module are from the part of the
controller while working in the read mode. Each result

Range-Doppler image processing in linear FMCW radar and FPGA based real-time implementation

of the 2nd FFT module is one column of the final

Range-Doppler image, it is send to PC through PCI bus
and the whole image is formed in PC application
software.

[2]

[3]

3. Conclusions
Linear FMCW radar has lots of advantages and
this kind of radar has been broadly applied in many
fields. An FPGA based signal processing architecture
to get the Range-Doppler Image for Linear FMCW
radar has been proposed and experimental test has been
made to guarantee that with this design idea, we can get
the correct result and achieve it in real-time. The
Ping-Pang architecture design in FPGA also can be
applied into other 2-step signal process algorithms.
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