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I. INTRODUCTION
The CBs are very popular protecting short circuit
device in the industries and the households. The detailed
procedures and testings of CBs are given in IEC 60898
[1]. Traditionally, the current sources for CB tests are
simply designed to use the motor driven tap changing of
auto-transformer for ac output current regulation.
Nowadays, several ac-ac converters have been developed
and improved in terms of higher current rating capability
and higher efficiency. In practice, the ac-ac converters are
widely applied to various industrial applications such as
UPS, voltage stabilizer, electric welding, and etc.
In literatures, several topologies of single-phase ac-ac
converters had been reported such as three-leg ac-ac
converters [2]-[5], ac-ac chopper [6], resonant converter
[7] and ac-ac Z-source converter [8]-[9]. The full-bridge
and half-bridge dc-ac converter structures are among the
popular choices in the UPS applications (1-phase or 3phase applications) [2]-[3]. These topologies consist
mainly of two stages; controlled rectifier (e.g., boost PFC
topology) and half-bridge (or full bridge) inverter. They
can be operated either buck or boost mode of ac output
voltage control with the same or different frequency from
the input voltage frequency.
The buck type ac-ac chopper in [6] controls the ac
output voltage by chopping the ac input voltage.
However, this topology would produce the distortion on
TABLE I
TIME-CURRENT OPERATING CHARACTERISTICS
S3
S4
iT1
iout
T1
C1
D3
C2
vC 2
vC 1
vS
S1
LS
iref
iT 1
vC 1
vC 2
iS
vS
D2
vC 2
D4
S2
iS
D1
vC 1
iS
vS
vS
iS
D1
LS
S1
vS
(a)
iS
D1
D3
C1
(b)
vC2
LS
vS
D1
iS
LS
S2
iS
vS
(a)
D2
D4
C2
TABLE II
CURRENT RATIO OF CURRENT TRANSFORMER (T1) AND THD OF AC
OUTPUT CURRENT
iT1(Arms) iout(Arms)
0.5
43.1
1.0
86.2
1.5
129.4
2.0
173.2
2.5
216.0
3.0
259.0
3.5
303.0
4.0
346.0
Average iout/iT1
(b)
S3
S4
iT1
iout
T1
C1
C2
vC2
vC 1
(a)
iT1
S3
C1
vC 1
S4
T1
iout
C2
vC 2
(b)
Fig.4: Circuit configurations under, (a) positive and (b) negative pulses
of bipolar sPWM operation.
C. Control Strategy
Basically, the control strategy of the circuit is separated
into two parts. The first part is the ac input current control
for power factor correction and the dual dc-link voltage
control. The overall block diagram of this first part is
shown in Fig.5. The waveform reference comes from the
ac input voltage for shaping the ac input current. Each
measured dc-link capacitor voltage is controlled by PI
controller. The outputs of two PI controllers are selected
according to the phase cycle of ac input voltage in the
multiplex block. The absolute ac input voltage is
multiplied with the output of multiplex block in order to
generate the current reference. Then, the absolute ac input
current is shaped its waveform following this current
reference by using PID controller. The output of PID
controller is PFC signal as the modulating signal with the
triangle signal, generating PWM signals of switches S1
and S2.
vC 1
vC2
vS
iS
iout
i out
vS
iS
iT1
i'T1
iout
6,000F
Cf
10 F
Lf
600H
vC1
vC2
fs
400V
400V
20kHz
Vc1
Vc2
vS
iS
vS
iS
iout
vS
iS
Vc1
Vc2
Fig. 10. Simulation results for transient response of dc-link voltages due
to sag voltage of ac input voltage.
vS
iS
iout
Vc1
vS
iS
Fig. 12.Simulation results for CB testing in test a by ramping current
up to 36.16 A(rms) of ac output current.
Fig. 14. Experimental results for steady-state response of dc-link
voltage voltages at 400 V(dc) and ac input voltage and current.
Vc2
Vc1
Vdc ref
Fig. 15. Experimental results for dc-link voltages with step change from
400 to 350 V(dc).
vS
V. EXPERIMENTAL RESULTS
The laboratory prototype was constructed to verify the
proposed system. The digital controller is designed by
using
a
32-bit
fixed-point
microcontroller
(STM32F103VET6) for implementing all algorithms in
the proposed system. The parameters in the real
implementation of the proposed system are the same as
ones in simulation previously seen in Table III. The
hardware prototype set the dc-link voltage reference of
400 V(dc). The switching frequency (fs) of the PWM
signals for both ac input current and ac output current
controls is same as 20 kHz. The dead time of leg switches
is set to 1s. The hardware is designed for 0-600 A(rms)
output with 220V, 50Hz input voltage. The frequency of
ac output voltage range can be either 50 or 60 Hz. The
dual-pack IGBT module is rated 1200V/50A and
specification of four diodes are 1200V/30A.
Referring to Fig 7, the same simulation condition is
experimented and shown in Fig. 14. The integrated
rectifier/boost converter and dual dc-link voltage/PFC
control performance is successfully implemented. The ac
input current is sinusoidal in phase with ac input voltage.
Then, the step responses of dual dc-link voltages from
400 to 350 V(dc) are tested and illustrated in Fig. 15. In
the test, the ac output current is controlled constant at 200
A(rms). Fig. 16 shows the experimental results for
steady-state response of ac output current controlled at
200 A(rms). Similar to simulation result shown in Fig. 8,
the ac output current is synchronously controlled with ac
input voltage. In addition, the step response of ac output
current from 100 to 200 A(rms) is successfully tested and
shown in Fig. 17. The disturbance due to sag voltage of
ac input voltage is also experimented as seen in Fig. 18.
During occurrence of sag voltage, dual dc-link voltages
iS
iout
iout
vS iS
Vc1
vS
Vc2
iS
vS
iref
iS
iout
iout
Fig. 23. Experimental results for step response of ac output current from
0 to 400 A(rms).
VI. CONCLUSIONS
In this paper, the single-phase ac-ac converter with ac
output current controls is proposed and digitally
implemented for the circuit-breaker (CB) testing standard
(IEC 60898). Both simulation and experimental results
show the improved transient step current control
performance over the traditional ac current source based
on the motor driven tap changing of auto-transformer.
The proposed system is simple and low cost with
minimum switches employed. The boost PFC topology
with dual dc-link voltage controls is also incorporated in
the proposed system.
iref
ACKNOWLEDGMENT
The financial support from the royal golden jubilee
Ph.D program, the Thailand research fund is
acknowledged. The student scholarship recipient code is
the 1.E.KT/51/K.1.
iout
iref
REFERENCES
[1]
[2]
[3]
iout
[4]
[5]
iref
[7]
iout
[8]
[9]