Beruflich Dokumente
Kultur Dokumente
QUESTION BANK
DEPARTMENT OF CSE
ADVANCED COMPUTER
ARCHITECTURE-CS2354
2-MARK QUESTIONS AND
ANSWER
PREPARED BY
S.MATHU MOHAN ME.,
AP/CSE
CISC
1. Complex Instruction set computer
2. Complex instruction take multiple
Cycles per operation.
3. Many instruction and address
Modes.
4. Variable format instructions are
used.
5. Instructions are interpreted by the
Microprogram and then executed.
6. CISC machines use single register
Set.
7. Complexity in the microprogram
8. CISC machines are not piplined.
59.Define
1. Signal - The binary information is represented in digital computers by physical
quantities called signals.
3. Gates The manipulation of binary information is done by logic circuits called
gates. Gates are blocks of hardware that produce signals of binary 1 or 0 where
input logic requirements are satisfied.
3. Flip flop The storage elements employed in clocked sequential circuits are called flip
flops. A flip flop is a binary cell capable of storing 1 bit of information.
PART-B
CS2354 -ADVANCED COMPUTER ARCHITECTURE
Unit I
1.What is instruction-level parallelism? Explain in details about the various dependences caused
in ILP?
2.Explain in details about static branch prediction and dynamic branch prediction
3.Explain the techniques to overcome data hazards with dynamic scheduling?
4. Explain in detail the hardware based speculation for a MIPS processor
Unit II
1.Explain in detail how compiler support can be used to increase the amount of parallelism
that can be exploited in a program.
2.Explain the limitations of ILP?
3.Explain Intel IA-64 Architecture in detail with suitable reference to Itanium processor
4.Explain how hardware supports for exposing more parallelism at compile time?
Unit III
1.Explain in detail the symmetric shared memory architectures and explain the cache
coherence problem in detail
2.Explain in detail the distributed shared memory architecture highlighting the directory
based cache coherence protocol. Substantiate your explanation with suitable examples and
state diagrams
3.Define synchronization and explain the different mechanisms employed for synchronization
among processors?
Unit IV
1.Discuss in detail the different levels of RAID
2.How does one reduce cache miss penalty and miss rate? Explain.
3.Discuss Reliability, Availability and Dependability for storage devices in detail
4.What are the ways available to measure the I/O performance? Explain each of them in
detail.
5 . Discuss in detail about type of storage devices
UNIT V
6. Explain in detail about CMP architecture and SMT
architecture?
7. Explain in detail about IBM Cell Processor
8.Discuss about Intel multi-core architecture.
9.Explain in detail about software and hardware multithreading techniques?