Digital Circuit

1. Number Systems
01 . Refer IES 15 E & T Conventional Paper II Q.08, page: 194
02 . Refer IES 15 E & T Conventional Paper II Q.12 ,page: 195
03 . Refer IES 15 E & T Conventional Paper II Q.10, page: 195

The Logic diagram for AC is

2. Logic Gates & Boolean Algebra

AC

A
C

01.
Sol: There is no correct option.
F = ABC + ABC ABC ABC

= AB C C ABC ABC
= AB + ABC ABC

The Logic diagram for AB AC is

= AB AB AB C ABC

A
B

AB AC

A
C

( A A B (A A )(A B)
The Logic diagram for AD is

= AB + C + ABC
= AB + C + A B C

(C+ C 1)

A
D

= 1+ AB + A B = 1
02. Refer IES 15 E & T Conventional Paper II
Q.08, page: 120
03.

AD

The Logic diagram for AD C is

A

Sol:

D
C

Given function is X

= AB A C AD C

The Logic diagram for AB is

A
B
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AD C

The Logic diagram for X

= AB AC AD C

AB
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: 270 :

Postal Coaching Solutions

B
C
D

A
B

A
C

A
D
C

04.
Sol: Using K map
f (A,B,C,D) = m1,2,3,4,7,9,10,12
f A, B, C, D BC D A CD B C D B C D

CD
00
AB
00
01

01
1

11

10

05. Refer IES 15 E & T Conventional Paper II

Q.07, page: 125
06.
Sol: F x y xy yz
Using NAND Gates is shown in fig (a)
x

xy
y

A
C
D
B
C
D
B
C
D

xy

11

yz

10

Fig (a)

Using NOR Gates is shown in fig (b)

Using the K-map, the minimal form of the
given minterms is found.
This function can be implemented using
seven number of 3 input NAND gates.

f B C D A CD B C D B C D
f B C D A CD B C D B CD

( using De-Morgans theorem)

The circuitry for above minimal expression
using NAND gates as follows. Let us
assume that variable are available in
complement form also.
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x y xy

x y x .y

y
x

z
y

z y z .y

Fig. (b)

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: 271 :

Digital Circuits

Using AND and NOT gates is shown in fig

(c)

3. K - Maps

01.
Sol:

y
x

y
y

Given circuit diagram is

B

A
z

Fig (c)

Implementation using OR and NOT gates is

shown in fig (d)
x

A
A

y
x

B
y

Series combination: AND gate

Parallel combination: OR gate

z
Fig (d)

Y A(B C ) AB (A B) C

07.
Sol:

(1)

AB AC AB AC BC

B(A A ) AC AC BC
(2)

xw

(4)

(5)
(3)

y
z

xyz

f w x w x yz
w[1 x ] xyz
f w xyz

02.
Sol:
The circuit diagram gives in the
question is redrawn as
G1 0

G3

G4 f

P=1

Thus from expression for the output f, the

can conclude that gate no.(2) is redundant
and even if the gate is removed from the
circuit the output expression is
f w xyz
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B A BC A B C

G2 1
C

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: 272 :

Output of gate G1 will definitely be 0.

If any one of the input of G2 is 0,
output of G2 is definitely 1.
Output of gate G3 = A
Output of gate G4 f = A A
f = A
03.
Sol: Given k map is
zw
xy
00
01
11
10

00
d
0
1
d

xy
00
01
11
10

4. Combinational Circuits
01.
Sol:

01
1
1
d
1

11
0
d
d
1

A
0
0
0
0
1
1
1
1

10
1
1
d
d

01
1
1
X
0

11
0
d
d
0

10
1
0
0
d

B
0
0
1
1
0
0
1
1

X
0
1
0
1
0
1
0
1

Y
1
0
0
1
1
1
0
0

K map for the above truth table is

A

00
d
0
1
d

LOGIC
GATES

X
A
B

Truth table:

The minimized SOP expression from

the given k map is
Y yw y w x zw xz w ---- (1)
for the expression in equation (1) the
Literal count = 10
zw

Postal Coaching Solutions

BX
00
0 1
1 1

01
0
1

11
1
0

10
0
0

y B X ABX ABX

BX A ABX

y B[ AX] BAX

The minimized POS expression is

y ( x y)( z w )( y z )( x z w ) ----(2)
For the expression in equation (2) the
Literal count = 9

y AXB AX B
y [ AX B]
If different logic gates are used then minimum
number of gates required is 3.
A
X

AX

Y AXB

B
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: 273 :

02.

Refer IES 15 E & T Conventional Paper

II Q.16, page: 143

03.
Sol:
The logic circuit to be designed produces an
output equal to 1 if the input variables have
more 1s in the sequence than the zeroes. For
3 variable input A, B, C the truth table is
A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

Y
0
0
0
1
0
1
1
1

BC
00
0 0
1 0

01
0
1

04. (a)
Sol:
Ex 3 to 2421 code converter
Dec no. Ex-3 Code
E3 E2 E1 E0
0
0 0 1 1
1
0 1 0 0
2
0 1 0 1
3
0 1 1 0
4
0 1 1 1
5
1 0 0 0
6
1 0 0 1
7
1 0 1 0
8
1 0 1 1
9
1 1 0 0

2 4 2 1 code
Y3 Y2 Y1 Y0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

K map for Y3
E 1E 0
00

01

11

10

00

01

11

10

E3 E2

K map for above truth table is

A

Digital Circuits

11
1
1

10
0
1

Y3 E 3

Y = BC+AC+AB

K map for Y2
Realization using basic gates:

E 1E 0
00

01

11

10

00

01

11

10

E3 E2

AB

A
B

Y = AB+ BC+CA

Y2 E 3 E 2 E 2 E1E 0 E 3 E 0 E 3 E1
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: 274 :

4. Map for Y3
E 1E 0
00

01

11

10

00

01

11

10

E3 E2

Y1 E 3E 2 E 3 E1 E 0
E 1E 0
00

01

11

10

00

01

11

10

E3 E2

Postal Coaching Solutions

complementary to each other so from

above table eg: if number is 3 its Ex-3
code is 0110. 9s complement of 3 in
Ex-3 code is 1001 which is
complementary to 0110. Thus Ex-3
code is a self complementary code.
05 . Refer IES 15 E & T Conventional Paper
II Q.07, page: 137
06 . Refer IES 15 E & T Conventional Paper
II Q.20, page: 144
08 . Refer IES 15 E & T Conventional Paper
II Q.03, page: 190
09.
Sol: V0 toggles between 0 and 1.
Output is a square wave with time period 2 micro
seconds.
1s
V0

Y0 E 0

04. (b).
Sol:

The excess 3 code table

Dec
0
1
2
3
4
5
6
7
8
9

BCD Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001

Ex3 Code
0011
0100
0101
0101
0110
1000
1001
1010
1011
1100

A self complementary code is a code in

which the code of a number and code
of 9s complement of that number are
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5. Sequential Circuits
01. Refer IES 15 E & T Conventional Paper II
Q.04, page: 150
02. Refer IES 15 E & T Conventional Paper II
Q.32, page: 166
03. Refer IES 15 E & T Conventional Paper II
Q.27, page: 163
05. Refer IES 15 E & T Conventional Paper II
Q.13, page: 155
07 . Refer IES 15 E & T Conventional Paper
II Q.41, page: 173

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: 275 :

Digital Circuits

(b)

6. Logic Gate Families

A
L
L
H
H

01.
Sol: Refer IES 15 E & T Conventional Paper
II Q.05 page: 128
02. Ans: (i)

(c)

03.
Sol: CMOS NAND gate:
Figure (a) shows the 2 input NAND gate
transistor
schematic.
The
electronic
operation follows the truth table in figure
(b). A logic 0 on any input line turns off an
NMOS driver transistor and open the path
form the output VC to ground. A Logic 0
ensures that a PMOS is turned on.
Therefore, for any logic 0 on the inputs, the
output is at logic 1, or VC = VDD, If both
logic inputs are logic 1 (VA = VB = VDD),
then both NMOS transistor are ON, and
V0 = 0V.

B
L
H
L
H

Q1
off
off
on
on

Q2
on
on
off
off

A
B

Q3
off
on
off
on

Q4
on
off
on
off

C
H
H
H
L

Truth table:
A
0
0
1
1

B
0
1
0
1

C
1
1
1
0

Advantages of CMOS gates:

CMOS gates are having less power
dissipation compare to all other logic family
gates and having high packing density.

VDD
(a)
Load Transistor

Q2

04 . Refer IES 15 E & T Conventional Paper

II Q.08, page: 131

Q4

05 . Refer IES 15 E & T Conventional Paper

II Q.08, page: 127,128
C

Q1

Q3

06 . Refer IES 15 E & T Conventional Paper

II Q.09, page: 131

Driver Transistor

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: 276 :

7. Semiconductor Memories
01.
Sol:
As there are 128 words 7 address lines are
required. For the random access R/W
memory no. of data lines is 8. If the write
enable pin is 1, the data lines behave as
input lines. If the write enable pin is 0, the
random access R/W memory will read data.
8
Chip select
7

Write enable

Postal Coaching Solutions

In this cell, the data bit is stored in a small

capacitor rather than in a latch used for
SRAM cell. Also, in this cell, only one
transistor and a capacitor are required per
bit, compared to six transistors in SRAM.
This allows DRAM to have very high
density in comparison to SRAM. The main
disadvantage in a DRAM cell is that since
the charge is stored in a capacitor, which can
not hold it over an extended period of time.
Therefore, the stored bit can not remain
unless the charge is replenished or refreshed
periodically. This requires additional
circuitry.
Fig (b) shows a DRAM cell along with the
simplified circuitry for read, write, and
refresh operations.
Refresh
enable

8
No. of address lines = 7
No. of data inputs / outputs = 8
Write enable = 1
Chip selected = 1
= 17
02.
(b)
Sol:

Column (bit line)

output enable OE
Data output
Dout
Row (word line)
Data input Din
Write enable

MOSFET Dynamic RAM (DRAM) cell:

The earlier DRAMs were made using
3-transistor cell, which were later replaced
by 1-transistor cell. Fig (a) shows a
1-transistor DRAM cell.
Column (bit line)
Row (word line)

Fig. (a) A 1- transistor DRAM cell

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WE
Fig. (b) A DRAM cell with Read, Write and
Refresh circuitry

Read operation:
For reading or writing operation, the word
lines (Row) is to be selected which switches
ON the transistor. The output enable OE
LOW will enable the output buffer, making
its output same as the bit line which is at the
same logic level as the voltage on the
capacitor. Thus, the output is at logic 1
corresponding to the capacitor charged and

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: 277 :

logic 0 corresponding
capacitor.

to

discharged

Digital Circuits

connected to the bit lines BL and BL . These

bit lines are used to transfer data for both
read and write operations.

Write Operation:
With the row line selected, the write enable
WE LOW allows writing into the cell. If
the Din bit is 1, the capacitor gets charged to
logic 1 through the ON transistor, whereas,
if Din bit is 0, the capacitor gets discharged
through the ON transistor to the logic 0.
when the WE is made HIGH, the charge on
the capacitor remains trapped on the
capacitor (1 or 0).
02. (c)
Sol:
MOSFET static RAM (SRAM) cell:
A CMOS SRAM memory cell is shown in
below fig
WL
VCC

T2

BL

T5
T1

Assume that the content of the memory is Q

= 1. the read cycle is started by precharging
both the bit lines BL and BL to logic 1, then
asserting the word line WL = 1 enables both
the access transistors T5 and T6. The values
stored in Q and Q are now transferred to the
bit lines by leaving BL at its precharged
value and discharging BL through the
transistors T1 and T5 to logic 0. on the BL
side, the transistors T4 and T6 pull the bi
lines to VCC, i.e., logic 1. If the content of
memory is Q = 0, the opposite will happen
and BL would be pulled towards 1 and BL
towards 0.
Write operation:

T4

Read operation:

T6

BL

T3

For writing into the cell, the bit to be stored

is applied at BL and its inverse at BL .
When the word line WL is asserted , the
value to be stored is latched. The new bit
replaces the earlier bit stored.

Fig. A six transistor CMOS SRAM cell

Each bit in an SRAM is stored on four

transistors, two NMOS and two PMOS, that
form two cross-coupled inverters. Two
additional transistors T5 and T6 serve to
control the access to a storage cell for read
and write operations. Access to the cell is
enabled by the word line (WL) which
controls the two transistors T5 and T6 which,
in turn control whether the cell should be
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8. A/D & D/A Converters

01.
Sol: we know that (form superposition theorem)
V01 = - VRef (b0 + b1 21 + b2 22 +b3 23 +
4
b4 2 + b5 25 + b6 26 +b7 27)
V02 = - VRef (b8 + b9 21 + b10 22 + b11 23
+ b12 24 + b13 25 + b14 26 + b15 27)
The correct value corresponding to an 16
bit DAC is,
V0 = Vref [ b0 + b1 21 + - - - -+ b15
15
2 ]
from virtual ground concept
0 V01 0 V02 0 V0

0
R
1k
1k
V
V
V0
01 02
1
R
1

02.
Sol: The counter in which conversion time is
almost doubled for every bit added to the
device is counter type A/D converter
because in an N bit counter type A/D
converter the no. of pulses required for
conversion is 2N.
TC1 2 N pulses

TC 2 2N+1
TC 2 2TC1

03 (a), (b). Refer IES 15 E & T Conventional

Paper II Q.09, page: 185
04.
Sol:

1k

V0

V0
V01

V02

1
7
V0 Vref (b 0 b1 2 .... b 7 2 ) Vref

1
1
R

[b 8 ...... b15 215 ]

V0 = Vref [b0 + b1 21 + +b15 215]

Comparing, we have
R = 0.5 K

R2
R1
R0

the

V0

5
0 M 5
5
100
200
400
800
E
1
5
5 5 6.875V R
4
8
F
E
V0 = 6.875V T
Ga

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V0

Fig
ure
:
Cr
oss
sec
R f b 3 R f b 2 R f b1 tio
R b

n f 0 Vref
R2
R1
R0
R3
&
eq given in
Comparing fig (i) with the figure
question b3 b2 b1 b0 = 1011, uiv
ale
Rf = 100k; R3 = 100k; R2nt= 200k;
R1 = 400k; R0 = 800k; cir
cui
Vref = 5V
t
of
a
100
100
100
100

b0

Rf
R3

b3
b2
b1

1k
V=0
R

Postal Coaching Solutions

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