03 - Analog All Chapters PDF

1
Analog Electronic Circuits

Input and output waves:
2. Diode Circuits
Vin
01.
Sol:
7V
The below circuit diagram behaves as a two
level clipper with clipping levels at 3V &

5V.
7V
V0
7V
D1
Vin
3V
5V
5V
D2
V0
3V
7V
Here the diodes D1 & D2 are ideal.
Let us assume, the input Vin = 7 sint is given

as input.
02.
D1 is Forward biased when
Sol: Given circuit diagram is
Vin > 5V V0 = 5V
1K
D2 is Forward biased when

Vin < 3V V0 = 3V
D1
Vin
1V
D2
2V
V0
1k
Both D1 & D2 are Reverse biased when

3 < Vin <5 V0 = Vin
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: 76 :
The above circuit can be redrawn as below
Postal Coaching Solutions
Transfer Characteristics:
V0
1k
1V
Vin
D1
1k
1V
D2
4V
Vin
2V
V0
2V
2V
Note:
Here the diodes D1 & D2 are assumed as ideal
diodes.
Thevenin
equivalent
0.5K
+
VTh =
D1
Vin
2
D2
2V
1V
V0
03.
Sol: Case (1):
Vin pos, D1 FB, D2 RB
+
+
Vo
Vin
Condition
2V < VTh < 1V
V
2V < in 1V
2
4V < Vin < 2V
VTh > 1V
Vin/2 > 1V
Vin > 2V
VTh < 2V
Vin/2 < 2V
Vin < 4V
State of
diodes
2k
D
Output
voltage
D1 is RB and
V
V0 = in
D2 is RB
2
2k
2k
VBD = Vo =
Vin
2
Case (2):
D1 is FB and
D2 is RB
V0 = 1V
Vin Negative D1 RB, D2 FB

A
D1 is RB and V0 = 2V
D2 is FB
Vin
D
D
2k
2k
V o=
Vin
2
2k
C
: 77 :
Let Vin = 10 sint
RC >> tp
V
Vi
10V
Vin
0
tp
VC
10V
0
V
5V
Vo
0
Vi Vc=VR
0
-V
04.
Sol:
+ VC
Vi is a square wave
+
Vo=VR
Vi
Vi
V/2
0
-V/2
Vi is a step input
V
Vi
-t/RC
V(1-e
)=VC
Vi Vc=VR
-t/RC
Ve
T
VC
VC
0
V
0
V
Vi is a pulse
Vi
RC << tp
V
0
V
tp
V/2
Vi Vc=Vo
-V
=VR
-V/2
t
T/2
-V
V V
100%
V
2
t
Vi Vc=VR
% tilt =
0
V
Vo = Ve RC
T
T
At t =
Vo = V Ve 2 RC ------ (1)
2
: 78 :
But, V ( V) V V V V --- (2)

T
From (2) V Ve 2 RC V
05.
Sol:
Vi
V[1 e 2 RC ] V
1 e
V
From (2)
T
2 RC
1 e
x
2
Risetime (tr) of a step response is defined as

the time taken for the exponentially rising
output waveform to rise from 10 percent to
90 percent of its final value V
x
2
Vi
x
4
V V
100
V
2
T V
T V
1 4RC 2 1 4RC 2
=
100
V
2
tilt =
T
100%
2RC
0
V
0.9V
VC
tilt =
0.1V
T
2 RC
x
4
RC << tp
0.9V
1
1 e
0
V
VC
1 e
t
RC >> tp
tp
VC
T
2 RC
V V
0.1V
0
t1 tr
0.1 V = V (1 e
0.9 V = V (1 e
t2
t
1
RC
t2
RC
tr = t2t1
) t1 = 0.1 RC
) t2 = 2.3 RC
tr = t2 t1 = 2.2 RC
3db
BW = f2 f1 f2 and f2 =
(or) RC =
1
2RC
1
1
2f 2 2f 3db
: 79 :
tr = 2.2RC =
tr =
Apply KVL
2 .2
0.35
2f3db f3db
Vm + Vm VC2 = 0
0.35
f3db
VC2 = 2Vm
When f3db is 3 db cutoff frequency (or)

3 db bandwidth
tr is the risetime
During the next negative cycle, diode D3 is

FB. After capacitor C3 is fully charged the
diode D3 gets RB
Vm
06.
C1
=
sint
D2
D3
D1
+
Vx
D4
D5
C4
VC +
Vm ~
VC3 = 2Vm
During the next positive half cycle diode D4 is
FB. After capacitor C4 is fully charged the
diode D4 gets RB
Vm
Apply KVL
Vm + Vm + VC3 2Vm = 0
2Vm
Vm + VC1 = 0
Vm ~
VC1 = Vm
2Vm
Apply KVL
During the first negative cycle D1 is FB & the

capacitor C1 charges to Vm Volts. After the
capacitor is fully charged D1 gets RB
C2
VC3
C3
Vm
Vin
During positive cycle Diode D2 is FB &

D1RB. After capacitor C2 is fully charged the
diode D2 gets RB.
VC1 +
2Vm + VC4 +
Apply KVL
Vm ~
+ Vm + Vm +2Vm VC4 2Vm = 0

VC2 +
Vc4 = 2Vm
: 80 :
Now the original circuit can be redrawn by

considering the voltages developed across
capacitor
Vm +
During the negative cycle D1 is RB & D2 is

FB and the capacitor C2 charges to 2Vm volts.
VC1
Apply KVL
2Vm +
+
Vx
2Vm +
D5
Vm ~
Vc2 = 2Vm
Vm Vm + VC2 = 0
+
Vin
VC2
The voltage across diode D1 is +
VD1 = Vin Vm
2Vm +
The voltage across diode D2 is VD2 = Vin + Vm

Apply KVL as shown in the fig
Vin + Vm + 2Vm Vx 2Vm 2Vm = 0
Vx = Vin Vm
08.
Procedure 1:
Sol: (0.5, 0 )
07.
x1

VC1
(0.7, 1m)
y1
x2
y2
y y1 = m (x x1)
Vm
+
~
VD1
I=
VD2
V = 0.5 + 200I
+
+
VC2
1m 0
( V 0.05)
0 .7 0 .5
200
I
0.5V
During the positive cycle D1 is FB &

capacitor C1 charges to Vm volts. After the
capacitor is fully charged D1 gets RB
Rth
+
VC1
Apply KVL
Vm VC1 = 0
VC1 = Vm
3K
I
0.5V
5V
Vm ~
I=
5 0 .5
3.75mA
1K 200
: 81 :
Procedure 2:
3. Transistor Biasing and

Stabiliztion
1k
Treat the device as a load
varying from 0 to
5V
01.
I
5m
5V
DC offset point (or) Q point
3.7m
1K
1m
0.5 1V 1.25V
(0.5 m )
(5, 0)
x2 y2
x1 y1
y y1 = m ( x = x1 )
I=
5m
( v 5)
05
-1000I + 5 = 200I + 0.5
4 .5
3.75mA
1200
R2
10K
5V
VE = VB + 0.7
V = 200 I + 0.5 - ( 2) (from the device equation )
1200 I = 4.5
VB
It is given in the problem that the transistor is

in saturation, take RE = 10K instead 10
V = -1000 I + 5 (1) ( from the network)
I=
+ VB + 0.7
0.2V
V + 0.7 0.2
10K
VEC = 0.2
VC = VE VEC
= VB + 0.7 0.2
= VB + 0.5
In a transistor IE = IB + IC
5 VB 0.7 VB VB 0.5 (5)
=
10K
10K
1K
4.3 VB
V
V 5 .5
B B
1K
10K
10K
: 82 :
4.3 VB =
4.3 VB =
VB VB 5.5
10
10
02.
VB VB 5.5
10
10
5V
IE
4.3 VB = 0.2VB + 0.55
5K
1.2VB = 4.3 0.55

VB =
3.75
1 .2
+ VE = 1V
VB = 3.125V
IB
VB
20K
R2
IC
Base voltage, VB = 3.125V

Emitter voltage, VE = VB + 0.7
5K
5V
The emitter current, IE =
= 3.125 + 0.7 = 3.825V

=
Collector voltage, VC = VB + 0.5
= 3.125 + 0.5 = 3.625V
V
Base current, IB = B
10K
5 3.825
1k
= 1.175mA
Collector current, IC =
VC 5
10K
3.625 5
= 0.8625mA
10K
Base voltage, VB = VE 0.7V

= 1 0.7 = 0.3V
0 .3
= 15A
20K
It is known that
= 0.3125mA
Emitter current, IE =
5 1
5K
4
= 0.8mA
5K
The base current, IB =
3.125
10K
VC
IE = IB + IC
0.8mA = 15A + IC
IC = 0.785mA
Collector voltage, VC = 5 + 5K IC
= 5 + 5K 0.785mA
= 5 + 3.925
= 1.075
: 83 :
Common emitter gain

=
=
IC =
I C 0.785m
=
= 52.33
IB
15
30
IE
2.32mA 2.245mA
1
31
VE = 9 IERE
= 0.98
1
= 9 2.32m 2.7K
VE = 2.72V
a) Given circuit diagram is

VB = VE 0.7 = 2.72 0.7 = 2.02V
9V
VC = 9 IC RC
IE
= 9 + 2.245m 2.7K
2.7K
0.7 +
VB
IB
IB
RB = 27K
IC
VE
= 2.9V
VC
VEC = VE VC
RC = 2.7K
VEC = 2.72 (2.9)
9V
VEC = 5.65V
Apply KVL along the loop shown
VEC > 0.2V
9 IE RE 0.7 IBRB = 0
The transistor is in Active region
9 IE RE 0.7
IE
RB 0
1
b)
9V
IE
I E R E B 9 0 .7
1
IE =
9 0 .7
27 K
2.7 K 31
8 .3
27 K
2.7 K 31
2.7K
0.7 +
VB
IB
VE
IB
RB = 27K
VC
IC
RC = 2.7K
9V
Apply KVL along the loop shown

9 IERE VBE IBRB = 0
IE = 2.32mA
: 84 :
IERE + IBRB = 9 VBE

IERE +
IE
R B 9 VBE
1
03.
Sol: a) Given = & VBE 0.7
The given circuit diagram is
IE
IE 2.7K +
27 K 9 0.7
30 1
IE =
5V
IC
8 .3
= 2.324mA
27 K
2 .7 K
31
1.6K
IB
VE = 9 IE RE
V2
22K
(1)
= 9 2.324m 2.7K = 2.72V
+
0.7V
R2
2mA
IE
IC =
IE
1
IC =
V1
5V
30
2.324mA =2.249mA
31
From the circuit diagram

IE = 2mA
Transistor to be in Active region

VEC > VEC (sat)
It is given that =
VEC > 0.3
IC IE = 2mA and also IB = 0
VE VC > 0.3
2.72 (2.249m R 9) > 0.3
2.72 2.249m R + 9 > 0.3
2.249m R < 9 + 2.72 0.3
Apply KVL at loop (1)

IB (22K) 0.7 V1 = 0
(0) (22K) 0.7 V1 = 0
11.42
R<
2.249m
V1 = 0.7V
R< 5.07K
And V2 = 5 IC RC
= 5 2m 1.6K = 1.8V
: 85 :
It is given in the problem that =
b) Given circuit diagram is

5V
IC = IE and IB = 0
IC
Apply KVL at the input loop (1)
1.6K
IB
V3
+
0.7V
(1)
R2
IB(22K) 0.7 IE (2.2K) + 5 = 0

(D) (22K) 0.7 IE (2.2K) + 5 = 0
V4
2.2K
I4
(2)
IE =
5V
5 0 .7
2 .2 K
Apply KVL at input loop
IE = 1.9545mA
0.7 I4 .2.2K + 5 = 0
IC = 1.9545mA & IB = 0
I4 =
5 0 .7
= 1.9545mA
2 .2 k
V6 = 0V
V7 = 5 1.6K (1.9545m)
Apply KVL at loop (2)
= 1.8728V
V4 I4(2.2K) = 5
V4 = (1.9545m) (2.2K) 5
V5 = IE (2.2K) 5
V4 = 4.3 5
V5 = (1.954m) (2.2K) 5 = 0.7V
V4 = 0.7V
d)
Given =
Given circuit diagram is

5V
V3 = 5 IC (1.6K)
= 5 (1.9545m) (1.6K) = 1.8728V
1.2V
(C) Given circuit diagram is

5V
IC
56K
+
0.7V
3.3K
V8
V9
22K
V7
5.1K
(2)
IC
5V
V6 +
0.7V
(1)
R2
IE
IE
IB
1.6K
IB
(1)
V5
2.2K
It is given that =
IC IE and IB 0
5V
: 86 :
Apply KVL in the loop shown

1.2 + IB (56k) + 0.7 + IE (3.3k) 5 = 0
The above circuit diagram can be redrawn as

shown below
5V
1.2 + 0 (56k) + 0.7 + IE (3.3k) 5 = 0

IE =
(1)
5 0 .7 1 .2
= 0.939 mA
3.3K
IE
3.3K
56.639K
+
V8 = 5 3.3K (0.939m)
0.7
+
+
IB
V11
V12
3.112V
= 1.9013V
R2
5.1K
Apply KVL along loop (2)
(2)
IC
V9 IC (5.1K) + 5 = 0
It is given in the problem that =
V9 = IC (5.1K) 5
IB = 0 & IC = IE
= 0.939m 5.1k 5 = 0.21V
Apply KVL in loop (1) as shown in fig
e) Given circuit diagram is
5 3.3K IE 0.7 IB (56.639K) 3.112 = 0
5V
+5V
5 3.3K IE 0.7 (0) (56.639K) 3.112 = 0
IE
91K
3.3K
V10
IB
150K
R2
V11
IE =
5 0.7 3.112
0.36mA
3.3k
IC = IE = 0.36mA
V12
V11 = 5 IE (3.3k)
5.1K
= 5 (0.36m) (3.3K)
Thevenin
Equivalent
150k 5
VTh =
= 3.112V
91k 150k
V11 = 3.812V
Apply KVL along loop (2)
V12 IC (5.1K) = 0
V12 = 5.1K 0.36 mA
RTh = 91K 150K

= 56.639 K
: 87 :
Apply KVL along the loop shown in the

figure
04.
5 + IB (10K) + 0.7 + IE (1K) = 0

5V
We know that IE = (1+ ) IB
IE
IE = 101 IB
10K
VE
Vin
5 +
VB
1K
IE =
5V
For Vi = 0V:
IE
(10K ) + 0.7 + IE (1K) = 0
101
5 0 .7
= 3.913mA
10K
1K
101
VE = IE (1K) = 3.913V
If the input voltage = 0V, then the two

transistors are in cut off region.
VB = 0.7 + VE
= 0.7 3.913
VB
Vin
VB = 4.613V
05.
VB = Vin = 0V

VCC = 12V
For Vi = 3V:
If input voltage V1 = 3V, the transistor Q1 is
ON & Q2 is OFF.
R1= 10 K
3.9K
VC
Q1
The equivalent circuit is shown below

R1= 2.2 K
IE
10K
VE
Vin = 5V
IC
+
0.7
R2 1K
+
0.7
Q2
V0
R2
4.7K
VB
1K
IB
5V
Thevenin
Equivalent
It is also given that is very large and IB = 0

& VBE = 0.7V
: 88 :
The diagram also can be redrawn as shown

below
VCC = 12V
06.
+VCC
Sol: Fixed bias
Rc
Rb
IC
IC
3.9K
RTH = 1.8K
VC
Q1
+
0.7
R2 1K
(1)
+
0.7
Q2
V0
R2
4.7K
Stability factor (s) =
IC
ICBO
IC = IB +(+1)ICBO
Thevenin
Equivalent
Differential with respective to IC
2.2K 12
VTH =
(10K 2.2K )
2.2 12
=
= 2.164V
12.2
1=
I B
I
( 1) CBO
IC
IC
IC
ICBO
RTH = 1.8K
Apply KVL in the loop (1)
2.164 IB (1.8K) 0.7 VE1 = 0
2.164 (0) (1.8K) 0.7 VE1 = 0
VE1= 1.464V
IE1 =
VE1 1.464
1.464mA
1K
1K
1
I
1 B
IC
In fixed bias IB =
VCC VBE
Rb
I B
0
IC
S=
1
1 worst case
1 ( 0 )
It is given that IB = 0
Collector to base bias
IE = IC = 1.464mA
KVL at input loop
VC1 = VCC IC (3.9K)
+VCC
IC+I
RC
RB
= 12 1.464m (3.9K)
IC
= 6.29V
V0 = VC1 0.7
= 6.29 0.7
IB
+
VBE
V0 = 5.59V
: 89 :
VCC = (IC+IB)RC + IBRB + VBE
KVL
+VCC
IB[RC+RB] = VCC VBE ICRC

IB =
R1
RC
R2
RE
RC
VCC VBE
IC
RC RB
RC RB
I B
RC
IC R C R B
S=
1
RC
1
RC RB
Vth = IBRth + VBE + IERE

Vth = IBRth + VBE + (IC+IB)RE
IB[Rth+RE] = Vth VBE ICRE
RC
Ideally S = 1 therefore
1
RC RB
I B
RE
IC R th R E
RC >> RB
+VCC
Bias circuit with emitter resistor (RE):
RC
KVL
Rth=R1||R2
IB
VCC = IBRB + VBE + (IC+IB)RE

Vth=
IB[RB+RE] = VCC VBE ICRE
IB =
VCC R 2
R1 R 2
VCC VBE R E
IC
R B R E R B R E
+VCC
I B
RE
IC R B R E
Rc
RB
1
S
RE
1
RB RE
Self bias
S =
+
VBE
RE
IE
1
RE
1
R
R
E
th
If S 1 then RE >> Rth
IB
+
VBE
RE >>
IE = IC+IB
RE
07.
: 90 :
As is very large IE1 = IC1 = 1mA
Sol: KVL
VC1 = 10 4K 1mA
V = (IC+IB)RE + VEB + IBRB
= 10 4 = 6V
IB[RE+RB] = VVEB ICRE
VE2 = VC1 + 0.7

IB =
RE
V VEB
IC
RE RB
RE RB
= 6 + 0.7 = 6.7 V
IE2 =
I B
RE
IC R B R E
10 6.7
1mA
3.3K
VC2 = IC2 5K
= 5K 1 = 5V
1
1
RE
I
1 B 1
RE RB
IC
VE3 = VC2 0.7

= 5 0.7 = 4.3
08.
IE3 =

10 V
4 .3
1mA
4.3K
IE3 = IC3 = 1mA

3.3K
7K
4K
4K
Q2
VB1
Q1
1K
Q4
Q3
5K
3K
2.3K
= 10 4K 1m = 6V
1K
Q5
VE4 = VC3 0.7
Q6
10K
4.3K
VC3 = 10 4KIC3
1K
10K
V0
= 6 0.7 = 5.3
10K
IE4 =
Let us assume is very large and VBE = 0.7V
10V 3K
Then VB1 =
7 K 3K
VB1 = 3V
IE1 =
IE4 = IC4 = 0.5mA

VE5 = VE4 0.7
= 5.3 0.7 = 4.6V
3 0 .7
1mA
2.3K
5 .3
0.53mA
10K
IE5 = IC5 = 0.46mA
: 91 :
VE6 = VE5 0.7
I2
h 21
------ (5)
I1 1 h 22 R L
(AI) =
= 4.6 0.7 = 3.9
eq(4)
V
I
h 21R L
---- (6)
2 2 RL
1 h 22 R L
I1
I1
I1
VE6 = V0 = 3.9V
IE6 =
3 .9
0.39mA
10K
Defining input impedance [Zin] =
09.
Sol: Refer solution of Question number 08
h21RL
eq(2)
V
1 h11 h12
[from 6]
I1
I1
1 h22RL
4. Small Signal Amplifiers
Zin h11
01.
Sol:
+
VS
IS RS I1
+
V1
I2
[h]
+
V2
h12 h 21
1
h 22
RL
IL
RL
+
Vo
1 h 22 R L
eq(2)
V
1 h11
h12
V2
V2
h 21R L
V2
h 21R L
V1 h11 R L [h11h 22 h12 h 21 ]
Zin
VS = I1RS + V1
----- (1)
V1 = h11I1 + h12V2
----- (2)
I2 = h21I1 + h22V2
----- (3)
V2 = ILRL = I2RL
----- (4)
Overall voltage gain

(AV) =
Vo Vo V1 V2 V1
VS V1 VS V1 VS
Output impedance (Zo) =

Substitute (4) in (3)
I2 = h21I1 + h22[I2RL]
I2[1+h22RL] = h21I1
I2
h 21
I1 1 h 22 R L
RS
V2
I2
I2
[h]
=
VS 0
1V
Ix V
Ix
+
V2
Zo=
Defining current gain

V1
I1
+
1V
1V
Ix
(1) VS = I1RS + V1 0 = I1RS + V1
: 92 :
Substitute in (2) V1 = I1RS
V1
I1 V
h11 =
I1RS = h11I1 + h12(1)

I1 =
h12
h11 R S
=
0
Vbe (AC)
I b (AC) Vce 0
Vce ( AC ) cons tant
x
y
h12
(3) Ix = h21
h 22 (1)
h11 R S
Ib
1
1
Zo =
I x h h12 h 21
22
h11 R S
x
0
V1 = h11I1 + h12V2
h12=
Vbe
V1
V2
=
I1 0
I2 = h21I1 + h22V2
V
h11= 1
I1 V
h12=
h21=
h22=
V1
V2
I2
I1
I2
V2
Short circuit input

impedance
I1 0
Open circuit reverse

voltage ratio
V2 0
Short circuit forward

curent gain
I1 0
Open circuit output

admittance
+
V1=Vbe
Vce1 = y1
x1
h21=
I2
I1
Vce2 = y2
Ib
=
V2 0
V2=Vce
b ( AC) is cons tant
x 2 x1
y 2 y1
I2 = Ic
I1 = Ib
Vbe (AC)
Vce (AC) I
Vbe
x2
Ic (AC)
I b (AC) V
ce ( AC ) is constant
y 2 y1
x 2 x1
y2
Ib2 = x2
y1
Ib1 = x1
Ic
0
Vce
: 93 :
h22 =
I2
V2
Ic (AC)
Vce (AC) I
=
I1 0

hie
Ib
b
( AC ) is cons tant
1k
Vbe
y
x
Ic
hreVce
hfeIb
1
hoe
Vc
e
[Complete [h] model]
Operating point
x
Ic
0
Note: Neglecting the effect of hre and
1
h oe
the simplified model can be drawn
Vce
B
1k
C
Ib
hie
hfeIb
h11
h12
h21
CE
(1k) hie
CC
(1k)hic
(410-6) hrb
(10-4) hre
(1)hrc
(-0.99) hfb
(100)hfe
(-101) hfc
(810-7) hob
(12s)hoe
(12s)hoc
CB
(30)
hib
[Simplified h-model]
02.
Sol: hib = h11, hrb = h12, hfb = h21, hob = h22,
RS = 0, RL = 20k
h22
(1) Current gain (AI) =
I2 = Ic
I1 = Ib
+
V1=Vbe
h11 = hie
V2=Vce
h12 = hre
h21 = hfe
h 21
1 h 22 R L
0.99
1 (8 10 7 )(20 103 )
= 0.974
h22 = hoe
V1 = h11I1 + h12V2 Vbe = hieIb + hreVce

I2 = h21I1 + h22V2 Ic = hfeIb + hoeVce
(2) Voltage gain

(AV) =
h 21R L
h11R L [h11h 22 h12 h 21 ]
= 647.9
: 94 :
(3) Input impedance

(Zin) = h11
03.
h12 h 21
= 30.08
1
h 22
RL
Sol: Current gain (AI) =
= 97.7
(4) Output impedance

Voltage gain (AV):
1
(Zo) =
=1.07M
h12 h 21
h 22
h11 R S
RS
(AV) =
IL
+
VS
+
V2=Vcb
h 21
h fe
1 h 22 R L 1 h oe R L
h 21R L
= 199.2
h11 R L [h11h 22 h12 h 21 ]
Input impedance (Zin) = h11
+
RL Vo
h12 h 21
1
h 22
RL
= 980.5
I2
RS I1 hib
+
1k
hrbVcb
VS
Output impedance (Zo) =

IL
hfbI1
1
hob
1
h h
h 22 12 21
h11 R S
RL
= 500k
Summary of CB configuration
Ic
(1) Current gain of less than 1

(2) High voltage gain
(3) Power gain approximately equal to
voltage gain
+
VS
+
Vbe
RS Ib
Vce
RL Vo h12 = hre
h21 = hfe
h22 = hoe
(4) No phase shift for current or voltage
Ic
RS Ib hie
(5) Low input impedance [current

controlled amplifier ]
(6) High output impedance [current
source]
h11 = hie
+
VS
1k
hreVce
IL
hfeIb
1
hoe
RL
(7) CB amplifier is a CCCS, as the current

gain 1 it is called a current buffer.
: 95 :
Note:
All the voltages and currents are AC parameters.

Summary :
1
= 9.9
h fc h rc
h oc
h ic R S
Summary :
(1) Large current gain
(1) High current gain

(2) Voltage gain of approximate unity
(2) large voltage gain

(3) Very high power gain Ap = AV.AI
(3) Power gain

current gain
approximate
equal
to
(4) No current or voltage phase shift

(4) Currents and voltage phase shifts by
180o
(5) large
input
impedance
controlled amplifier]
(5) Moderate input impedance
(6) Low output impedance [voltage source]
(6) Moderate output impedance

04.
Sol AI =
h 21
h fe
98.6
1 h 22 R L 1 h oc R L
AV =
h 21R L
h11 R L [h11h 22 h12 h 21 ]
h f cR L
h ic R L [h ic h oc h fc h rc ]
= 0.995
Note: Common collector amplifier is a VCVS

(or) voltage amplifier. As the voltage gain
is close to unity, it is used as voltage
buffer.
05.
Sol: AC equivalent
+
Vin
Zin = h11 h12 h 21

1
h 22
RL
Zo =
1
h h
h 22 12 21
h11 R S
RB
+
Vo
RE
= hic h rc h fc = 8.41M
1
h oc
RL
[voltage
Iin
Vin
Ib1
hie
RB
hfeIb1
(1+hfe)Ib1 Ib2
hfeIb2
hie
Zins
Zin
(1+hfe)Ib2
RE
+
Vo
: 96 :
Vo = (1+hfe)Ib2RE = (1+hfe)2Ib1RE ------ (1)
Ib2 hie
Vin = Ib1hie + (1+hfe)Ib1hie + (1+hfe)2Ib1RE
Iin
---- (2)
Vin
Voltage gain
Ib1 1k
hie
RL
hfeIb2
hfeIb1
IL
Vo
V
(AV) = o
Vin
(1 h fe ) 2 R E
=
h ie (1 h fe )h ie (1 h fe ) 2 R E
IL = Ib1 + Ib2 + hfeIbl + hfeIb2

= (1+hfe)(Ib1+Ib2) ----- (1)
Vin
Zin
Ib1
h ie (1 h fe )h ie (1 h fe )R E (from 2)
Zins = RB||Zin
R B || h ie (1 h fe )h ie (1 h fe ) 2 R E
Current gain (AI)
Voltage gain (AV) =
06.
AV =
+
Vin
RL
hie
+
Vo
Vo
Vin
IL R L
h
Iin ie ILR L
2
hie
h ie
(1 h fe )R L
2
Zin=
hfeIb
(1 h fe )R L
h
Vin = Iin ie I L R L
2
Ib
Ib
IL
IL
1 h fe
Iin I b1 I b 2
IL
R L
I
= in
hie IL
R L
2 Iin
Sol: Ac equivalent
hfeIb
Vin h ie
=
+(1+hfe)RL
Iin
2
: 97 :
Step 1: AC equivalent
Zo
h
1kie
Ib1
1V
Ix
3k
Ib2
hie
hfeIb2
hfeIb1
1V
B
1k
Z1
+
Vin
KCL
+
V1
V0=V2
C
Z2
E
+
V2
Ib1 + Ib2 + hfeIb1 + hfeIb2 + Ix = 0

Replace transistor with equivalent model
Ix = (1+hfe) (Ib1+Ib2) ------ (1)
0 1
But Ib1 =
Ib 2
h ie
+
Vin
1k V B
1
+
hie 1k
Z 1 V1
2
I x (1 h fe )
h ie
Zo =
C IC
hfeIb
+
3k
z2 v2
Vo
z1
1
h ie
I x 2(1 h fe )
V0 100I b
1 1
R 1 R 2
07.
Sol:
VCC
3k
10k
10k
10k
, z2
1
1 A
1
A
VO
1
1
100I b
1 1
3k z
2
Vi = Ib (1k)
+
Vin
1k
V0
100
1
A
Vi
1k 1 A 1
3k 10k A
: 98 :
1
A 1
A 1k
100
3k 10k A
10kA 3kA 3k
10A
1
3k 10kA
08.
Sol: From the fig Rs = 10k
voltage gain from the signal source to
base
Q1 & Q2 is
10A 3A 3
1
3000
Vid
R id
40.4
0 .8
Vi R id R s 40.4 10
13A 3 = 3000
The voltage gain from the bases to the

output is
A = 230.54
Vo Total resis tan ce in collector
Vid
total resis tan ce in emitter
z1
10k
43.56
1 A
z2
10k
10.043k
1
1
A
2R C
2re R E
2 10
50
250 50 10 3
the overall differential voltage gain is

Ad
KCL:
V1 Vin
V1
V
1 0
1k
43.56 1k
Vin
1
2
1k
V1
1k
1k 43.56
Common mode gain

RC
R C
where R EE 200k
2R EE R C
Where RC = 0.02 RC in worst case

A cm
V0 V0 V1
.
Vin V1 Vin
A.
Vo
50 0.8 40
Vi
A cm
Vin
0.0397
V1
Av
Vo Vo Vid
Vi Vid Vi
10
0 .2
2 200
= 5 104
Worst case CMRR
V1
Vin
CMRR 20 log
= (230.52) (0.0397)
= 9.2
20 log
Ad
A cm
40
5 10 4
: 99 :
1
Vin I b h ie 1 h fe R E ||
SC E
CMRR = 98.06 dB
(i) input differential resistance
(Rid) = 40.4k
(ii) overall differential voltage gain
(Ad) = 40
(iii) the worst case CMRR = 98.06 dB
RE
I b h ie 1 h fe
(2)
1 SC E R E
AV
09.
Sol:
Effect of bypass capacitor on the low
frequency response
1 SC R
h fe R C
E E
SC
R
h ie 1 h fe R E
E E h ie
h ie 1 h fe R E
+VCC
RC
+
_
~
RE
hfe Ib
~
E
1
SC E
RE
0
+
RC V0
_
S=
S=0
Gain
C
Ib
hie
h fe R C
h ie
CE
Vin
_
1 S 1
K
1 S 2
V0
Vin
V0
h fe R C 1 SC E R E
Vin
h ie 1 h fe R E SC E R E h ie
1
1
1 R E C E
1 h ie 1 h fe R E
2
C E R E h ie
2 > 1
V0 = (-hfeIb)RC (1)
: 100 :
10.
Sol:
3K
Vin ~
_
1K
+
V
_
gmV
100K
E
Rth
IC
I b Vce 0
emitter]
h fe
Ib
+
Vin ~
_
100K
1F
hie
3K
hfe Ib
1K
+ V
fc
11.
Sol:
unity gain frequency (fT)
V
V SC V SC
r
V SC C (1)
r
IC = [gm - SC] V gmV (2)

C
[neglecting the value of C]
IC
Ib
B
E
VCe=0
V SC I C g m V
gmV
V
_
E
Ib
hfe in terms of 3db band width [f3db] and
IC C
1
SC
1
1
= 39.788Hz
2 24K 1
Calculation of short circuit current gain or
1
SC
Ib
1
1
1

R th C 11K 3K
[Short circuit collector to
g m V
1
V SC C
r
g m r
K
LPF
1 Sr C C 1 S
: 101 :
Defining 3db Band width or 3db cut off

frequency
1
1
f 3db
2 2r C C
fT
gm
(4)
2C C
Gain = K = gmr
From (3) and (4) unity gain frequency is
Gain BW product g m r
1
2r C C
gm
(3)
2C C
gain BW product.
12.
Sol: Refer theory material page no. 134
14.
gmr
3dB
Vcc
Vcc
IC2
I C1
200
Gain
1
f3dB
fT
Frequency
Defining unity gain frequency (fT) as the
200
1 mA
VEE
From the figure I = 1 mA

The collector current IC1 IC 2 = 0.5 mA
frequency at which the gain falls down to

one.
IC
1
Ib
g m r
1 r C C
g m r
1
r C C
gm
1
2f T C C
It is given that = 100;

Thermal voltage vt = 25 mV
IC
g m DC
vt
0.5m 1
gm
25m 50
100
5000 5 K
r1 r 2
1
gm
50
The AC picture of the given circuit diagram
is shown in the below figure.
: 102 :
AC picture:
I B1
Vin
r2
+_
16.
Sol: Given data is
The input resistance of amplifier = 1k
(A)
5 k
100
The output resistance of amplifier = 200
I B1 I B2
r2
5 k
Open circuit voltage gain = 60
100 I B
2
200
200
Load resistance RL = 2.2 k
I B1
The three similar stages of the above

specifications are cascaded. The equivalent
IB
representation is shown below
Rin
Vi
From the figure
State
State
State
(1)
(2)
(3)
= 200
AVR=0 60
= 200
AVR=0 60
= 200
AVR=0 60
KCL at node (A)

100 I B1 I B 2 100 I B 2 I B1 0
Ri = 1K
101 I B1 101 I B 2 0
The equivalent circuit is shown below.
Ri = 1K
Ri = 1K
I B2 I B1
200
Apply KVL through the loop as shown in

fig.
VS
+
_
VS
__
1 k
60VS
VS
__
1 k
Vin 5K I B1 400101I B1 5K I B 2 0
Vin 5K I B1 400101I B1 5K I B1 0
Vin 5K 5K 400 101I B1 0
Vin
50.4 K
I B1
Overall voltage gain =

Vx
200
200
+
V0
60VS
Vx
_
1 k
60VS
+
2.2k V0
V0 V0 Vy Vx
VS Vy Vx Vs
60Vs 1K
200 1K
Vy
Vx
50
Vs
Vx
Rin = 50.4 K
V0
15.
60Vy 2.2K
200 2.2K
V0
55 50 50
Vs
= 137500
: 103 :
circuit for AC, eliminating the gain reducing
17.
Sol:
emitter resistor RE.
RC Coupled Amplifier Analysis
* Purpose of output capacitor CC is to block DC
+VCC
and allow AC signal.

* RC, RL are load resistors.
R1
RC
18. Find the DC collector current if is 100 and

if Vt = 25 mV.
V
Find voltage gain 0 , VBE (ON) = 0.7V
Vin
CC
+
+
Vin
RL
R2
RE
+10 V
V0
CE
9.3 K
2K
V0
+
Vin
* The purpose of R1 R2 and the coupling

Capacitor Cb is to superimpose the small signal
V R
Vin at a DC of CC 2 so that the BJT can be
R1 R 2
ON and the nonlinear device can behave as
linear. R1 , R2 resistors are also called biasing
resistors.
* Purpose of RE is to stabilize Ic DC independent
10 V
18.
Sol:
DC analysis:
+10 V
IC = 2mA
9.3 K
2K
of Variations
V0
* CE behaves as open circuit for DC, allowing RE

to play its role in establishing. independent
+ Q2
0.7
Q1
+
Vbe
9.3K
5K
IF = 2mA
DC collector current. CE behaves as short

10 V
: 104 :
IE
VCC Vbe 10 0.7
1mA
RE
9.3K
AC equivalent:
+
Vbe

100
I CDC
I E
1mA 0.99mA
101
1
gmVbe/Ib
I CDC 1mA
VC1 10 I CDC R C
B
VC1 10 0.99 2k 8.019 V
+
Vin
(1) VE1 0.7 V

(2) I E1
Vbe 2.5k
1
__
1
25
Vbe
1_
9.3K
1.25k
Vbe
200
+
2
__
Vbe
2
25
+
2k V0(AC)
VE1 10
1mA I C1
9.3k
(3) VC1 10 I C1 9.3k 0.7 V
V0
Vbe 2 2k ----(1)
25
(4) VE 2 VC1 0.7 V 0V
0 10
2mA
5k
(6) V0 10 I C2 2k 10 2 2 6V
Vbe2 Vbe1 9.3k || 1.25k --- (2)

25
(5) I E 2
Vin Vbe1
AC Analysis:
Q1
Q2
I C1
IC
1m
gm1
0.04 g
2 2 0.08
m2
25m 25m
25m 25
100
100
=2.5k
r 1
r 2
125 0
1
gm
2
25
25
V0
V Vbe Vbe1
0 . 2
Vin Vbe2 Vbe1 Vin
2 1
2k 9.3 || 1.251
25 25
4k
7052
252
AV = 7052
AC analysis:
9.3 K
B
AV
E
+
Vin
9.3K
2K
B
V0
E
5K
__
: 105 :
(b)
5. Feedback Amplifiers

gain with feedback
1000
1 1000 0.01
1000
90.9
1 10
Feedback Amplifier:
01.
Sol: Given data is
A0
1 A 0
02.
Open loop gain of an amplifier

A0 = 1000 11
+VCC
It is known that if open loop gain varies by
dA
% , then the % change in closed loop gain is
A
RC3
RC 2
RC1
given by
dA
dA f
A
Af
1 A
(a)
+
+
Vs 0V
R2
I0
R3
R1
it is given that
Let us neglect the drop (VBE) across base and
emitter junction
The equivalent circuit diagram is
A0 = 1000 11
x % of 1000 = 11
x = 1.1 %
R2
the percentage change in closed loop gain
dA f
0 .1
Af
from
the
I0
+
Vs
problem
R1
R3
statement]
1 .1
0 .1
1 1000
1.1 0.1 + 100
1 100
0.01
Feedback factor required is
0.01
Vs
I0 R 3
R1
R 3 R1 R 2
VS
I 0 R 1R 3
R1 R 2 R 3
I0 R1 R 2 R 3
Vs
R 1R 3
I0
R2
1
1
VS R 3 R 1R 3 R 1
: 106 :
03:
04.
Sol:
+VCC
1. Voltage Series Feedback Amplifier:
Cc
0V
RS
VS
R5
R3
R E1
RC
R4
RC1
R2
CS
V0
+
Vi
+
Vs
V0
+
Vx
Vf
R1
+
R L V0
Voltage
Amplifier,
AV
CE
Figure.6. Block diagram (Topology)

of voltage-series feedback amplifier
RF
V0 = I0RC
V0
R C
I0
IE IC = I0
I0
Vx
Ii
RF
RS
+
VS
Is
I0
+
+
+
Vs
0V
R1
R0
IS
Vi
+
Ri AVVi
0
RV
L
Vf=V0
V
f
Figure.7. Small-signal model of voltage-series

feedback amplifier
Vs
I
1
s
Rs
Vs R s
And I s
R 1I 0
R1 R F
R
I0
1 F
Is
R1
voltage gian
V0 V0 I 0 I s
. .
Vs I 0 I s Vs
R 1
R c 1 F
R 1 R s
V0 R E
1
Vs R 1
R C
R s
Input resistance Rif =VS/Ii:

The input impedance of the amplifier without
feedback is Ri = Vi/Ii
The input impedance of voltage-series
feedback amplifier is, Rif = Vs/Ii
V
Consider R i i
Ii
V Vf
Vi Vs Vf
Ri s
Ii
Ri
Vs V0
Vf V0
Ii
: 107 :
Vs .AVi
V0 AVi
Ii
IiRi = VsAVi

feedback factor
Ri
the percentage change in closed loop gain is
IiRi = VsAIiRi
dA
dA f
A
Af
1 A
IiRi+AIiRi = Vs
(1+A) IiRi=Vs
(1+A)IiRi = Vs
40
1 10 6
1
4
0.000159%
06.
Sol:
V
S R i (1 A)
Ii

+Vcc
Rif = Ri (1+A)
RF
Is
1
4
Therefore, for voltage-series feedback

amplifier, the input impedance is increased by
a factor of (1+A).
05
Sol:
0V +
IS
RC
V0
Neglecting base current

The given data is open loop gain of an op-amp
(A) = 106
The given circuit diagram is
+
Vs
3k
1k
V0
0 V0
Is 0
RF
V0
Is
RF
V0
R F
Is
Loop gain A f 1 F
R1
Af = (1 +3) = 4
: 108 :
6. Oscillators
2.5V
Vin
0
-2.5V
01.
Sol:
It is a regenerative circuit (Positive feedback)
which has two thresholds, UTP and LTP. UTP
stands for Upper Threshold Point and LTP for
Lower Threshold Point. The Schmitt trigger
output switches from +Vsat to Vsat when input
Vin is greater than UTP. The output switches from
Vsat to +Vsat when input Vin is less than LTP.
The output does not change when Vin is between
UTP and LTP.
+10V
V 0
0
10V
Transfer Characteristics
+10V
+Vsat
Vin
_
V0
-10V
7.5K
V 0
-2.5V
2.5V
Vin
2.5K
Vt = VUTP when V0 = +10V
-Vsat
Vt = VLTP when V0 = -10V

02.
-10V
+10V
7.5K
7.5K
+
VUTP = 2.5V
+
2.5K VLTP = -2.5V
2.5K
: 109 :
03.
KCL
0 Vin 0 VB 0 VB
R R 2R 0
Sol: FULL WAVE RECTIFIER (FWR)

R
R
R
R
D1
+
Vi
n
2 Vin 3 VB
0 3VB 2 Vin
2R
V
O
Vx
VB
D2
R
Case 1
KCL
VB 0 VB VO
0
2R R
:
Vin Pos
D1 FB
Vx NegD2 RB
VB 2 VB 2 VO
3
0 VO VB
2R
2
R
R
R
VA
0.7
V
+
Vin
2
Vin
3
VO
3
2
3 Vin
V0 = Vin
R
VO
VA
R
R
VA
Vin
R
Vin
V0 = Vin
Case 2
Vin Neg
Vx Pos
D1 RB
D2 FB
R
R
R
+
Vin
0V
+
0.7V
VB
VB +
VO
V0
t
0
V0 = Vin
V0 = - Vin
V
: 110 :
04.
Case 2:
Sol: Peak Detector
Vin < VC Vx = Vsat Diode RB (Op amp in

open loop configuration)
Vx
+
Vin
VC
V0
VC
Vx
+
Vin
V0 = VC
VC
V0
Vx
Vin
Vin > VC Vx = + Vsat Diode FB

Vin < VC Vx = - Vsat Diode RB
Case 1 :
Vin > VC Vx = + Vsat Diode FB Op amp in
Negative feedback (virtual ground is valid)
Vin
Vin
t
0.7
+
VX
+
Vin
VC Vx = 0.7 + Vin
Capacitors charges to the new voltage Vin > VC
Case 1
V0 = VC
Case 2
05.
Sol: Log amplifier:
Consider the circuit in the fig shown below.
The diode is to be forward biased, so the
input signal voltage is limited to positive
values. The diode current is
: 111 :
VVD
i D I s e T 1
Antilog (or) Exponential amplifiers:
i1
VD
D1
R1
Vi
V1 = 0
V2 = 0
The complement or inverse function of the

log amplifier is the antilog, or exponential,
amplifier, a simple example using diode is
shown below
iD
V0
Vi
V1 = 0
iD
i2
V0
If the diode is sufficiently forward biase,

the 1 term is negligible, and
i D Ise
Fig. A simple
amplifier
VD
VT
exponential
Vi
The input current can be written

i1
antilog (or)
i D I s e VT and V0 = i2R = iD R
V1
R1
(or) V0 I s R.e
And the output voltage, since v1 is at virtual

ground, is given by
Vi
Vt
The output voltage is an exponential

function of input voltage
V0 = VD
Noting that i1 = iD, we can write
V0
V
i1 i i D I s e VT
R1
If we take the natural log of both sides of

this equation, we obtain
V V0
ln i
R 1I s VT
06.
Sol: TRIANGULAR WAVE GENERATOR
C
_
+
R3
R1
V0
Vt
R2
V
V0 VT ln i
Is R1
Above equation indicates that, for this
circuit, the output voltage is proportional to
the log of the input voltage
V0
+V _
V0
Schmitt
trigger
Miller
integrato
r
: 112 :
0 V01 0 V0
0
R1 R 2
If V01 = +Vsat V0
i.e. V0
V0
R 2 V01
R1
Find the frequency of triangular wave

VC t VC 0
R 2 Vsat
for Vt = 0V
R1
At t
Vsat
i.e. V0
1
I dt
C 0
R 2 Vsat 1 Vsat
VC t

dt
R1
C 0 R3
R 2 Vsat
for V01 to switch from +Vsat to
R1
If V01 = Vsat V0
R 2 Vsat
for Vt = 0V
R1
R 2 Vsat
for V01 to switch from Vsat to
R1
T
2
VC t
R 2 Vsat
R1
R 2 Vsat R 2 Vsat Vsat T

R1
R1
CR 3 2
2R 2 Vsat Vsat T
R1
2CR 3
+Vsat
+Vsat
R 2 Vsat
4R 2 R 3C
R1
R1
V01
R 2 Vsat
R1
-Vsat
VC = -V0
Frequency f
R1
1
T 4R 2 R 3C
07.
Sol: ASTABLE MULTIVIBRATOR
(USING OP-AMP)
R
T
+10V
_
R 2 Vsat
R1
V0
+
+
VC
-10V
R 2 Vsat
R1
Vt
T/2
R1 = 5K
R2 = 5K
T
: 113 :
Initially, the moment you switch ON,

assume, output is at +Vsat = 10V. The
threshold voltage Vt = 5V. The capacitor
charges from the output port towards +10V.
Once the capacitor voltage crosses slightly
greater than +5V, the difference at the input
of an op-amp becomes negative and output
switches to Vsat = -10V.
VC t Vinitial Vfinal e RC Vfinal

t
R 2 Vsat
RC
Vsat e Vsat
R1 R 2
At t
Now the new threshold Vt = -5V and

capacitor as usual charges from the output
port towards -10V. But as it reaches slightly
below -5V, the difference Vd becomes
positive and output switches to +10V.
T
2 RC
+5
V
VC
0
5V
+10
V
V0
0
T
2
VC t
R 2 Vsat
R1 R 2
T
R2
2RC
R 2 Vsat
Vsat
1 e
Vsat
R1 R 2
R1 R 2
This procedure continues to build a square

wave at the output.
R2
R2
1
1
R1 R 2
R1 R 2
T
2 RC
R1
R 1 2R 2
Time period of square wave
R1
R 1 2R 2
T 2RC n
08.
T
10
Calculation of time period of square wave
V
+Vsat
final
R 2 Vsat
R1 R 2
R 2 Vsat
R1 R 2
initial
Sol: If the circuit has to oscillate and generate a

sine wave, it should simulate a 2nd order
differential equation(two pole system). This
is possible by a minimum of two RC
networks or one LC Network if op-amp
open loop gain is real. In the problem given,
op-amp is a single pole system. So with a
single capacitor externally connected, it
should sustain a sine wave when the loop
gain is equal to one [Barkhausens criterion]
If a circuit has to oscillate, loop gain = 1
T/2
T
Vf Vx V0
1
V0 Vf Vx
: 114 :
Vf
V0 R 1
R1 R 2
Put s = j and equate real and imaginary

parts on both sides Equate imaginary parts
Vf
R1
V0 R 1 R 2
1
V0
sC
V0
0
Vx
1
1 sC 0 R 0
R0
sC 0
V0
1 sC 0 R 0
Vx
Vf Vx Vd
V0
V0 Vf Vx
,
A Vf Vf Vf A
R2
1
R1
Vx
1
Vf
A
R2
1
R1
Vx
1
Vf
A
R2
1
R1
Vx
1
Vf
1
R1 R 2
C0R 0
R
1 1
R2
1
R1
1
C0R 0
R1
sR1 R 2 s2C0 R0 R1 R 2
1
sC
R
=1
0 0
R1 R 2
R1 1
R1 1
9K
1K 10K rad / sec

0.1F(10K )
Equate real parts
sR 1 R 2
1
1 sC 0 R 0 = 1
R
1
1
R R2
s C 0 R 0 1
0
R 11
R1
R1 R 2
Vf Vx V0
1
V0 Vf Vx
R1
R1 R 2
2 C 0 R 0 (R 1 R 2 )
1
1
R 11
1
R
2
R R1
C 0 R 0 1 2
R1
R
1 2
R1
C0R 0
R2
R R1
C 0 R 0 1 2
R1
2 C 02 R 02 1
R2
R1
R2
1
R1
9K
1K
C 0 R 0 0.1F.10K
= 3K rad/sec
: 115 :
09.
Sol: The above circuit can be drawn as
Vf
SCR
2 2 2
V0 S C R 3SCR 1
R
RF
C
+
1
3 SCR
1
Step 2:
1
SCR
3 j RC
RC
V
R
A 0 1 F
Vf
R1
RF
R1
R1
V0
+
Vf
Step 1
Step 3:
A = 1 A
Vf
V0
V0
Vf
1
1
R
SC
R
1
SC
1 SCR
R
SC
R
Z Shunt
Z series R
Loop gain = 1
1 1 SCR
SC
SC
V0 Z shunt
Z series Z shunt
RF
1
3 j RC
R1
RC
Equate Imaginary Parts:

1
0 RC
RC
1
1
2 2 2 f
2RC
R C
Frequency of Oscillation
Equate Real Parts:
RF
3
R1
RF = 2R1
Condition for sustained Oscillations
: 116 :
10.
For a good Oscillator the variation of phase with
Sol:
respect to frequency should be very high ideally

Magnitude and phase response of RC
network in wein bridge Oscillator.
| |
0
0
2
1
1
0
RC 3
0
2
1
1
3 j RC
RC
| |
3 RC
RC
2
2 2
d
1 R C 1
; tan
d
3RC
d
d
1
3
||
A0
10 6
S
S
1
1
3db
10
3db = Band width

A0
3db
A0 = DC Gain
d
6 2 R 3 C 3 2
2
1
RC
2
2
2
d
3
3
9 R C
RC
Gain
At high frequency of Oscillation, RC network

have a slow variation of phase with respect to
frequency. If the Basic amplifier [op-amp] suffers
a phase lag, the compensation has to
automatically come from the RC network to give
a phase lead. But to give a small phase lead, the
variation of frequency is enormous. So the
frequency stability of RC Oscillators at high
frequency is poor. Let us prove.
RC
RC
tan 1
3
1
RC
3RC 2R 2 C 2 2 R 2 C 2 1 3RC
2
2 2 2
9 R C
2 R 2 C 2 1
1
3RC
1
1
RC
3db
: 117 :
RF = 2R1
R1
9 10 6
0.45 rad / sec stable
2 10 7
At a high frequency of 100K
rad
sec
Variation in frequency
=
R1
1
R F R1 3
Af
We conclude than RC network suffer from

this major disadvantage that their phase
verses frequency response is very poor. For
a high frequency of 100 K rad/sec there is
error of 4.5% [i.e. 4.5 K rad/sec]. So we go
for wide band amplifiers with LC network
for high frequency of Oscillation.
3
3
3S
S
1 7 1
10
10 7
Phase lag suffered
by the Amplifier
3
3
= tan 1 7 ~ 7
10
10
9 1010
4.5K rad / sec 4.5% error.
2 10 7
11.
Sol: HARTLEYS OSCILLATORS:
RF
This is compensated by RC network at a rate

d
2
d 3
_
R1
Variation of frequency to compensate

d d
2

3
3
7
9 2
10
2 2 10 7

3
At a frequency
1 K rad
sec
L1
(1)
Z1 + Z2 + Z3 = 0
SL1 + SL2 +
1
0
SC
S L 1 L 2 2 0
S C
Variation in frequency
L1 L 2
L2
2 C
1
Leq C
: 118 :
Leq = L1 + L2
(2)
(3)
C eq
Z1 SL1 L1
Z2
SL 2
L2
C1C 2
C1 C 2
(2)
1
V
SC1 C 2
f
1
V0
C1
SC 2
(3)
R F L2
1
R1
L1
R F L2
R 1 L1
R
C1
R
C
1
f
F 1
R1
C2
R1 C2
13.
12.
Sol:
Sol: Find
COLPITTS OSCILLATOR:
Vf
V0
Rx
Vf
RF
R1
V0
+
1/SC
SL
0.5k
+
Vf
C1
(1)
V0
1 Vf
SC SL 0.5k 0
V
Rx
f
1
1
V0 1
R 0.5k j C L
Z1 + Z2 + Z3 = 0
1
1
SL 0
SC1 SC 2
1 1
1
S 2 L 0

S C1 C 2
V V0
KCL f
Vf
Rx
1
1
1 V0
Vf
j C

L R x
R x 0 .5 k
C2
1
1
2 L
C1 C 2
Vf
1
L Ceq
Step2: Find A
V0
9K
1
10
Vf
1K
Step3: loop gain = 1 A = 1
: 119 :
Rx
1
10
1
1
1
R 0.5k j C L
X S2 C 2 R 2
Z
1 SCR
Given
S 2 C 2 R 2 1
10 0.5k R x
1
j C
R x ( 0 .5 K ) R x
L
Equate imaginary parts and Equate real parts

C
1
SC
1
LC
Frequency of oscillations
2 LC
Z
_
1
Z
X
1
SC
X
1
Z 1 SCR
R
SC
R x 4.5k
X S2 C 2 R 2
1
Z
1 SCR
1 SCR
R
X
_
1
0
L
1
RC 1 2 R 2 C 2 1
RC
C
R
_
+
R
C
14.
Sol: Loop gain = 1
y z x
1
x y z
1 1
SC
SC X 1
1
R R Z
SCR 1 1 X
SCR SCR Z 1
This Oscillator is a Quadrature Oscillator.

90
SCR1 1 1
SCR SCR 1SCR
-90
-90
-90
: 120 :
Note:
3
2CR F
RC phase shift Oscillator is a fixed audio

frequency Oscillator whereas wein bridge
Oscillator is a variable audio frequency
Oscillator. For high frequency of Oscillations
we go for wide band amplifiers with LC
Network.
Condition for sustained Oscillations

RF = 2R1
A
15.
Sol: Loop gain = 1
y z x
1
x y z
A33 = 1360
y
1
x
R F || SC
1;
3
R 1
3 = 360
= 120
RF
R
1
1 SCR F
16.
Find
Sol:
1
SC
RF
32
1 SCR F
R1
Vf
V0
1
SC
1
SC
+
R
V0
_
Vf
1 S3C3 R F 3SCR F 3S2 C 2 R F

3
RF
3
2
3 3
2 2
1 j C R F j3CR F 3 C R F
R1
Vf
S3 C 3 R 3
3 3 3
V0 S C R 6S 2 C 2 R 2 5SCR 1
Equate imaginary parts and real parts
V0 R F
Vf
R1
0 = 3CRF-3C3RF3
3
RF
2
2 2
1 3 C R F
R1
Vf
R1
RF
_
+
V0
Frequency of Oscillations
Loop gain = 1
: 121 :
A=1
RF
R1
17.
j 3 C 3 R 3
1
3 3 3
2 2
2
C
R
C
R
j
5
RC

Rx
Equate real parts on both sides

0 = 1 62C2R2
1
2 C 2 R 2
6
1
RC 6
2RC 6
Equate Imaginary Parts

RF 3 3 3
C R 5RC 3C3R 3
R1
RF 2 2 2
C R 5 2C 2 R 2
R
1
RF
R1
Vf
C
C
R
Condition for oscillation is
V0
1
1
5
6
6
A = 1
Where A = gain of amplifier
= feedback factor
Calculation of gain (A) :
As it is a non inverting amplifier
R
A 1 x
R
Calculation of feed back factor () :

1/sC Vx
RF = 29R1
V0 +
R
R 1/sC
+
Vf
A = 29180
KCL at node (2)
1
180
29
Vx V0 Vx Vx Vf
0
1
R
R
sC
: 122 :
Vx V0 sC Vx
R
Vx Vf
0
R
Vx 2 sCR V0 sCR Vf 0 1
R x 1 2 R 2 C 2 j3RC
R
jRC
1
KCL at node (3)

Vf Vx Vf 0
0
1
R
sC
Rx
j 1 2 R 2 C 2
3
R
RC
Equate real parts on both the sides

1
Vf Vx + Vf sCR = 0
Rx
3
R
Rx = 2R
Vx = (1+ sCR)Vf ----(2)

From (1) and (2)
(1+sCR)Vf [2+sCR] V0 sCR Vf = 0
[(1+sCR) (2+sCR) 1] Vf = V0 sCR
s C R
2
3sCR 2 1 Vf V0 sCR
Vf
sCR
2 2 2
V0 s C R 3sRC 1
Equate imaginary parts on both the sides
2 R 2 C 2 1
1
RC
1
2RC
Put s= j
Vf
jRC
2 2 2
V0 R C j3RC 1
We know, for sustained oscillation the

condition to be satisfied is
A = 1
1 2 R 2 C 2
0
RC
The condition for sustained oscillations

Rx = 2R
The frequency of oscillations is
1
2RC
: 123 :
7. Power Amplifiers

L
Vi
D
R1
Sol: The term switched mode regulator is used to

describe a circuit that takes d.c. input
(unregulated) and provides single dc output of
the same or opposite polarity, and of a lower
or higher voltage. The switched mode
regulators use an inductor and there is no
input to output isolation.
Limitations of linear voltage regulators
as compared to switching regulators
Variable pulse
width OSC
01.
+
VZ
RF
RL
R1
(Step down regulator (or) Buck)

L
Vi
+
VZ
Vo
R1
1. The
required
input
stepdown
transformer is bulky and expensive
2. Due to low line frequency [50Hz], large
values of filter capacitors are required.
3. The efficiency is very low.
4 Input must be greater than output
voltage.
5. Larger the difference b/w input and
output voltage, more is the power
dissipation in the series pass transistor.
6. For higher input voltages and low
o/p voltage, efficiency decreases.
Hence in modern days, to overcome all
these limitations switched mode power
supplies [SMPS] are used.
There are three basic configurations of the
switching regulators
1. Step down or Buck switching regulator
2. Step up or Boost switching regulator.
3. Inverting type switching regulator.
Vo
Variable pulse
width OSC
RL
RF
R1
(Step up or Boost Regulator)
Vi
+
VZ
Vo
R1
+
Variable pulse
width OSC
L
RF
RL
R1
(Voltage Inverter (or) Buck - Boost)
: 124 :
Buck switching regulator :
Case2:
The pulse width oscillator controls the

operation of Q1 transistor ON or OFF,
depending on the load requirement.
If Q1 is OFF (cutoff), the magnetic field of

the inductor L collapse and its polarity gets
reversed. This is because an inductor
current cannot change instantly. Due to the
reversal of polarity, it gets added to Vin.
When Q1 is ON, the cap charges and when

Q1 is OFF, the cap discharges through the
load resistance.
Q1 ON
VL
ON Period
+
Vo
RL
+
Vin
IL(0) = IL(0+)
IL =
=
Q1 OFF
+
Vin
VL
Diode
ON
+
Vo
RL
1
VL dt
L
1
(Vin Vsat ) dt
L
(Vsat 0V, Vin = constant)

=
1
Vin dt
L
IL(ON) =
If ON time is more then o/p voltage
increases and if OFF time is more, o/p
voltage decreases this adjusting the duty
t ON
t
cycle
ON o/p voltage can
t ON t OFF
T
be regulated.
= tON.f and Vo = Vin
Step-up switching regulator (Boost)
Case1:
Let Q1 is ON
VL = Vin VCEsat
This expands the magnetic field around the
inductor very quickly. The longer the ON
time of Q1, the smaller will be the voltage
across L.
1
Vin [ t ON ]
L
OFF Period
Vout = Vin + VL
VL = Vout Vin
IL =
=
1
VL dt
L
1
(Vout Vin )dt
L
IL(OFF) =
Vout Vin
( t OFF )
L
I L (0 ) I L (0 )
(V Vin )
1
Vin ( t ON ) out
( t OFF )
L
L
: 125 :
Advantages
t t
Vout = Vin OFF ON
t OFF
1. Higher efficiency
t ON
t OFF
But =
and 1 =
t ON t OFF
t ON t OFF
2. Simple to design
3. Low ripple content
4. Small output filter
Vout
V
in
1
5. Low switch stress

6. Large tolerance
regulation
If = 0.5 [50% Duty cycle]

Vout =
Vin
1
of
line
voltage
7. Low cost, size and weight

Disadvantages
Vout = 2 Vin
1. Single output
If the output voltage decreases, the voltage

across R3 decreases. The reference voltage
Vz is fixed. The error at the input of error
amplifier is more. This produces a pulse of
higher width and capacitor charges
increasing-the output voltage.
2. No isolation between input and output
If the output voltage increases, the voltage

across R3 increases. The error at the input of
the amplifier decreases. The output of error
amplifier controls the output of variable
pulse width oscillator. It produces pulse of
smaller width which reduces tON for Q1.
This makes the capacitor C to discharge
more, and the increased output voltage gets
compensated
6. Due to finite reverse recovery time of

commutating diode, the instantaneous
short circuit occurs across the source,
due to which active switches may fail.
tON > tOFF

Vc=Vo
4. The input voltage must be always

slightly greater than output
5. Slow transient response compared to
linear regulators
Voltage inverter type switching

Regulator [Buck-Boost]:
This type of switching regulator produces
output voltage having polarity opposite to
that of the input voltage.
Case1:
Vout
Q1 is switched ON in sat the voltage across

an inductor suddenly rises to Vin- VCE sat and
tON < tOFF
the magnetic field around it expands. The

diode is reverse biased. The inductor
voltage starts exponentially decreasing from
the initial value Vin- VCE sat .
t
3. High input ripple current
: 126 :

2
Case2:
1 V
1 VCC
CC R L
(1)
2 RL
2 RL
Q1 is switched OFF, the magnetic field

across L tries to collapse. But inductor
current cannot change instantaneously. Thus
the voltage across inductor VL reverses its
polarity.
ICmax
IC total
0
Due to the reversed VL, D1 is FB. The

capacitor changes through D1 producing an
output voltage of opposite polarity to that of
Vin. Hence the regulator is called voltage
inverter type.
Pin = VCC IC total avg
2I
VCC C max

The repetitive ON-OFF action of Q1

produces a repetitive changing and
discharging of the capacitor C which is
smoothed by the LC filter action.
02.
V
2
VCC CC
RL
2 VCC
RL
PO
100%
Pin
100% = 78.5%
4
efficiency
Sol: Refer the solution of Question no. 11 in

chapter 6
04.
03.
Sol:
Sol: Efficiency of class B power amplifier
DC equivalent
+VCC
+VCC
R1
+
Vin
_
RL
_
-VCC
PO
1 2
IL R L
2 m
VL = VCC
VCE
_
R2
RE
IE
: 127 :
V CE VCC I
DC
C
DC
IC
IC
C
DC
V CE VCC I
DC
R C R E
total
DC
R DC (1)
DC
I C ( AC) R AC (2)
VCE
( AC )
-IC(AC)
AC equivalent
total
VCC I C
VCE
R DC (1)
when VCE
total max
By supersposition
+
VCE
_
+
Vin ~
_
IC
IC
total
RC||RL
R1||R2
IC
DC
VCE
VCE
total
VCE
total
CE
( AC )
CE
( AC )
total
I C ( AC) R AC (2)
total
LOCATION OF Q POINT
For maximum symmetrical swing Q point
should be located in the middle of the
characteristic satisfying the relation.
when VCE
total
0 VCE
I C I C
R AC
DC
DC
total max
IC
IC
VCE
DC
total max
DC
R AC
maximum
symmetrical
swing
I C total max 2I C DC
Sat
I CDC
I C I C R AC (5)
total
DC
total max
For
I Ctotal max
DC
IC
IC
(4)
( AC )
I C R AC [from 2]
DC
AC
VCE
VCE
I C ( AC) R C || R L
VCE
DC
VCE
(3)
AC
IC total max
Sub in (6)
Active
ICQ
region
IC
2I C
DC
cutoff
IC
DC
DC
VCE
DC
R AC
VCE
DC
R AC
IC
DC
VCC I C
R DC
DC
R AC
Max current in a BJT occurs when the swing

almost touches saturation where V CE 0
total
: 128 :
IC
DC
VCC
I CQ
R AC R DC
(location of Q
I C total max I C
DC
point) where RAC = RC || RL
VCE total max VCE
IC total max
R AC
IC
R AC
DC
Slope of DC load line

AC load line
V
CC
R
= DC
VCC
IB5
IB4
Q Point
IB3
Slope of AC load line
DC load line
IB2
IC total
(VCC, 0)
equation for DC load
VCC I C
DC
R DC
DC
1
R DC
I C total max
VCE total max
VCE
DC
I C DC
R AC
1
VCE I C R AC R AC
IB1
VCE
DC
DC
RDC = RC + RE
VCC
0,
R DC
VCE
line.
DC
DC
05.
IC
VCE
VCC
R DC
VCC
Sol:
Class A [RC coupled amplifier] Power
amplifier:
+VCC
equation for AC
VCE load
Vline.
I C I C R AC
CE
total
DC
DC
total
ICtotal
VCEtotal
ICtotal max
VCEtotal max
RC
R1
+
Vin
_
~
R2
RE
RL
+
V0
_
: 129 :
Class A [Direct coupled Amplifier] Power

Amplifier:
+VCC
During positive cycle of Vin QN is ON and QP is

OFF. But the BJT is not ON, till Vin is greater
than 0.7V.
+VCC
RC (load)
R1
+
Vin
_
+
Vin ~
_
+
0.7 _
RE
R2
RL
+
V0 = VB 0.7
_
= Vin 0.7
Class A
[transformer coupled amplifier]
power amplifier:
+VCC
1:1
During negative cycle of Vin, QP is ON and QN is

OFF. But the BJT is not ON till Vin is lesser than
-0.7V.
0.7 +
_
RC
R1
+
Vin
_
Vin
_
~
VCC
R2
06.
+VCC
Vin
0.7
Sol:
QN
-0.7
Vin
_
RL
QP
QP
-VCC
RL
+
V0
_
V0
0
Crossover
distortion
: 130 :
The inability of the circuit at zero crossing as QN

needs 0.7V and QP -0.7V, leads to crossover
distortion. It can be eliminated if the base-emitter
junction is made ON for voltages for less than
07.
Sol:
Efficiency of transformer coupled amplifier
[class A]
+VCC
1:1
0.7. Hence include a precision diode or super

RC
R1
diode.
+VCC
Vin
_
+
+
Vin
_
RL
+
VL
_
R AC
R2
N
1
N2
R C R C
-VCC
This circuit eliminates cross over distortion.
V0
-0.7
RC
RDC = DC resistance of inductor is zero

0.7
Vin
I CQ
Transfer characteristics
without op-amp
I CQ
VCC
V
1
CC
(1)
R AC R DC
RC
VCC R C
PO avg
1 2
I Lm R L
2
V0
Vin
Transfer characteristics with

op-amp
N1:N2 = 1:1
1 2
I Cm R L (for maximum efficiency)
2
Pin avg = VCC ICQ

1 2
I R
PO 2 C Q C 1 I CQ

R C
Pin
VCC I CQ
2 VCC
(2)
: 131 :
Then the output voltage
Sub (2) in (1)
efficiency
R
V0 1 2 V3
R1
P0
1
100% 100% 50%
Pin
2
Whenever all the sources are present
8. Operational Amplifiers
R
V0 1 F maxV1 , V2 , V3
R1
01.
Sol: Given circuit diagram
R1 V
N
02.
R2
+
+
V1
-
VA1
D1
Vin
+
V2
+15V
+5V
VA2 D
2
Vo
+
-
Vo 150
VB
=100
VE
VA3 D
3
10
15V
10k
V3
15V
Whenever Vin = 2V, the output is at +Vsat

When V1 is present and remaining are not
present then the output voltage
R
V0 1 2 V1
R1
Transistor is ON
Now there is a negative feedback from output to
input

present
So virtual ground concept is valid
Then the output voltage
IE
R
V0 1 2 V2
R1

present
VE = Vin = 2V
2 15 17
10
10
IE =1.7A
IB
IE
1 .7
16.83mA
1 101
: 132 :
V0 VB 150 I B
IE
V0 VE 0.7 150 16.83mA VE 0.7 2.5245

V0 Vin 0.7 2.5245
2
2mA
1k
V0 1k 3k 2mA
= 4k 2m
2 0.7 2.5245 5.2245V
V0= 8V
VCE = 15 Vin
IE = (1 + )Ix
VCE ranges from 10 to 15 V [i.e VCE > 0.2 V]
Ix = (1 + ) I0
BJT is in active region
I0
Ix
1
I0
IE
1 2
I0
2mA
2m
2
1 99 100 2
03.
Sol: Given circuit diagram
+V
Vref =2V
IO
+
Q1
V +
01 V
BE1
+
Q2
VBE2
VO
I0 = 0.2 A
3k
Vx
IE
The required values V0 = 8V, I0 = 0.2 A
1k
04.
Initially Vref = +2V, Vx= 0
Sol:
Given data is
The voltage V01 = +Vsat

+ Vdrop=2V
Two transistors Q1 and Q2 are ON

There is a negative feedback exists
Vin
7805
+
5V
_
So virtual ground concept is valid

Vx = Vref = 2V
Vo
0.25A
IQ=o
RL=76
: 133 :
From the figure

I = 0.25 A
R
VB2
2k
10.7
5.35mA
2k
Here the is not given. Assume high value
of that implies base current can almost be
neglected
5
R
5
20
0.25
V0 = I [R + RL] ( IQ =0)
= 0.25 [20 +76]
I = 5.35 mA
= 24 V
V0 = I [1 k +2k]
By KVL
= 3k 5.35 m = 16.05 V
Vin Vdrop V0 = 0
Vin = Vdrop + V0
RL
= 2 + 24
Vin= 26 V
16.05
32.1
0 .5
From the fig

VB1 V0 VBE1
05.
Sol:
IE1
Q1
IR2
IR1
2k
IB1
VB1
IC2
10k
Vin=30V
Q2
+
10V
_
VBE1
+
0.5A
RL
I
IR2
1k
2k
I R1
From the figure it is clear that

VB2 Vz VBE 2
=10V +0.7
Vin VB1
2k
30 16.75
2k
13.25
6.625mA
2k
VB2
+
VBE2
IZ
16.05 0.7 16.75V
Vo
Vin Vz
10k
30 10 20
2mA
10k
10k
As is very high
I B1 0A
= 10.7V
: 134 :
I C2 I R 2 6.625mA
07.
Sol: Non Inverting Summer:
I C2 I E 2 6.25mA
RF
R
I Z I E 2 I R1
Vx
R
= 2mA +6.625 mA
V1
V2
V3
= 8.625 mA
Vx
I1
I2
I3
R
R
From the figure, KCL at output node
KCL
I E1 I I L
Vx VR Vx V2 Vx V3
0
R
R
R
= 5.35 mA + 0.5A
= 0.50535 A
is very high
I B1 0 I E1 I c1 0.50535A
Power dissipation in the zener diode:

P = Vz Iz
P = 10 8.625 mA
P = 86.25 mW
3Vx V1 V2 V3
0
R
R
Vx
V1 V2 V3
3
Vx 0 Vx V0
0
R
RF
Vx Vx V0
R RF RF
1
1 V0
Vx
R RF RF
Power dissipation in the transistor Q1 :

P VCE1 I C1
V0
P VC1 VE 1 I C1
P = ( 30 16.05) 0.50535
R RF
V0 R F
Vx
RR F
R V V2 V3
V0 1 F 1
R
3
Choose RF = 2R
P =7.049 W
V0 = V1 + V2 + V3
06.
: 135 :
1
1 V1 V0
VN
---- (1)
R1 R 2 R1 R 2
Inverting summer:
R
V1
V2
V3
RF
I1
I2
I3
R
VN
VP
V0
KCL: IF = I1 + I2 + I3
V1 V0 V2
R1 R 2 R1
0 V1 0 V2 0 V3 =0
R
R
R
(1) / (2)
V0 V1 V2 V3
0
R F
R
RF
V1 V2 V3
R
Assume RF = R
V0 = (V1 + V2 + V3)
V1
R1
VN
VP
R1
V0
R2
V1 V2
R1
V0
R2
V1 V2
R1
V0 = V1 V2
08.
Sol: Differentiator:
A circuit in which the output voltage
waveform is the differentiation of input
voltage is called differentiator
R2
IL
Ie
V1 V2 V0
R1 R1 R 2
If R1 = R2
The output is the inverted sum of voltages

given difference amplifier
V2
VP V2 VP 0
0
R1
R2
1
1 V2
VP
---- (2)
R1 R 2 R1
Virtual short: VN =VP = 0V
V0
V0
If
R2
Virtual ground: VN = VP
KCL
Vin
If
V2
V1
V0
VN V1 VN V0
0
R1
R2
: 136 :
The expression for the output voltage can be
obtained by applying KCL at node V2

Since, Iin = If
C
V0 RC
0 V0
d
(Vin 0)
dt
R
dVin
dt
Thus the output V0 is equal to the RC times

the instantaneous rate of change of the input
The output voltage is directly proportional to

the negative integral of the input voltage and
inversely proportional to the time constant
RC.
If the input is a sine wave the output will be
cosine wave. If the input is a square wave, the
output will be a triangular wave. For accurate
integration, the time period of the input signal
T must be longer than or equal to RC.
If the input is a square wave, the output will
be a triangular wave.
Vin
Vin
voltage Vin with time.

t
V0
Vin
t
V0
Vin
t
V0
V0
Fig: Output waveforms for square and sine

wave inputs.
Integrator:
KCL at node V2
11.
Sol: Band width extension:
Consider an op-amp with an open loop gain
= 106 with a 3db band width = 10 rad/sec. so
the gain-bw product = 10610 = 107
A0
10 6
S
S
1
1
W3db
10
[Before feedback]
Gain
I1 = If and V2 = V1 = 0
d (0 V0 )
Vin 0
C
R
dt
Fig: Output waveforms for square and sine

wave inputs.
Integrating both sides with respect to time

from 0 to t, we get
t
d ( V0 )
Vin
dt C
dt C(V0 ) V0
R
dt
0
1
Vin dt
V0 t 0 0V then V0
R 0
+
2K
if
1K
V0
t 0
+
+
Vin
_
[with feedback]
: 137 :
Sol:
R1
R F R1
1K
1
2K 1K 3
10 6
A
S
1
10
Active Realization of all pass filter :

R
R
Vin
A
Gain with feedback A f
1 A
Af
3
3
1 10
1
6
10
New gain = 3
10 7
New Bandwidth =
3
Before feedback
Gain = 106
Bandwidth = 10
Gain
Bandwidth
product = 107
R vX
V0
1
A
3
3
3S
S
1 7 1
10
10 7
3
1
Vin 1
Vin
Vx =
R 1 SC 1 SCR
SC
KCL
(1)
Vx Vin Vx Vo
0
R
R
Sub (1) in (2)

2Vin
Vin Vo
1 SCR
After feedback
New gain = 3
10 7
3
Bandwidth
New Bandwidth =
Gain
product = 107
Note: Gain-Bandwidth product remains constant

106
2
=V
Vin
o
1 SCR 1
Vo 1 SCR
Vin 1 SCR
Vo
1
Vin
Passive Realization of all pass filter :
Gain
+
V0
3
10
10
3
R
R
V0
R
C
Passive realization
Correct to s- domain
12.
: 138 :
13.
Sol:
Vin(s)
Vy(s) V0
C2
R1
R2
Vx(s)
1/sC
V0
Vin
Vx s
Vin s
1
sC
1
R
sC
Correct to s- domain
1/sC2
V s
in
1 sRC
Vy s
Vin s R Vin s
RR
R
Vin
V
in
1 sCR 2
2V 1 sCR Vin
in
21 sCR
V0
R2
0V
+
Vin(s)
V0(s)
KCL at inverting node
V0 = Vx vy
R1
2Vin Vin Vin sCR

21 sCR
Vin 1 sCR
21 sCR
0 Vin s 0 V0 s
0 1
R1
Z eq
Where Z eq R 2 ||
1
sC 2
1
sC 2
1
R2
sC 2
R2
Z eq
R2
1 sR 2 C 2
Substitute the above value in equation (1)
V0 1 1 sCR

Vin 2 1 sCR
V0 s
Vin s
0
R2
R1
1 sR 2 C 2
1 sC 2 R 2 0
Vin s
V0 s
R1
R2
: 139 :
V0 s
R
1
2
Vin s
R 1 1 sC 2 R 2
Given: mid band gain = A = 33.98dB

Centre frequency = fc = 200Hz
Put s = j
3dB band width = BW = 20Hz
V0 j R 2
1
Vin j
R 1 1 sC 2 R 2
C = 0.1F
The voltage gain in normal scale is
At = 0
20log Av = 33.98
V0 j R 2
Vin j R 1
Av = 101.7
AV = 50.11
The voltage gain of the above amplifier is
At =
V0 j
0
Vin j
AV
R2
R1
( Inverting amplifier)
The given circuit diagram is an LOW
PASS filter
R2
50.11
R1
R2 = 50.11R1 (1)
14.
Sol:
A 2nd order-active Band pass-filter using
The lower cutoff frequency of the amplifiers
operational amplifier is shown below
is
C2
fL fC
BW
2
R2
R
200
V0
The higher cutoff frequency is
Vin
Vout
fH fC
BW
2
200
20
190Hz
2
20
= 210Hz
2
: 140 :
The lower cutoff frequency of the BPF is

fL
1
(2)
2R 2 C 2
15.
Sol: Given circuit is
V0
C1
Given C2 = 1F
fL
1
2R 2 1 10 6
R2
R2
a
VS
V1
R3
R1
b
0v
0v
C2
V0
2 f L 10 6
1
2 190 10 6
fig (a)
Apply Nodal equation at node a
R2 = 837.65
R2 838
V1 VS V1 0 V1 V0 V1 0
+
+
+
=0-----(1)
R2
R3
R1
1 / SC 2
Substituting the value of R2 in (1) we get R1

R1
R2
50.11
Observe that current flowing through R1 is

equal to current flowing through C1 (Because
R1 = 16.71
The frequency response of the filter is shown
below
of high input impedance of op amp no current

flows through the op amp).
M in dB
Apply Nodal at node b

33.98dB
3dB
(34.6dB)
FL=190Hz
fH=210Hz
Therefore to get the above frequency response the
0-V1 0-V0
+
=0
1
R1
SC1
V1
= V0 SC1
R1
V1 = V0SR1C1 -----------(2)
value of R1 & R2 to be
R1 = 16.171
Substitute (2) in (1)
R2 = 838
: 141 :
-V0SR1C1 -VS + V0SR 1C1

+
V0SR 1C1 V0
R2
V0SR 1C1
1
SC 2
R 1 R 2 C1C 2 R 1 R 2 R 2 R 3 R 3 R 1
R1
R3
=0
-SR1C1 SR1C1 (1+SR1C1 ) 2

V
-S R1C1C2 = s
R1
R2
R3
R3
V0
For
2R 1 R 2 R 3 C 2
1 R1R 2 C1 1
1
1
+
+
2
C2 R1 R 2 R 3
2nd
order
characteristic
V0
Where
The characteristic equation is
S2R1R2R3C1C2+SC1(R1R2+R2R3+R3R1)+R3 = 0
equation
S2 +2 ns + 2n = 0
Natural frequency (n) =
1
R1R 2 C1C 2
Damping factor ( )
=
(R 1 R 2 R 2 R 3 R 3 R 1 )
R 1 R 2 R 3 2 n
Substitute n value in
the
given
cut-off
L = n(1- 2 2) + (1-2 2 )+ (1-2 2 ) 2 +1
V0
-R 2
= 2
VS S R 1R 2 R 3C1C 2 +SC1 (R 1R 2 +R 2 R 3 +R 3 R 1 )+R 3
By comparing with 2nd order Characteristic
equation)
(for
frequency is
S2 R 1R 2 R 3C1C 2 +SR 1R 2 C1 +SR 1R 3C1 +SR 2 R 3C1 +R 3 -Vs
=
R 2R 3
R3
R R +R R +R R
1
S2+S 1 2 2 3 3 1 S+
=0
R 1R 2 R 3 C 2
R1R 2 C1C2
equation
1
R1R 2 C1C 2
n =
1 R1R 2 C1
2
C2
1
1
1
+
+
R1 R 2 R 3
16.
Sol:
The circuit given is a Howland current
source named after its inventor. The output
V
current I L in and it is independent of the
R1
load.
Proof 1:
Vx
V0 R 4
R4 R3
KCL at node X.
Vx Vin Vx V0
IL 0
R1
R2
: 142 :
R R3
1 4
R 4 1
1 V0
1
Ix
R2
R1
R2
R1
1
1
1
1
Vx
Vin V0
IL 0
R
R
R
2
1
1
R 2
V0 R 4
R4 R3
1
1
1
1
V0
Vin I L 0
R
R
R
2
1
2
R1
If
IL
R4
Vin
V0
R1
R 4 R 3
Ix
R1 R 2
R 1R 2
1

0
R 2
R3
1
R 4R 2 R1
If R0 = Ix = 0
R4 R2 (R1+R2) = (R4+R3) R1R2
R4 (R1+R2) = (R4+R3) R1
R4R1 +R4R2 = R4R1+R1R3
R3
1
0
R1 R 4R 2
R3
1
R1 R 4R 2
R1R3 = R2R4
Proof 2:
If the current IL should be independent of
the load voltage, its output resistance
R0 =
R1R3 = R2R4
17.
Sol:
+15V
Let us find R0 [Kill Vin]
RC
Vx
V1
Ix
R1
IC
R2
+
V0
+
Vx
R4
1V
V2
10k
R3
Ro = Rth = 1V/IX
Vx 1V Vx
V0 R 4
R R3
V0 4
R4 R3
R4
IE
2k
15V
Apply KVL in the loop (1) shown in figure

+0.7 + 0.7 VBE IE 2k = 0
: 143 :
+0.7 +0.7 0.7 IE 2k =0

IE
VBE + ISC RSC = VD + VD

0.7 + ISCRSC = 0.7 + 0.7
0 .7
2k
R SC
IE = 0.35 mA
0 .7
I SC
Note:
value is not given, assume to very high
If the short circuit is 1A, then RSC = 0.7 in
IC = IE = 0.3 mA
the absence of two diodes, we can use a

single BJT.
Apply KVL in loop (2)

V1 VBE IC RC V2 = 0
Q1
6.8 0.7 (0.3m) RC = 0
ISC
RSC
0.3 mRc = 6.1

+
6 .1
RC
20.33k
0.3m
R SC
V
BE
I SC
VBE
_
Protection
Circuit
18.
19.
Sol: Short circuit protection
Sol: Foldback current limiting

RSC
VS
ISC
RS
Here the short circuited current is lesser than
VL
Q1
the normal current.
RL
RF
During short circuit

Protection Circuit
Q2
RB
R1
I
V
In case of any short circuit to RL, then a

large current ISC flows through RSC.
: 144 :
VS
VX
Q1
VL
RA
RS
RSC
VB

IE3
VS
I4
RS
RL
RB
RY
RL
VB3
I1
RF
V0
Q3
IC2
IC1
I2
IB1
RF
VZ
Q2
Q1
Q2
R1
RB
I3
RX
R1
I3
VZ
_
R RB
VX R B
VB
VX A
RA RB
RB
R
VX 1 A VBE VL
RB
IZ
20.
Sol:
For a given IC of 7805 the current range can
be increased by the following steup.
R
IR SC VL 1 A VBE VL
RB
R
I I 1 A VBE VL VL
RB
7805
Ix
Io
+
VBE
I0
+
VO
If VL is normal voltage then I = inormal. But in

the case of short circuit, VL = 0.
From the figure it can be inferred that the IC

output current is Ix
R
I ISC 1 A VBE
RB
But to the load the current reaching is Ix (1 +
Hence ISC < Inormal
In this set up the voltage at the output of Ic is
)amount of current
less by an amount of VBE so the efficient way

of current range increased 7805 IC without
effecting its output voltage is
: 145 :
1/3VCC > trigger S = logic 1

1/3VCC < trigger S = logic 0
R
IB
+
VBE
IC
R S
RL
Load
7805
0
0
1
1
IL
21.
0
1
0
1
Q O/P=Q
Previous State
0
1
1
0
Dont try
Sol: 555 TIMER

+VCC
discharge
5K
Reset
Threshold
+
2/3 VCC
5K
trigger
1/3 VCC
Inverter
Output
5K
Discharge
= logic 0 transistor is OFF
+VCC
= logic 1 transistor is ON
2/3 VCC
threshold
1/3 VCC
VCC
3R
VCC
3
+
_
22.
Sol:
SCHMITT TRIGGER
Grid
trigger
Threshold > 2/3VCC R = logic 1

Threshold < 2/3VCC R = Logic 0
1/3 VCC
threshold
output
Reset
+
_
555
VCC
discharge
threshold
control
: 146 :
+VCC
+VCC
5K
100K
Threshold 2/3 VCC +
VX
+
Vin
Reset
5K
trigger 1/3 VCC
Inverter Output
VC
5K
Discharge
R S
100K
VX = 0
VX
VX
VX
VX
V
CC
2
2
VCC
3
V
CC
2
1
VCC
3
O/P
Let
us
assume
1
2
VC VCC
3
VC = OV
Previous
state
VC
0 1
1 0
0 0
0 1
0 1
23.
Sol: MONOSTABLE MULTIVIBRATOR
2
VCC
3
VC = OV
Output
=Q
0 1
Let us give
an external
0
trigger
(VC=0)
1
VC VCC
0
3
Previous
state
Transistor
ON,
capacitor
discharges
Previous
State
Transistor
OFF,
capacitor
will charge
Previous
State
Transistor
ON,
capacitor
discharge
Previous
State
+VCC
Threshold
2/3 VCC
2/3 VCC
Reset
5K
+
_
1/3 VCC
R
5K
+
trigger VCC (or) 0 _
Inverter
VC
Output
5K
+
_VC
trigger
V0
0
: 147 :
2
I ref I 0 1

is large
VC t Vinitial Vfinal e RC Vfinal

t
0 VCC e RC VCC
Iref ~ I0
RC
VC t VCC 1 e
At t = T; VC(t) =
Disadvantages:
2
VCC
3
In this current mirror 2% error is present

for = 100
2
VCC VCC 1 e RC
3
VCE Q VBE 0.7 V
be
Early Effect in Transistor Q2
24.
Sol:
Basic Current Mirror
This is the basic building block in the design
of integrated circuit current sources.
25.
Sol:
+ 15 V
+VCC
1000
Vx
IC1
3k
Load
Vin = 5V
2IC
IC
VCE Q can
anything i.e. there exists a problem called
T = 1.1RC pulse width
Iref
but
I0 = IC
Vx
Load
IL
5V
IE1
2.5k
IC
IC
Let Vin = 5V (not given in the problem)

By virtual concept, the voltage at non
-VCC
I ref
2I
IC C
inverting terminal
2
I C 1

inverting terminal is equal to voltage at
I E1
5
2mA
2 .5 k
: 148 :
is not given, assume to be very high

IB = 0 I C1 I E1 2mA
Vx = 15 IC1 3k
= 15 2 3 = 9V
By virtual concept
VE = VX = 9V
I E2
15 VX 15 9
6mA
1K
1000
Assume to be very high

I L I E 2 6mA

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1

Analog Electronic Circuits

The below circuit diagram behaves as a two

level clipper with clipping levels at 3V &

Here the diodes D1 & D2 are ideal.

Let us assume, the input Vin = 7 sint is given

D1 is Forward biased when

Sol: Given circuit diagram is

D2 is Forward biased when

Both D1 & D2 are Reverse biased when

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The above circuit can be redrawn as below

Postal Coaching Solutions

Vin Negative D1 RB, D2 FB

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Analog Electronic Circuits

Let Vin = 10 sint

But, V ( V) V V V V --- (2)

Postal Coaching Solutions

Risetime (tr) of a step response is defined as

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Analog Electronic Circuits

When f3db is 3 db cutoff frequency (or)

During the next negative cycle, diode D3 is

During the first negative cycle D1 is FB & the

During positive cycle Diode D2 is FB &

+ Vm + Vm +2Vm VC4 2Vm = 0

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Now the original circuit can be redrawn by

During the negative cycle D1 is RB & D2 is

Postal Coaching Solutions

The voltage across diode D1 is +

The voltage across diode D2 is VD2 = Vin + Vm

Sol: Given circuit diagram is

During the positive cycle D1 is FB &

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Analog Electronic Circuits

3. Transistor Biasing and

Sol: Given circuit diagram is

-1000I + 5 = 200I + 0.5

V = 200 I + 0.5 - ( 2) (from the device equation )

It is given in the problem that the transistor is

V = -1000 I + 5 (1) ( from the network)

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Postal Coaching Solutions

4.3 VB = 0.2VB + 0.55

1.2VB = 4.3 0.55

Base voltage, VB = 3.125V

The emitter current, IE =

= 3.125 + 0.7 = 3.825V

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Base voltage, VB = VE 0.7V

The base current, IB =

Common emitter gain

Analog Electronic Circuits

a) Given circuit diagram is

VEC = 2.72 (2.9)

Apply KVL along the loop shown

VEC > 0.2V

The transistor is in Active region

Apply KVL along the loop shown

IERE + IBRB = 9 VBE

Postal Coaching Solutions