Digital PDF

ECE-GATE 2014 Topic Test-Digital
Duration: 90 Minutes
Maximum Marks: 50
Read the following papers instructions carefully:

1. There are a total of 33 questions carrying 50 marks. Questions are of multiple choice type or numerical
answer type. A multiple choice type question will have four choices for the answer with only one correct
choice. For numerical answer type questions, the answer is a number and no choices will be given. A
number as the answer should be entered by writing approximate value.
2. Q.1- Q.13 are of multiple choice type and carries 1 mark each. Q.14- Q.16 are of numerical answer type
and carries 1 mark each. Q.17- Q.24 are of multiple choice type and carries 2 marks each. Q.25- Q.29
are of numerical answer type and carries 2 marks each.Q.30-Q.31 include one pair of common data
questions which are of numerical answer type and carries 2 marks each and Q.32-Q.33 include one pair
of linked answer questions which are multiple choice type and carries 2 marks each. The answer to the
second question of the linked answer questions depends on the answer to the first question of the pair. If
the first question in the linked pair is wrongly answered or is not attempted then the answer to the second
question in the pair will not be evaluated.
3. Questions not attempted will result in zero mark. Wrong answers for multiple choice type questions will
result in NEGATIVE marks. For all 1 mark questions, 1/3 mark will be deducted for each wrong
answer. For all 2 marks questions, 2/3 mark will be deducted for each wrong answer. However, in the
case of the linked answer question pair, there will be negative marks only for wrong answer to the first
question and no negative marks for wrong answer to the second question. There is no negative
marking for questions of numerical answer type.
4. Objective questions must be answered on Objective Response Sheet (ORS) by marking (A, B, C, D)
using HB pencil against the question number on the left hand side of the ORS. For Numeric data
questions answer must be marked in form of numerical value only. Each question has only one correct
answer. In case you wish to change an answer, erase the old answer completely. More than one answer
marked against a question will be treated as a wrong answer.
5. Calculator is allowed. Charts, graph sheets or tables are NOT allowed in examination hall
6. Do the rough works in scribble pad provided/ In case of offline it can be done on paper itself?
28A/11, Ground Floor- Jia Sarai New Delhi 16 Ph.: 09811382221, 011-32662945 www.panaceainstitute.org.in
Q.1.
Consider the logic function in Min terms form as f (A, B,C, D) (1,3,5,8,9,11,15) d(2,13) what
are the numbers of complemented literals in the expression of SOP form for f (A, B,C,D)?
(A) 3
(B) 4
(C) 5
(D) 6
Q.2.
Q.3.
For a Boolean function Y AB AC the POS form will be:

(A) (0, 2, 4)
(B) (1, 2,5,7)
(C) (2,3,5,7)
(D) (0, 2, 4,5)
What is the value of f (A, B,C) (f1.f 2 ) f3 if Min-terms of expressions are given as follows?
f1 (A, B, C) (0, 2,3, 4)
f 2 (A, B, C) (1, 2,3)
f3 (A, B, C) (4,5, 6)
(A) (0, 2,3, 4)

Q.4.
Q.5.
Q.6.
Q.7.
Q.8.
Q.9.
(B) (2,3, 4,5,6)
(C) (0,1, 2,3, 4,5,6)
(D) (2,3)
Which of the following identity is not correct?

(A) A B C A (B C) (A B) C
(B) A
CA
(B C) (A
(C) A B AB A
(D) A
CA
(B
AB A B
C) (A
B) C
B)
A 1 bit full adder takes 5 ns to generate carry out bit and 10 ns for the sum bit. What is the maximum
rate of addition per second when four 1-bit full adders are cascaded?
(A) 107
(B) 6.25 106
(C) 4 107
(D) 6.25 107
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean
function of n-variables. What is the Minimum size of Multiplexer needed??
(A) 2n-2 line to 1 line (B) 2n line to 1 line (C) 2n+1 line to 1 line (D) 2n-1 line to 1 line
Which of the following statement is not correct?
(A) Half adder can be implemented by use of five two input NAND gate & five two input NOR gate
(B) Full adder can be implemented by use of nine two input NAND gate & nine two input NOR gate
(C) Half subtractor can be implemented by use of five two input NAND gate & five two input NOR
gate
(D) Half adder can be implemented by use of two 2:1 MUX (inverter is not available)
Consider the following statements. A 4 16 decoder can be constructed with enable inputs by
1. Using 4, 2 4 decoders (each with enable input)
4. Using 2, 3 8 decoders (each with enable i/p & inverter)
Which statements are correct?
(A) Only 1 & 4
(B) Only 2 & 4
(C) Only 1 & 3
(D) Only 2 & 3
A 5 bit serial adder is implemented using two 5 bit shift registers, a full adder and a D Flip-flop. The
two binary words to be added are 11011 and 11011.The sum of the two numbers is stored in one of
the shift registers and the carry in the D Flip-flop. Assuming that D Flip-flop is set initially the
contents of the sum shift register and D Flip-flop respectively are:
(A) 10111 and 0
(B) 11011 and 1
(C) 11101 and 0
(D) 10111 and 1
Q.10. In circuit shown in figure, when inputs A = B = 0, Then possible logic states of C & D are
A
C
D
B
(A) C = 0, D = 1 or C = 1, D = 0
(C) C = 1, D = 0
Q.11. In the circuit shown below initially
D0
Q0
(B) C = 1, D = 1 or C = 0, D = 0
(D) C = 0, D = 1
D1
Q1
Q0
Q1
CLK
Q0 = Q1 = 0 Then what are the values of Q0 and Q1 after 335th clock pulse.
(A) 00
(B) 01
(C) 10
(D) 11
Q.12. An X Y Flip-flop, whose characteristic table given below is to be implemented by use of a JK FlipFlop. This can be done by using
X
0
0
1
1
( A) J X K Y
Y
0
1
0
1
( B) J X K Y
Qn+1
1
Qn
Qn
0
(C ) J Y K X
( D) J Y K X
Q.13. Figure shows a ripple counter using positive edge triggered flip-flops. If the present state of the
counter is Q2 Q1 Q0 = 100 then its next state (Q2 Q1 Q0) will be:
1
1
CLK
(A) 011
T0
Q0
1
T1
Q0
Q1
Q1
(B) 100
T2
Q2
Q2
(C) 111
(D) 101
Q.14. Consider X (54)b where b is the base of the number system. If
X 7 then value of base b is?
Q.15. In a 8 variable K-Map if 32 number of 1s are forming a group then number of literals in that group
after minimization will be?
Q.16. How many essential prime implicates are available in expression of f (A, B,C) (0, 2,3, 4,5,7) ?
Q.17. A combinational circuit accepts a 2 bit binary number and output is square in binary. To design this
circuit using a ROM the minimum size of ROM required is:
(A) 2 2
(B) 4 2
(C) 4 4
(D) 8 4
Q.18. For the circuit shown in figure, which statements are correct, initially it is assumed that Q0Q1 = 00
1.
It is a Mod-3, counter
2.
It is a Mod-4 counter
3.
After 334 clock pulses output will be zero
4.
After 339 clock pulses output will be zero
A.
1, 3, 4
B.
1, 4
C.
2, 3
D.
1, 3
Q.19. What is the value of output voltage for a given R - 2R ladder as shown in figure?
A.
1 Volt
B.
2 volt
C.
3 volt
D.
4 volt
Q.20. The 4 1 MUX is shown in figure what is the value of output f(x, y, z)
A.
xyz
B.
xyz
C.
xyz
D. x y z
Q.21. Consider the partial implementation of a 2-bit counter using T Flip-Flops following the sequence 02-3-1-0 as shown below. To complete the circuit input X should be
T2
MSB
CLK
A.
Q2
B.
Q2
T1
Q1
LSB
Q2 + Q1
(Q1 Q2 )
C.
D.
(Q1 Q2)
Q.22. In 8085, Microprocessor the contents of the accumulator, after the following instructions are
executed will become
XRA A
MVI B FOH
SUB B
A.
01 H
B.
0F H
C.
F0 H
D.
10 H
Q.23. Let A = 11111010 and B = 0000 1010 be two 8, bit 2s complement numbers, then their product in
2s complement is
A.
11000100
B.
10011100
C.
10100101
D.
11010101
Q.24. A Boolean function f(x, y, z) = xyz is to be implemented by use of universal gates only. If
complement inputs are not available then Minm no. of 2-input, universal gate required are.
A.
1
B.
2
C.
3
D.
4
Q.25. An R 2R ladder type DAC is shown in Figure, if a switch status is 0 then 0 volt is applied and if a
switch status is 1 then 5 volt is applied to the corresponding terminal of DAC.
R
R
v0
2R
2R
2R
S0
S1
2R
What is the step size of DAC in volt?
+5v
Q.26.
A
B
o/p
In the I.C. logic gate shown in figure. If threshold voltage VBE is o.75 volt and VCE (sat) = 0.2 V
calculate value of output voltage in volt. If VA = VB = 4.5 volt
5
Q.27. In a dual slope integrating type digital voltmeter the 1st integration is carried at for 10 periods of
supply frequency of 50Hz. If reference voltage used is 2 volt then total conversion time in second for
an output of 1 volt is?
Q.28. Consider the following data in respect of a certain digital gate:
IOH = 0.2 mA, IIH = 40 A
IOL = 16 mA, IIL = 1.6 mA
Symbols have their usual meaning, what is the value of its fan-out?
Q.29. What is the Minimum number of gates required to implement the Boolean function (AB+C) if we
have to use only 2-input NOR, gate
Common data for question 30&31:
Q0
Q1
Q2 Q3
A 4-bit shift register which shifts 1 bit to right at every clock pulse is initialized to values (1000) for Q0 Q1
Q2 Q3. The D input is derived from Q0, Q2 and Q3 through two XOR gates as shown in figure.
Q.30. After how many clock pulses Q0 Q1 Q2 Q3 will reappears as 1000.
(a) 4
(b) 6
(c) 7
(d) 8
Q.31. To what values should the shift register be initialized so that pattern (1001) occurs after the 1st clock
pulse??
(a) 0001
(b) 0010
(c) 1000
(d) 1001
Data for linked questions (32 33)
For a given MUX network as shown in fig.
21
MUX
f1
21
MUX
f2
21
MUX
33.
32.
The values of f1 and f2 are:

A.
x y z & x1y + yz + x1z respectively
B.
C.
x y z & xy yz zx respectively.
D.
xy + yz + zx &xy+yz+zx respectively.
Above circuit can acts as a:

A.
Full adder
B.
Full subtractor
C. Comparator
y z & x1 y yz x1 z respectively
D.
Parity checker
ECE-GATE 2014 Topic Test-Digital Solution

CD
AB 00
00
1. (B)
01
1
11
1
01
10
11
10
Y ABC AD BD CD
2. (D)
BC
A 00
01
11
10
A AB AC
POS will be 0, 2, 4,5

3. (B)
AND operation means Intersection of Min terms and OR operation means Union of Min terms
4. (D) 3Input EX OR
A
B
C
If in i/p even no of 1s are present then o/p = 0

If in i/p odd no of 1s are present then o/p will be 1.
Truth table
A B C A B C A B C A B C
0 0 0
0
0
0
0 1
0
1
1 1
0 0
0
1
0
1
0 1
B
0
0
1
0
1
1
0
1
0
1
0
CA
A
B
B
C A
B
1
C A B C A
1
B C
1
C
C
Conclusion for 3 input XOR:

A
A
B
C
B
C
(1)
A
A
B
B
C
(2)
(3)
Conclusion for 3 input XNOR:

A
A
B
B
C
5.
(C)
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3S3 S2 S1
S0
for n-bit propagation delay

= n 1 C S
T 3 5 10 25n second
Rate =
1
4 107 /second
25 109
6. (D) 2n 1 MUX it can express up to (n+1) variable (When inverter is given)

2n 1 1 MUX
n variable
For dual MUX.
2n 1 n 2 variable
If inverter is not given then there is a need of an extra 2:1 MUX
7. (D) S A B AB AB
C = AB
0
Cy=AB
21
But if inverter is not given then

1
0
B
21
0
1
B
So for Half adder there will be need of 3 MUX.

8. (B) 4 16, decoder
0
1
2
3
E
I2
I1
I0
I1
I0
I1
I0
6
416
I1
I0
11
I1
12
I0
15
15
0
416
7
I3
I2
I1
I0
8
416
15
9. (D)
1 1 0 1 1
1 1
0 1 1
1 for carry
110 1 1 1
C
10. (A)
A=B=0
Let C = 0
then D = 1, C = 0
Let C = 1
then D = 0, C = 1
Either C = 0 & D = 1 or C = 1 & D = 0.
11 (B) MOD 4-Jhonson Counter
Q1 Q0
D0 Q1 1
0
0
D1 Q0 0
335
83 4 3
4
, Q1 0
Q 0 1
D0 Q1 1, D1 Q0 1
Q0 1, Q1 1
D0 0, D1 1
After 3rd
Q0 0,
Q1 1
12. (D)
Take
JK Table
Y Y Q n 1
K Q n 1
0
0
0
1
1
Qn
1
1
0
1
Qn
0
0 0
0 1
1 0
Qn
0
1
1 1
Qn
J Y &K = X
10
13. (D)
Clock edge
O/P given
1
Mod 5 UP Counter:
O/P Taken
1 up Counter
VCC
VCCV
VCC
CC
J0
Q0
J1
Q1
J2
Q2
K0
Q0
CLK
K1
Q1
CLK
K2
Q2
CLK
iSB
Q2
Q1 Q 0
0
0
0
0
0
1
VCC
By OR Gate
Q0
CLK
CLK
CLK
MOD-5 Down counter:

VCC
1 1 1
1 1 0
1 0 1
1 0 0
VCC
7
6
5
4
0 1 1 2
0 1 0 2 101
Q0
Q2
Pr
Pr
VCC
0 0 1
0 0 0
Pr
VCC
J0
Q0
J1
Q1
J2
Q2
K0
Q0
Pr
K1
Q1
Pr
K2
Q2
Pr
14. Ans=9
X 54b 5.b1 4.b0 5b 4

x 7 x 49
5b 45 b 9
15. Ans=3
5b 4 49
00
01
11
00
01
11
10
1 1
10
11
Rule: Let n = variable of K-Map

2m = 8 m = 3.
number of terms in minimised group = nm
m no of bits for pairing.
n 8
2m 32 & m 5
n m 85 3
16. Ans=0
f A, B,C, D 4,5,8,12,13,14,15
CD
AB 00
00
01
01
11
10
11
10
It has 3 prime Implicates

1
A prime implicate is said to be EPI if it covers at least one minterm which is not covered by other prime
implicates. f A, B,C, D 0, 2,3, 4,5,7
00
0 1
01
11
1
1 1
10
1
This prime implicates is also known as cyclic prime implicates

17. (B)
Size of ROM = MN
M 2P : P Address Lines
A B
b3
b2
b1 b 0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
0
1
0
1
1
0
0
0
0
1
if P add. lines
ROM
Size of ROM = M N 2P N
N is the no of O/P bit
224
= 44 should be
b3 b2 b1 b0
12
size of ROM = 4 2
For 3 bit Square ROM Size of ROM must be = 8 4
For 4 bit Square ROM
18. (B) Q1
0
Q0
0
J0 = 1, K0 = 1, J1 = 0, K1 = 1 Q0 = 1, Q1 = 0
J0 = 1, K0 = 1, J1 = 1, K1 = 0 Q0 = 0, Q1 = 1
J0 = 0, K0 = 1, J1 = 0, K1 = 1 Q0 = 0, Q1 = 0
So 00 01 10 00 (MOD 3)
339/3=113 so after 339 clock cycles it will be reset to zero.
19. (A)
A value of output voltage Vo is given by
VR
b .2 N 1 bN 2 .2 N 2 ......... b0 .2
N N 1
2
4
1.21 1.0 volt
8
20. (D) f = x y x y x y xyz
By K Map f x y z
21. (D)
It is a synchronous counter and then use K-Map.
22. (D) XRAA
Accumulator has zero value
MVI B F0 B will have F0

SUB B
00 F0
00 + 10 = 10
23. (A)
A
11111010 (-6)
00001010 (+10)
A.B (-60) 11000100

24. (B)
x
y
f ( xy ) z
f
z
xy.z
13
25. Ans=0.625
R
2R
2R
V0
2R
S0
1
2R
For valid R2R ladder

Last should be R2R
S1
S2
0
0
Put here (100)
VR
b .2n 1 b n 2 .2n 2 .......b0 20
n n 1
2
VR Reference Voltage
V0
n = no of bits
L.S.B Step size or Resolution are same thing
V0
5
1.20 5 8 0.625V
23
26. Ans=0.2
5v
low
A
B
TTL always works as NAND Gate
Q1
Q2
High
Q3
V0 = VCC
for cut off
V0 = 2.0 low
27. Ans=0.1
In a dual slope integrating type digital voltmeter
T
vin vref where T1 is first integration time
T1
1
0.2sec
50
vin 1v, vref 2v
T1 10
T2
28. Ans=5
vin T1 1 0.2
0.1sec
vref
2
Fan-out =
0.2
5
0.04
14
16
10
1.6
Smaller of both Fan-in & Fan-out will be required Fan-out
Fan-in =
29.
Ans=3
f(A, B, C) = (A+C) (B+C)
30. B
31. B
32. A
33. B
15

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ECE-GATE 2014 Topic Test-Digital

Read the following papers instructions carefully:

For a Boolean function Y AB AC the POS form will be:

(D) (0, 2, 4,5)

(A) (0, 2,3, 4)

(B) (2,3, 4,5,6)

(C) (0,1, 2,3, 4,5,6)

Which of the following identity is not correct?

Q.14. Consider X (54)b where b is the base of the number system. If

X 7 then value of base b is?

What is the step size of DAC in volt?

The values of f1 and f2 are:

x y z & x1y + yz + x1z respectively

Above circuit can acts as a:

ECE-GATE 2014 Topic Test-Digital Solution

POS will be 0, 2, 4,5

If in i/p even no of 1s are present then o/p = 0

Conclusion for 3 input XOR:

Conclusion for 3 input XNOR:

for n-bit propagation delay

6. (D) 2n 1 MUX it can express up to (n+1) variable (When inverter is given)

For dual MUX.

But if inverter is not given then

So for Half adder there will be need of 3 MUX.

MOD-5 Down counter:

X 54b 5.b1 4.b0 5b 4

Rule: Let n = variable of K-Map

It has 3 prime Implicates

This prime implicates is also known as cyclic prime implicates

N is the no of O/P bit

A value of output voltage Vo is given by

It is a synchronous counter and then use K-Map.

22. (D) XRAA

Accumulator has zero value

MVI B F0 B will have F0

A.B (-60) 11000100

For valid R2R ladder

TTL always works as NAND Gate

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