BSNL TTA (JE) MICROPROCESSORS 200 EXPECTED

QUESTIONS (WWW.ALLEXAMREVIEW.COM) PART TWO

ANSWER KEY-Correct answer is indicated by symbol (V) in options.

1) On receiving an interrupt from an I/O device, the CPU

A [ ]) halts for a predetermined times
B [ ]) hands over the control of address bus and data bus to the interrupting device
C [ ]) branches off to the interrupt service routine immediately
D [v]) branches off to the interrupt serviceroutine after completion of the current instruction

2) The ALE line of 8085 microprocessor is used to

A [ ]) latch the output of an I/O instruction into an external latch
B [ ]) deactivate the chip-select signal from memory device
C [v]) latch the 8-bit of address lines AD0-AD7 into an external latch
D [ ]) find the interrupt enable status of the TRAP interrupt

3) The first operation performed in INTEL 8085 microprocessor after RESET is

A [v]) instruction fetch from 0000H
B [ ]) memory read from the location 0000H
C [ ]) instruction fetch from location 8000H
D [ ]) stack initialization

4) The 8085 microprocessor will enter into INA cycle after recognition of
A [ ]) any interrupt
B [ ]) TRAP only
C [v]) INTR only
D [ ]) RST 7.5,RST 6.5 & RST 5.5 only

5) Which of the following lists the interrupt in decreasing order of priority?

A [ ]) TRAP, RST 5.5, RST 6.5, RST 7.5, INTR
B [ ]) INTR, TRAP, RST 7.5, RST 6.5, RST 5.5
C [v]) TRAP, RST 7.5, RST 6.5, RST 5.5, INTR
D [ ]) RST 7.5, RST 6.5, RST 5.5, TRAP, INTR

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6) The interrupt vector address for TRAP is

A [ ]) 0000H
B [v]) 0024H
C [ ]) 0018H
D [ ]) 002CH

7) In order to reset the carry without affecting the accumulator content one has to use,
A [ ]) SUB A
B [ ]) XRA A
C [v]) ORA A
D [ ]) CMC

8) Maximum number of I/O that can be addressed by the INTEL 8085 is

A [ ]) 65536
B [ ]) 285
C [ ]) 512
D [v]) 256

9) The microprocessor may be made to exit from HALT state by asserting

A [ ]) RESTART
B [ ]) any of the five interrupt lines
C [ ]) READY line
D [v]) RESTART or any of the five interrupt lines or HOLD line

10) The 8085 microprocessor enters into bus idle machine cycle whenever
A [ ]) INTR interrupt is recognized
B [v]) RST 7.5 is recognized
C [ ]) DAD RP instruction is executed
D [ ]) none of the above

11) During OPCODE fetch the state of S0 and S1 is

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A [ ]) 00
B [ ]) 01
C [ ]) 10
D [v]) 11

12) After RESET 8255 will be in

A [v]) mode 0; all ports are input
B [ ]) mode 0; all ports are output
C [ ]) mode 2
D [ ]) unchanged condition

13) The microprocessor issues ALE during first T-state of

A [ ]) fetch cycle only
B [ ]) memory READ cycle only
C [ ]) memory WRITE cycle only
D [v]) every machine cycle

14) The content of the A15-A8 (higher order address lines) while executing IN 8-bit port
address instruction are
A [v]) same as the content of A7-A0
B [ ]) irrelevant
C [ ]) all bits reset (i.e. 00H)
D [ ]) all bits set (i.e. FFH)

15) Which one of the following ICs is used to interface keyboard and display?
A [ ]) 8251
B [v]) 8279
C [ ]) 8259
D [ ]) 8253

16) Which one of the following interrupt is only level triggering?

A [ ]) TRAP
B [ ]) RST 7.5

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C [v]) RST 6.5 and RST 5.5

D [ ]) RST 6.5

17) Which one of the following instruction may be used to clear the accumulator content
irrespective of its initial value?
A [ ]) CLR A
B [ ]) ORA A
C [v]) SUB A
D [ ]) MOV A, 00H

18) The execution of RST n instruction causes the stack pointer to

A [ ]) increment by two
B [v]) decrement by two
C [ ]) remain unaffected
D [ ]) none of the above

19) The stack is nothing but a set of

A [ ]) reserved ROM address space
B [v]) reserved RAM address space
C [ ]) reserved I/O address space
D [ ]) none of the above

20) S0 and S1 pins are used for

A [ ]) serial communication
B [v]) indicating the processors status
C [ ]) acknowledging the interrupt
D [ ]) none of the above

21) Pick out the matching pair

A [ ]) READY; RIM
B [ ]) HOLD; DMA
C [ ]) SID; SIM
D [v]) S0;S1;wait status

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22) In order to save accumulator value on the stack, which of the following instruction may
be used
A [v]) PUSH PSW
B [ ]) PUSH A
C [ ]) PUSH SP
D [ ]) POP PSW

23) A single instruction to clear the lower nibble of accumulator in 8085 language
assembly is
A [ ]) XRI 0FH
B [v]) ANI F0H
C [ ]) XRI FOH
D [ ]) ANI OFH

24) In a vector interrupt

A [v]) the branch address is assigned to a fixed location in memory
B [ ]) the interrupting source supplies the branch information to the processor through an
interrupt vector
C [ ]) the branch address is obtained from a register in the processor
D [ ]) none

25) A sequence of two registers that multiplies the content of DE register pair by two and
stores the result in HL register pair (in 8085 assembly language) is
A [ ]) XCHG & DAD B
B [ ]) XTHL & DAD H
C [ ]) PCHL & DAD D
D [v]) XCHG & DAD H

26) Identify the programmable interval timer from the following

A [ ]) 8252
B [v]) 8253
C [ ]) 8279
D [ ]) 8275

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27) Identify the communication interfacing device from the following

A [ ]) 8155
B [ ]) 8255
C [v]) 8251
D [ ]) 8257

28) Identify the programmable DMA controller from the following

A [v]) 8257
B [ ]) 8253
C [ ]) 8251
D [ ]) 8279

29) Identify the non-programmable interfacing device from the following

A [ ]) 8295
B [ ]) 8257
C [v]) 8212
D [ ]) 8255

30) The maximum number of seven segment displays that can be connected to 8279 is
A [ ]) 12
B [ ]) 16
C [v]) 18
D [ ]) 8

31) Using one 8259 IC is equivalent to providing BBBB. INTR pins on 8085
A [ ]) 16
B [ ]) 12
C [v]) 8
D [ ]) 18

32) Total number of modes the 8253 can work

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A [ ]) 4
B [v]) 6
C [ ]) 8
D [ ]) 12

33) Maximum of how many devices can be connected simultaneously to the

microprocessor via 8257 in DMA data transfer mode?
A [v]) 4
B [ ]) 6
C [ ]) 8
D [ ]) 10

34) A microprocessor with a 12-bit address bus will be able to access

A [ ]) 1 K bytes
B [v]) 4 K bytes
C [ ]) 8 K bytes
D [ ]) 10 K bytes

35) The frequency of the driving network connected between pins 1 and 2 of 8085
microprocessor is
A [v]) twice the desired frequency
B [ ]) equal to the desired frequency
C [ ]) four times the desired frequency
D [ ]) none of the above

36) A high on RESET OUT signifies that

A [ ]) all the registers of the CPU are being reset
B [ ]) all the registers and counters are being reset
C [v]) all the registers and counters are being reset and this signal can be used to reset external
support chip
D [ ]) processing can begin when this signal goes high

37) READY signal in 8085 is useful when the CPU communicates with

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A [v]) a slow peripheral device

B [ ]) a fast peripheral device
C [ ]) a DMA chip
D [ ]) a PPI

38) PSW stands for

A [ ]) accumulator contents
B [ ]) flag byte
C [v]) accumulator and flag register contents
D [ ]) none

39) DMA is used between

A [ ]) microprocessor and I/O
B [ ]) microprocessor and memory
C [v]) memory and I/O
D [ ]) none

40) Temporary registers in 8085 are

A [ ]) B and C
B [ ]) D and E
C [ ]) H and L
D [v]) W and Z

41) Register pair used to indicate memory

A [ ]) B and C
B [ ]) D and E
C [v]) H and L
D [ ]) W and Z

42) Total numbers of output pins in 8085 microprocessor are

A [ ]) 13
B [v]) 27

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C [ ]) 30
D [ ]) 40

43) Basic steps of execution of an instruction is

A [ ]) fetch execute decode
B [ ]) decode fetch execute
C [ ]) execute fetch decode
D [v]) fetch decode execute

44) When RET instruction is executed by any subroutine then

A [v]) the top of the stack will be popped out and assigned to the PC.
B [ ]) without any operation, the calling program would resume from instruction immediately
following the call instruction.
C [ ]) the PC will be incremented after the execution of the instruction.
D [ ]) without any operation, the calling program would resume from instruction immediately
following the call instruction and also the PC will be incremented after the execution of the
instruction.

45) Which of the following instruction is not possible in 8085?

A [ ]) POP PSW
B [ ]) POP B
C [ ]) POP D
D [v]) POP 30 H

46) How many T-states are required for execution of OUT 80H instruction?
A [v]) 10
B [ ]) 13
C [ ]) 16
D [ ]) 7

47) How many machine cycles are required for execution of IN 30H instruction
A [v]) 3
B [ ]) 4

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C [ ]) 5
D [ ]) 6

48) Length of the instruction POP D is

A [v]) 1byte
B [ ]) 2byte
C [ ]) 3byte
D [ ]) 4byte

49) While INX B instruction execute,

A [ ]) only carry flag will be affected
B [ ]) all flags will be affected
C [ ]) only carry and zero flags will be affected
D [v]) no flags will be affected

50) While STC instruction execute,

A [v]) only carry flag will be affected
B [ ]) all flags will be affected
C [ ]) only carry and zero flags will be affected
D [ ]) no flags will be affected

51) Which instruction is required to rotate the content of accumulator one bit right along
with carry?
A [ ]) RLC
B [ ]) RAL
C [ ]) RRC
D [v]) RAR

52) In a microprocessor system with memory mapped I/O

A [ ]) Stops execution of instructions
B [v]) Acknowledge interrupt and branches of subroutine
C [ ]) Acknowledges interrupt and continues
D [ ]) Acknowledge interrupt and waits for the next instruction from the interrupting device

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53) The software used to drive microprocessor-based systems is called:

A [v]) assembly language
B [ ]) firmware
C [ ]) machine language code
D [ ]) BASIC interpreter instructions

54) The ________ ensures that only one IC is active at a time to avoid a bus conflict caused
by two ICs writing different data to the same bus.
A [ ]) control bus
B [ ]) control instructions
C [v]) address decoder
D [ ]) CPU

55) When referring to instruction words, a mnemonic is

A [ ]) a short abbreviation for the operand address
B [v]) a short abbreviation for the operation to be performed
C [ ]) a short abbreviation for the data word stored at the operand address
D [ ]) shorthand for machine language

56) The technique of assigning a memory address to each I/O device in the computer
system is called
A [v]) memory-mapped I/O
B [ ]) ported I/O
C [ ]) dedicated I/O
D [ ]) wired I/O

57) What type of circuit is used at the interface point of an output port?
A [ ]) decoder
B [v]) latch
C [ ]) tristate buffer
D [ ]) none of the above

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58) I/O mapped systems identify their input/output devices by giving them a(n) ________
A [v]) 8-bit port number
B [ ]) 16-bit port number
C [ ]) 8-bit buffer number
D [ ]) 8-bit instruction

59) What type of circuit is used at the interface point of an input port?
A [ ]) decoder
B [ ]) latch
C [v]) tristate buffer
D [ ]) none of the above

60) The 8085A is a(n)

A [ ]) 16-bit parallel CPU
B [ ]) 8-bit serial CPU
C [v]) 8-bit parallel CPU
D [ ]) none of the above

61) Because microprocessor CPUs do not understand mnemonics as they are, they have to
be converted to _______
A [ ]) hexadecimal machine code
B [v]) binary machine code
C [ ]) assembly language
D [ ]) all of the above

62) A register in the microprocessor that keeps track of the answer or results of any
arithmetic or logic operation is the
A [ ]) stack pointer
B [ ]) program counter
C [ ]) instruction pointer
D [v]) accumulator

63) What is the difference between a mnemonic code and machine code?

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A [ ]) There is no difference.
B [v]) Machine codes are in binary, mnemonic codes are in shorthand English
C [ ]) Machine codes are in shorthand English, mnemonic codes are in binary.
D [ ]) none of these

64) Which of the following buses is primarily used to carry signals that direct other ICs to
find out what type of operation is being performed?
A [ ]) data bus
B [v]) control bus
C [ ]) address bus
D [ ]) address decoder bus

65) What kind of computer program is used to convert mnemonic code to machine code?
A [ ]) debug
B [v]) assembler
C [ ]) C++
D [ ]) Fortran

66) Which of the following are the three basic sections of a microprocessor unit?
A [ ]) operand, register, and arithmetic/logic unit (ALU)
B [v]) control and timing, register, and arithmetic/logic unit (ALU)
C [ ]) control and timing, register, and memory
D [ ]) arithmetic/logic unit (ALU), memory, and input/output

67) Which of the following can be accessed only sequentially?

A [ ]) Floppy disk
B [ ]) Hard disk
C [v]) Magnetic tape
D [ ]) ROM

68) To multiply a number by 8 in 8085 we have to use RAL instruction

A [ ]) once

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B [ ]) twice
C [v]) thrice
D [ ]) four times

69) The interface chip for 8086 and 16 bit ADC is

A [ ]) 8259
B [v]) 8255
C [ ]) 8253
D [ ]) 8251

70) EEPROM permits

A [ ]) read operation only
B [ ]) read and byte erase operations
C [ ]) read, byte erase and byte write operations
D [v]) read, byte erase, byte write and chip erase operations

71) Which has volatile memory?

A [ ]) Magnetic tape
B [v]) RAM
C [ ]) Diskette
D [ ]) Hard disk

72) Contents of RAM cannot be altered.

A [ ]) True
B [v]) False

73) Assertion (A): Microprocessor 8085 can address 65536 memory locations.
Reason (R): Microprocessor 8085 has 16 address lines.
A [v]) Both A and R are correct and R is correct explanation of A
B [ ]) Both A and R are correct but R is not correct explanation of A
C [ ]) A is correct R is wrong
D [ ]) A is wrong R is correct

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74) Assertion (A): Dynamic RAM needs refreshing.

Reason (R): Capacitors tend to loose charge
A [v]) Both A and R are correct and R is correct explanation of A
B [ ]) Both A and R are correct but R is not correct explanation of A
C [ ]) A is wrong R is correct
D [ ]) A is correct R is wrong

75) A microprocessor is generally

A [ ]) single chip SSI
B [ ]) single chip MSI
C [v]) single chip LSI
D [ ]) any of the above

76) A nibble corresponds to

A [ ]) 2 successive bits of data
B [v]) 4 successive bits of data
C [ ]) 8 successive bits of data
D [ ]) 16 successive bits of data

77) When we use RRC instruction once in 8085, the number is

A [ ]) multiplied by 2
B [v]) divided by 2
C [ ]) multiplied by 4
D [ ]) divided by 4

78) Which of the following is not treated as hexadecimal constant by assembler in 8085?
A [ ]) 64 H
B [ ]) 5 AFH
C [v]) AFH
D [ ]) OCFH

79) In 8085, which instructions are useful for writing and using subroutines?

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A [ ]) CALL
B [ ]) RET
C [v]) CALL and RET
D [ ]) none of the above

80) The memory segment registers in 8086 are denoted by

A [ ]) AS, BS, CS, DS
B [ ]) BS, CS, SS, ES
C [v]) CS, DS, SS, ES
D [ ]) DS, ES, FS, SS

81) The signal in 8086 are in minimum mode when

A [v]) MN / Mx pin is tied to Vcc
B [ ]) MN / Mx pin is grounded
C [ ]) MN / MX pin is left open
D [ ]) none of the above

82) Which of the following instruction modes does not exist in microprocessor 8085?
A [v]) instrict
B [ ]) Register
C [ ]) Immediate
D [ ]) Implied/implicit/Inherent

83) Read the following statements as regards register pairs in microprocessor 8085
1.B represents B, C pair with B as high order register and C as low order register.
2.D represents D, E pair with D as high order register and E as low order register.
3. H represents H, L pair with H as high order register and L as low order register.
Which of the above statements are correct?
A [v]) All
B [ ]) 1 and 3
C [ ]) 1 and 2
D [ ]) 2 and 3 only

84) The number of primitive string operations in 8086 is

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A [ ]) 3
B [ ]) 4
C [v]) 5
D [ ]) 6

85) Which of these are 16 bit microprocessors?

A [ ]) 80286
B [ ]) MC68000
C [ ]) Z8000
D [v]) all

86) The number of registers and flags in 8086 are

A [ ]) 13 and 5 respectively
B [ ]) 9 and 5 respectively
C [v]) 13 and 9 respectively
D [ ]) 9 and 9 respectively

87) Which of the following buses does not exist in 8085?

A [ ]) Data bus
B [ ]) Address bus
C [ ]) Control bus
D [v]) Exchange bus

88) System bus is the communication channel between microprocessor and peripherals.
A (V) TRUE
B ( ) FALSE

89) Assertion (A): In 8085 WR and RD signals are active high.

Reason (R): LOW WR means write operation and low RD means read operation.
A [ ]) Both A and R are correct and R is correct explanation of A
B [ ]) Both A and R are correct but R is not correct explanation of A
C [v]) A is wrong R is correct

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90) Assertion (A): In direct addressing the address of operand is specified in the
instruction.
Reason (R): Direct addressing is also called absolute addressing.
A [ ]) Both A and R are correct and R is correct explanation of A
B [v]) Both A and R are correct but R is not correct explanation of A @
C [ ]) A is correct R is wrong
D [ ]) A is wrong R is correct

91) In a microprocessor the clock signal

A [ ]) is always generated internally
B [ ]) is always supplied externally
C [v]) may be generated internally or supplied externally
D [ ]) is mostly supplied externally

92) In 8085
A [v]) the upper 8 address bits appear on address bus and lower 8 bits on address data bus
B [ ]) the lower 8 address bits appear on address bus and the upper 8 address bits appear on
address data bus
C [ ]) either upper or lower 8 address bits may appear at address bus

93) Which of the following methods does not cause any reduction in instruction length?
A [ ]) Using program counter
B [ ]) Common source and destination address
C [ ]) Implicit source and destination address
D [v]) Machine language programming

94) In 8085 the term 'absolute addressing' means

A [v]) Direct addressing
B [ ]) Immediate addressing
C [ ]) Register addressing
D [ ]) Register indirect addressing

95) Which of the following statements is written in plain English in 8085?

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A [v]) Data definition

B [ ]) Assignment
C [ ]) Conditional
D [ ]) Repetitive

96) In a microprocessor
A [ ]) one machine cycle is equal to one clock cycle
B [ ]) one clock cycle consists of several machine cycles
C [v]) one machine cycle consists of several clock cycles
D [ ]) one machine cycle is always less than one clock cycle

97) Which addressing mode is suitable only for these instructions in which there is only
one operand?
A [v]) Implicit
B [ ]) Register
C [ ]) Direct
D [ ]) Immediate

98) In 8085 microprocessor with memory mapped I/O which of the following is true?
A [v]) I/O devices have 16 bit addresses
B [ ]) I/O devices are accessed during IN and OUT instructions
C [ ]) There can be a maximum of 256 input and 256 output devices
D [ ]) Logic operations can not be performed

99) The signals in 8086 are classified into

A [v]) minimum mode and maximum mode
B [ ]) decrement mode and increment mode
C [ ]) low mode and high mode
D [ ]) none of the above

100) Internally the two distinct units of 8086 are called

A [v]) bus interface unit and execution unit
B [ ]) command unit and follow unit

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C [ ]) master unit and slave unit

101) In 8085, which of the following is an 8 bit register?

A [v]) A
B [ ]) SP
C [ ]) PC
D [ ]) ALL

102) In 8086 the word address is

A [v]) the address of the least significant byte
B [ ]) the address of most significant byte
C [ ]) either (1) or (2) depending on the word
D [ ]) neither (1) nor (2)

103) The general purpose register code for accumulator in 8085 is

A [v]) 111
B [ ]) 000
C [ ]) 001
D [ ]) 1111

104) In 8085, high level on INTR line can be recognised only if

A [ ]) TRAP and RST lines are high
B [v]) TRAP and RST lines are not high
C [ ]) TRAP line is high but not RST line
D [ ]) RST line is high but not TRAP line

105) For an accurate clock period in 8085 it is preferable to use

A [v]) Crystal
B [ ]) Crystal or LC resonant circuit
C [ ]) Crystal or RC circuit
D [ ]) LC or RC circuit

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106) The memory hierarchy in microprocessor based system is

A [v]) register, cache, primary, mass, off line back up
B [ ]) cache, register, primary, mass, off line back up
C [ ]) cache, register, mass, primary, off line back up
D [ ]) register, cache, mass, primary, off line back up

107) When a peripheral device is not ready for data transfer it will send to the
microprocessor a
A [v]) low READY bit
B [ ]) high READY bit
C [ ]) low or high READY bit depending on whether input or output is activated
D [ ]) none of the above

108) In 8085 the address space size is

A [ ]) 64 kbits
B [v]) 64 k bytes
C [ ]) 32 kbits
D [ ]) 16 k bytes

109) In 8085 the data is stored in the stack on

A [ ]) First in First Out basis
B [v]) Last in First Out basis
C [ ]) First in Last Out basis
D [ ]) Last in Last Out basis

110) In 8085 the instruction MOV A, M is an example of

A [ ]) Direct addressing
B [ ]) Immediate addressing
C [ ]) Register addressing
D [v]) Register indirect addressing

111) In 8086 the flag which enables or disables external interrupts is

A [v]) IF

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B [ ]) DF
C [ ]) TF
D [ ]) CF

112) The chip 8257 is a

A [ ]) programmable interrupt controller
B [v]) programmable DMA controller
C [ ]) programmable peripheral interface
D [ ]) none of the above

113) In memory mapped I/O means that

A [ ]) an input or output device is treated by the microprocessor as one memory location
B [ ]) input or output devices are treated as distinct
C [ ]) an address on the address bus may refer either to a memory location or to an I/O device
D [ ]) none of the above

114) In 8085, the pins for SID and SOD are

A [ ]) 4 and 5 respectively
B [v]) 5 and 4 respectively
C [ ]) 3 and 4 respectively
D [ ]) 4 and 3 respectively

115) In 8085, the pairing of registers B, C, D, E, H, L is

A [v]) B - C, D - E, H - L
B [ ]) B - D, C - E, H - L
C [ ])

B - C, D - L, H - E

D [ ]) B - H, D - E, C - L

116) In Intel 8085, the integer range per word length is

A [v]) -128 to 127
B [ ]) -127 and 128
C [ ]) -64 and 63

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D [ ]) -63 and 64

117) In 8085 the pins for + 5 V input and ground are

A [ ]) 20 and 40 respectively
B [v]) 40 and 20 respectively
C [ ]) 1 and 2 respectively
D [ ]) 1 and 1 respectively

118) In 8086 the number of lines on which data and address is multiplexed is
A [ ]) 8
B [ ]) 16
C [v]) 20
D [ ]) 32

119) An instruction using immediate addressing mode in 8085 is

A [ ]) 2 bytes long
B [ ]) 3 bytes long
C [ ]) 2 or 3 bytes long
D [v]) 1 or 2 or 3 bytes long

120) DS directive in 8085

A [ ]) forces the assembler to reserve one byte of memory
B [ ]) forces the assembler to reserve a specified number of bytes in the memory
C [v]) forces the assembler to reserve a specified number of consecutive bytes in the memory
D [ ]) none of the above

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