Beruflich Dokumente
Kultur Dokumente
(Synchronous)
Sequential Circuits
J.J. Shann
Contents
6-1
6-2
6-3
6-6
6-4
6-5
6-7
Sequential circuit:
E.g.s:
Classification:
is syn seq ckts that use clock pulses in the inputs of storage elements
has a master-clock generator to generate a periodic train of clock
pulses
The clock pulses are distributed throughout the system.
Storage elements are affected only w/ the arrival of each pulse.
(Optional)
Flip-flops
Clock pulses
6-2 Latches
Latches:
A. SR and SR Latches
SR latch
SR latch
SR latch w/ control input
SR Latch
Async
Seq Ckt
Useful states:
Q+
N o ch a n g e (Q + = Q )
Set state: Q = 1, Q = 0
R eset (Q + = 0 )
Reset state: Q = 0, Q = 1
S et (Q + = 1 )
In d eterm in a te
Undefined states: Q = Q
Q + : n ex t sta te o f Q
(Case 1)
0 0
0
0
S R
Q Q
Q+ Q+
0 0
0 1
1 0
0
1
1 9
0 9
0 1
0 1
1 0
0
0
1
1
1 0
0 1
1 0
1
1
0
0
1 1
0 1
1 0
0
0
0
0
S R
1 1
Q+
No change (Q+ = Q)
Reset (Q+ = 0)
Set (Q+ = 1)
Indeterminate
(Case 2)
1
0 0
0
0
S R
Q Q
Q+ Q+
0 0
0 1
1 0
0
1
1
0
0 1
0 1
1 0
0
0
1 9
1
1 0
0 1
1 0
1
1
0
0 9
1 1
0 1
1 0
0
0
0
0
S R
1 1
Q+
No change (Q+ = Q)
Reset (Q+ = 0)
Set (Q+ = 1)
Indeterminate
(Case 3)
1 0 0 0
0 0 1
1 0 0
0
S R
Q Q
Q+ Q+
0 0
0 1
1 0
0
1
1
0
0 1
0 1
1 0
0
0
1
1 9
1 0
0 1
1 0
1
1
0 9
0
1 1
0 1
1 0
0
0
0
0
S R
0 0 1 1
Q+
No change (Q+ = Q)
Reset (Q+ = 0)
Set (Q+ = 1)
Indeterminate
(Case 4)
0 0 0
1 0
0 0
1
1 0 0
S R
Q Q
Q+ Q+
0 0
0 1
1 0
0
1
1
0
0 1
0 1
1 0
0
0
1
1
1 0
0 1
1 0
1
1
0
0
1 1
0 1
1 0
0
0
0
0
Q+
N o ch a n g e (Q + = Q )
R eset (Q + = 0 )
S et (Q + = 1 )
In d eterm in a te
Q + : n ex t sta te o f Q
(Case 4+)
0 1 0
0 1
0 1
0
S R
Q Q
Q+ Q+
0 0
0 1
1 0
0
1
1
0
0 1
0 1
1 0
0
0
1
1
1 0
0 1
1 0
1
1
0
0
1 1
0 1
1 0
0
0
0
0
S R
0 1 0
Q+
No change (Q+ = Q)
Reset (Q+ = 0)
Set (Q+ = 1)
Indeterminate
Summary:
S R
Q Q
Q+ Q+
0 0
0 1
1 0
0
1
1
0
0 1
0 1
1 0
0
0
1
1
1 0
0 1
1 0
1
1
0
0
1 1
0 1
1 0
0
0
0
0
S R
Q = ( R + Q )
+
Q + = ( S + Q)
Q+
No change (Q+ = Q)
Reset (Q+ = 0)
Set (Q+ = 1)
Indeterminate
Q+
N o ch a n g e (Q + = Q )
R eset (Q + = 0 )
S et (Q + = 1 )
In d eterm in a te
Q + : n ex t sta te o f Q
S R Latch
Q+
N o ch a n g e (Q + = Q )
R eset (Q + = 0 )
S et (Q + = 1 )
In d eter m in a te
S R
Q Q
Q+ Q+
1 1
0 1
1 0
0
1
1
0
0 1
0 1
1 0
0
0
1
1
1 0
0 1
1 0
1
1
0
0
0 0
0 1
1 0
1
1
1
1
Q+
Q + = ( S Q )
N o ch a n g e (Q + = Q )
R eset (Q + = 0 )
Q = ( R Q)
S et (Q + = 1 )
In d eter m in a te
enable signal
S = R =1
B. D Latch
D latch
D latch w/ transmission gates
D Latch
C D
C S R
Q+
0 X
0 X X
1 0
1 0 1 0 (Reset)
1 1
1 1 0 1 (Set)
Q (No change)
1
D
0
D+
6-3 Flip-Flops
Flip-flop:
responses only to a transition of a triggering input called the
clock.
Positive-edge trigger: 0 1
Negative-edge trigger: 1 0
Latch Flip-flop:
1. Master-slave flip-flop: pulse-triggered f-f
Employ two latches in a special configuration that
isolates the output of the flip-flop from being affected
while its input is changing.
2. Edge-triggered flip-flop:
Produce a flip-flop that triggers only during a signal
transition, and is disabled during the rest of the clock
pulse duration.
A. Master-Slave Flip-Flops
SR master-slave flip-flop:
Master disable
* Q may change
only during the
negative edge
of the clock.
Logic simulation of
an SR master-slave
flip-flop:
Master-slave D f-f
Negative
edge-triggered
D flip-flop
Positive
edge-triggered
D flip-flop
B. Edge-Triggered Flip-Flop
Negative
edge-triggered
D flip-flop
Positive
edge-triggered
D flip-flop
D-Type Positive-Edge-Triggered
Flip-Flop (p.6-27~6-32)
S
1
No change
0
1
No change
1
D
D
D
D
Timing
Setup time: G1 + G4
the time interval b/t the trigger edge and the stabilization
of the output to a new state
J.J. Shann 6-38
Setup time: G1 + G4
D
D
D
J.J. Shann 6-39
the minimum time for which the D input must not change
after the application of the positive transition of the clock
D
D
the time interval b/t the trigger edge and the stabilization
of the output to a new state
D
D
D
D
C. Flip-Flop Timing
Clock pulse
width, tw
Setup time, ts
Hold time, th
Propagation
delay times,
tPHL, tPLH, tpd
* Assumption:
All flip-flops are of the positiveedge-triggered type, unless
otherwise indicated.
J.J. Shann 6-43
E. Direct Inputs
flops is unknown.
The direct inputs are useful for bringing all flip-flops in the
system to a known starting state prior to the clocked operation.
0
1
E.g.: ()
D flip-flop w/
asynchronous
reset
*
*
1
*
* Active LOW
direct set
(active LOW)
direct reset
(active LOW)
J.J. Shann 6-46
JK flip-flop
T flip-flop
J-K Flip-Flop
SR flip-flop
JK flip-flop
S
0
R
0
Q+
Q
J
0
K
0
Q+
Q
0
1
1
1
0
1
0
1
Indeterminate
0
1
1
1
0
1
0
1
Q
JK flip-flop
Q+
J
0
K
0
Q+
Q
0
1
1
1
0
1
0
1
Q+ = JQ + KQ
J.J. Shann 6-49
Q+
0
0
1
1
0
1
0
1
Q
0
1
Q
0
1
T Flip-Flop
J
0
0
1
1
K
0
1
0
1
Q+
Q
0
1
Q
Q+ = JQ + KQ
J=K
T
0
1
Q+
Q
From D flip-flop:
Q+ = D = TQ + TQ
Q+ = TQ + TQ
J.J. Shann 6-51
(1)
(1)
(2)
Analysis procedure:
Flip-Flop Characteristic Equation
1
Circuit
(sync seq)
Flip-flop
input
Equations
Output
equations
Next
state
equations
State
table
(Transition
table)
State
diagram
A. Analysis w/ D Flip-Flops
E.g. 1:
<Analysis>
1. Flip-flop input equations & Output equations:
DA = AX + BX
DB = AX
Y = (A + B) X
B(t + 1) = DB = A X
comb. ckt.
J.J. Shann 6-56
3. State table:
Next state equations:
A(t + 1) = AX + BX
B(t + 1) = A X
Output equations:
Y = AX + B X
(One-dimensional)
State table
Two-dimensional
state table
input/output
X/Y
4. State diagram:
E.g. 2:
3. State table:
A+ = A X Y
Z=A
4. State diagram:
A/Z
state/output
Analysis w/ JK Flip-Flops
Flip-Flop Characteristic Equation
1
Circuit
(sync seq)
Flip-flop
input
Equations
Next
state
equations
State
table
(Transition
table)
State
diagram
Output
equations
Example:
3. State table:
A+ = A B + A B + A x
B+ = B x + A B x + A B x
4. State diagram
Analysis w/ T Flip-Flops
Flip-Flop Characteristic Equation
1
Circuit
(sync seq)
Flip-flop
input
Equations
Next
state
equations
State
table
(Transition
table)
State
diagram
Output
equations
Example:
TA A + TA A
A B + A x + A B x
TB B + TB B
xB
J.J. Shann 6-69
3. State table:
A+ = A B + A x + A B x
B+ = x B
y = AB
4. State diagram
Mealy model:
Combinational
Logic for
Outputs and
Next State
State Register
Zk
Outputs
Clock
State
Feedback
E.g. 1:
J.J. Shann 6-72
Xi
Inputs
State Register
Zk
Outputs
Combinational
Logic for
Outputs and
Next State
Clock
State
Feedback
E.g. 1:
Moore model:
Comb.
Logic for
Outputs
Combinational
Logic for
Next State
(Flip-flop
Inputs)
Zk
Outputs
Clock
state
feedback
E.g. 2:
J.J. Shann 6-74
State
Register
Xi
Inputs
Comb.
Logic for
Outputs
Combinational
Logic for
Next State
(Flip-flop
Inputs)
Zk
Outputs
Clock
E.g. 2:
state
feedback
Comparison:
Moore model:
The outputs of the ckt are synchronized w/ the clock.
Mealy model:
The outputs may change if the inputs change during the clock
cycle.
Example 6-1:
Suppose that all f-fs used are the same and have tpd = 0.2 ns
and ts = 0.1 ns. Then the longest path beginning and
ending w/ a f-f will be the path w/ the largest tpd,COMB.
Further, suppose that the largest tpd,COMB is 1.3 ns and that
tp has been set to 1.5 ns.
<Ans.>
Discussion
Hold time: th
(clock skew)
D. Simulation
Function simulation
Timing simulation
Simulation timing:
Design procedure:
1. Specification: Write a specification for the ckt.
2. Formulation: Obtain either a state diagram or state
table from the statement of the problem.
* State reduction: Reduce the # of states if necessary.
3. State assignment: Assign binary codes to the states
and obtain the binary-coded state table.
4. Flip-flop input equation determination: Select the
flip-flop type or types. Derive the flip-flop input
equations from the next-state entries in the encoded
state table.
5. Output equation determination: Derive output
equations from the output entries in the state table.
J.J. Shann 6-87
A.
State
diagram
Functional
description
B.
State
table
Minimal
state
table
C.
State
assignment
D.
Binary-coded
state
table
Flip-Flop
input
equations
&
Output
equations
E.
Circuit
F.
Verify
(Used/Unused
states)
Initial State
Initial state:
Example 6-2
Problem description:
Recognize the occurrence of the sequence of bits 1101 on input
1101
Seq Recognizer
1101
Seq Recognizer
State diagram:
1/0
0/0
1/0
A
Init
1/0
1/0
0/0
11
0/0
110
0/0
1/1
1101
0/0
X/Z
State B = State E
J.J. Shann 6-93
State table:
Example
Input
x
0
1
0
1
0
1
0
1
Next
state
Output
y
S0
S1
S0
S2
S0
S3
S0
SJ.J.
3 Shann
0
0
0
0
0
0
1
1
6-96
Example 6-3
BCD-to-excess-3
decoder
LSB
MSB
LSB
MSB
B1 B2 B3 B4
0
1
2
3
4
5
6
7
8
9
B1 B2 B3 B4
State diagram:
B1 B2 B3 B4
State diagram:
Init
0/1
1/0
B1=0
0/0
B3=0
0/0
B1=1
0/1
1/0
0/0
1/1
B2=0
B2=1
B2=0
B2=1
1/1 0/1
B3=1
1/1 0/0
B3=0
0/0
1/0
0/1
B3=1
B3=0
0/1 0/0
1/0
B3=1
1/1
0/1
0/1
1/0
B3=0
B3=1
0/0
0/1
Init
J.J. Shann 6-99
State reduction:
Goal:
<Ans.>
State diagram:
0/0
S0
0/0
1/0
S1
S2
0/0
1/0
0/0
1/0
S3
S4
S5
S6
1/0 0/1
1/0
0/0
S0
1/0
0/1
1/0
State table:
Input Sequence
Reset
0
1
00
01
10
11
Next State
Present State X=0 X =1
S0
S2
S1
S1
S3
S4
S2
S5
S6
S3
S0
S0
S4
S0
S0
S5
S0
S0
S6
S0
S0
Next State
Present State X =0 X =1
S1'
S'1
S0
S1'
S3'
S'4
S3'
S0
S0
S4'
S0
S0
Output
X =0 X=1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
Output
X =0 X =1
0
0
0
0
0
0
1
0
J.J. Shann 6-106
Input Sequence
Reset
(S1, S2)
0 or 1
(S3, S5) 00 or 10
(S4, S6) 01 or 11
Next State
Present State X =0 X =1
S1'
S'1
S0
S1'
S3'
S'4
S3'
S0
S0
S4'
S0
S0
Output
X =0 X =1
0
0
0
0
0
0
1
0
S0
0,1/0
S1 = S2
0/0
1/0
S3 = S5
0/0
S4 = S6
1/0 0/1
1/0
S0
J.J. Shann 6-107
Next State
Present State X=0 X=1 Output
S0 S1
S0
0
1
S1
S1 S2
0
S2
S2 S1
No
Noway
wayto
tocombine
combinestates
statesS0
S0and
andS2
S2
based
basedon
onNext
NextState
StateCriterion!
Criterion!
Next States
Under all
Input
Combinations
S0
S1
S1
S2
S2
S3
S3
S4
S4
S5
S5
S6
S6
S0
S1
S2
S3
S4
S5
S6
S0
S1
S2
S3
S4
S5
Implication Chart
J.J. Shann 6-109
Eg.:
S0 transitions to S1 on 0, S2 on 1;
S1 transitions to S3 on 0, S4 on 1;
S1
S1-S3
S2-S4
S0
J.J. Shann 6-110
<Ans.>
State table:
Input Sequence
Reset
0
1
00
01
10
11
Next State
Present State X=0 X =1
S0
S2
S1
S1
S3
S4
S2
S5
S6
S3
S0
S0
S4
S0
S0
S5
S0
S0
S6
S0
S0
Output
X =0 X=1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
J.J. Shann 6-111
Starting
Present State
Input Sequence
S0
Reset
S1
0
S2
1
S3
00
S4
01
S5
10
S6
11
implication chart:
Next State
X=0 X =1
S1
S2
S3
S4
S5
S6
S0
S0
S0
S0
S0
S0
S0
S0
Output
X =0 X=1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
S2 and S4
have different
I/O behavior
S1
S1-S3
S2-S4
S2
S1-S5 S3-S5
S2-S6 S4-S6
S3
S1 and S0 cannot
be combined
S4
S5
S6
S0
S1
S2
S3
S4
S5
J.J. Shann 6-112
S1-S3
S2-S4
S1
S2
S1-S5 S3-S5
S2-S6 S4-S6
S2
S3
S3
S4
S4
S5
S3-S5
S4-S6
S6
S0
S1
S2
S3
S0-S0
S0-S0
S5
S4
S0-S0
S0-S0
S6
S5
S0
S1
S2
S3
S4
S5
S1
S3-S5
S4-S6
S2
S3
S4
S0-S0
S0-S0
S5
S0-S0
S0-S0
S6
S0
S1
S2
S3
S4
S5
Next State
Present State X =0 X =1
S1'
S0
S'1
S1'
S3'
S'4
S3'
S0
S0
S4'
S0
S0
Output
X =0 X =1
0
0
0
0
0
0
1
0
J.J. Shann 6-114
Next State
X =0 X =1
S1
S0
S1
S2
S2
S1
Output
0
1
0
No
Noway
wayto
tocombine
combinestates
statesS0
S0and
andS2
S2
based
basedon
onRow
Rowmatching
matchingmethod!
method!
Implication
ImplicationChart
Chart
S1
S2 S0 -S2
S1 -S1
S0 is equivalent to S2
since nothing contradicts this assertion!
S0
S1
J.J. Shann 6-115
10
00
S0
[1]
S1
[0]
01
11
10
01
00
S2
[1]
01
00
S3
[0]
01
10
10
11
11
10
00
01
S4
[1]
11
00
10
11
01
Present
State
S0
S1
S2
S3
S4
S5
00
S0
S0
S1
S1
S0
S1
Next State
01 10
S1 S2
S3 S1
S3 S2
S0 S4
S1 S2
S4 S0
Output
11
S3
S5
S4
S5
S5
S5
1
0
1
0
1
0
S5
[0]
11
State Diagram
J.J. Shann 6-116
Present
State
S0
S1
S2
S3
S4
S5
S1
S2
S0-S1
S1-S3
S2-S2
S3-S4
S4
S3
S0-S0
S1-S1
S2-S2
S3-S5
S0
Present
State
S'0
S1
S2
S'3
S1-S0
S3-S1
S2-S2
S4-S5
S0-S1
S3-S4
S1-S0
S5-S5
S5
00
S0
S0
S1
S1
S0
S1
Next State
Output
01 10 11
S1 S2 S3
1
S3 S1 S5
0
S3 S2 S4
1
S0 S4 S5
0
S1 S2 S5
1
S4 S0 S5
0
S1
S1-S1
S0-S4
S4-S0
S5-S5
S2
S3
Next State
00 01 10
S0' S1 S2
S0' S3' S1
S1 S3' S2
S1 S'0 S'0
Output
11
S3'
S3'
S0'
S'3
1
0
1
0
Implication Chart
J.J. Shann 6-117
C. State Assignment ()
State Assignment
HY
01
01
10
10
11
11
00
00
10
10
11
11
FG
10
11
01
11
01
10
10
11
00
11
00
10
FY
11
10
11
01
10
01
11
10
11
00
10
00
HG
10
10
10
10
10
10
11
11
11
11
11
11
HY
00
00
01
01
11
11
00
00
01
01
10
10
FG
01
11
00
11
00
01
01
10
00
10
00
01
FY
11
01
11
00
01
00
10
01
10
00
01
00
State Map
State Maps: similar in concept to K-maps
S0
S1
Assignment
State Name Q2 Q 1 Q0
S0
0 0 0
1 0 1
S1
1 1 1
S2
0 1 0
S3
0 1 1
S4
S2
S3
Assignment
Assignment
Q1 Q 0
Q 00 01
2
0 S0
1
S4
Assignment
State Name Q2 Q1 Q0
S0
0 0 0
0 0 1
S1
0 1 0
S2
0 1 1
S3
1 1 1
S4
S1
11
10
S4
S3
S2
State Map
Q1 Q 0
Q2 00 01 11 10
0 S0 S1 S3 S2
1
S4
State Map
i.
i/j
i/k
Highest Priority
ii.
Medium Priority
iii.
i/j
i/j
Lowest Priority
i/j
E.g.:
i/k
Highest Priority
0/0
A
0/0
1/0
0/0
B
1/0
1/1
0/0
C
1/0
J.J. Shann 6-123
E.g.:
Medium Priority
0/0
A
0/0
1/0
0/0
B
1/0
1/1
0/0
1/0
J.J. Shann 6-124
Guideline 3:
i/j
i/j
E.g.:
Lowest Priority
0/0
A
0/0
1/0
0/0
B
1/0
1/1
0/0
(A, B, C, D) (A, B, C)
C
1/0
J.J. Shann 6-125
E.g.:
State diagram
State table
0/0
A
0/0
State Map:
Q1
Q0
0
1
1/0
0/0
B
1/0
1/1
0/0
C
1/0
State Assignment:
A=
B=
C=
D=
J.J. Shann 6-126
Transition Table 1
Q1Q0
00
01
10
11
Q1+ Q0+
00
00
11
00
01
10
10
01
Transition Table 2
Q1Q0
00
01
11
10
Q1+ Q0+
00
00
10
00
01
11
11
01
J.J. Shann 6-127
Q1+ Q0+
Q1+ Q0+
Q1Q0
00
01
10
11
00
00
11
00
Q1Q0
01
10
10
01
00
01
11
10
00
00
10
00
01
11
11
01
Q1+
0
0
0 0 1
1 0 1
Q1+
0 0 1 0
0 1 1 0
Q0+
0
1
0 0 1
0 1 0
Q0+
0 0
1 1
0 0
1 1
0 0
0 0
0 0
0 0
0 0
0 1
J.J. Shann
0 0
1 0
6-128
Reset
(S3', S4') 2
S0
i/j
i/k
Highest Priority
0,1/0
0,1/0
1/0
S1
0/1,
1/0
0/0
(S3', S4')
Medium Priority
S3
'
S4
'
i/j
i/j
Lowest Priority
J.J. Shann 6-129
Highest Priority:
(S3', S4') 2
Q1
Q0
S0
S3
S1
S4
Medium Priority:
(S3', S4')
Lowest Priority:
0/0: (S0, S1', S3')
1/0: (S0, S1', S3', S4')
Reset State = 00
Highest Priority Adjacency
Q1
Q0
S0
S1
S3
S4
Not
Notmuch
muchdifference
differencein
inthese
thesetwo
two
assignments
assignments
1/0
0/0
S1
S2
1/0
0/0
1/0
1/0
0/0
S7'
0,1/0
Medium Priority:
(S1, S2), (S3', S4') 2, (S7', S10')
0/0
S4'
S3'
0,1/0
Highest Priority:
(S3', S4'), (S7', S10') 2
S10'
0/1
1/0
Lowest Priority:
0/0: (S0, S1, S2, S3', S4', S7')
1/0: (S0, S1, S2, S3', S4', S7' , S10')
Highest Priority:
(S3', S4'), (S7', S10') 2
Medium Priority:
(S1, S2), (S3', S4') 2, (S7', S10')
State Map
Q1 Q0
00
Q2
0
01
11
10
Q1 Q0
00
Q2
S0
01
11
S0
1
Q1 Q0
00
Q2
0
01
S0
10
S0
S4'
S7'
01
11
10
Q1 Q0
00
Q2
00 = Reset = S0
S10'
11
10
S3'
S7'
S0
S3'
S4'
S10'
S7'
S4'
S10'
10
11
10
S0
S1
S3'
S2
S4'
(a)
Q1 Q0
00
Q2
0
01
10
S0
S3'
Q1 Q0
00
Q2
0
11
Q1 Q0
00
Q2
0
01
Lowest Priority:
0/0: (S0, S1, S2, S3', S4', S7')
1/0: (S0, S1, S2, S3', S4', S7' , S10')
01
11
Q1 Q0
00
01
11
S7'
S0
S1
S3'
S10'
S7'
S2
S4'
Q2
(b)
10
Adjacent states:
(S7', S10')
(S3', S4'),
(S1, S2),
S10'
Next State
X =0 X=1
101
001
111
011
011
111
010
010
110
010
000
000
000
000
Q2 Q1
00
Q0 X
00 0
01
0
11
0
10
X
01
01
11
10
Next State
X =0 X=1
010
001
100
011
011
100
101
101
110
101
000
000
000
000
11
0
10
X
01
11
10
01
11
10
01
01
11
10
P2
01
0
11
0
10
X
11
10
01
11
10
P1
Q2 Q1
00
Q0 X
00 0
(Another assignment)
Q2 Q1
00
Q0 X
00 1
01
0
P2
(p.6-120(a))
Current
State
( S0) 000
( S1) 001
( S2) 010
( S3' ) 011
( S'4 ) 100
( S7' ) 101
(S'10) 110
Q2 Q 1
00
Q0 X
00 0
Q2 Q1
00
Q0 X
00 0
P0
Q2 Q1
00
Q0 X
00 1
01
11
10
01
11
11
10
10
P1
P0
First encoding exhibits a better clustering of 1's in the next state map
J.J. Shann 6-133
State assignment
Transition table
Eg.:
Transition table
(Binary-coded
state table)
J.J. Shann 6-134
State table:
State assignment:
A = 00, B = 01,
C = 11, D = 10
Binary coded state table:
B (t + 1) = DB ( A, B, C ) = m(1,3,5,7)
Z ( A, B, X ) = m(5)
Logic diagram:
DA = AB + BX
DB = X
Z = AB X
Example:
State table:
3 unused states
000
110
111
Logic diagram:
DA = AX + BX + B C
DB = A C X + A B X
DC = X
Example:
State diagram:
flip-flop inputs:
Q Q+
0 0
0 1
1 0
1 1
J
0
1
1
0
Circuit:
JA = B x
JB = x
KA = B x
KB = Ax + A x = (A x)
Circuit:
F. Verification
Verification w/ simulation
requires a seq of input combinations and applied clocks
Example
E.g.:
Synthesis
(A ~ F)
Verify
Analysis
(G)
Example 6-4
1101
Seq Recognizer
0,1
1,1
1,0
0,1
0,0
0,1
1,1
1,0
0,0
Simulation
0,1
1,1
1,0
0,1
0,0
0,1
1,1
1,0
0,0
Word Problems
Example: Vending Machine
deliver package of gum after 15 cents deposited
single coin slot for dimes, nickels
no change
<Ans,>
Understand the problem:
N
Coin
Sensor
D
Reset
Vending
Machine
FSM
Open
Gum
Release
Mechanism
Clk
Reset
S0
Output: open
N
S1
S2
S4
S5
S6
[open]
[open]
[open]
S3
S7
S8
[open]
[open]
State Minimization
Reset
0
N
5
D
N
10
D
N, D
15
[open]
reuse states
whenever
possible
Problems
Sections
Exercises
6-1
6-2
6-1, 6-2
6-3
6-3, 6-4
6-4
6-5~6-13
6-5
6-6
6-7 ()
6-32~6-37
6-8 ()
6-38~43
Homework
6-5
6-8
6-9
state diagram
state table
6-16
JK flipflopsc