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HDMP-1636A and HDMP-1646A Gigabit

Ethernet Transceiver DesignConsiderations


Application Note 1205
Introduction
The HDMP-1636A/1646A[1] ICs are complete 1.25 GBd
Gigabit Ethernet transceivers in a single IC and compatible with the IEEE 802.3z Gigabit Ethernet standard.[2] The
HDMP-1636A and HDMP-1646A are +3.3 V parts available in a 10x10 mm and 14x14 mm QFP plastic package,
respectively. Both parts use the same silicon bipolar die.
The transmitter is designed to serialize a 8b/10b encoded
10-bit wide word and either transmit it across cable or to
an external fiber optical transceiver. At the other end of the
link, the receiver of another HDMP-1636A/46A takes the
serialized data and reconstructs the 10 bit parallel word.
The transceiver contains all the necessary high-frequency
circuitry, PLL, mux, demux, clock, data recovery circuitry,
cable driver, and cable equalizer.
The purpose of this application note is to show how to
get the best possible performance from the IC and take
advantage of its capabilities. Information on how to test
the HDMP-1636A/46A and the equipment required is discussed. Guidelines for PC board layout are also discussed
in detail. The HDMP-1636A/46A incorporates the latest in
PLL and high frequency design techniques.
Use of these transmitters eliminates the difficult task of
dealing with such circuitry, but does require that the designer use and understand proper layout techniques in
order to get the best performance from the IC. The next
section briefly covers some of these important topics.
Signal Interconnections
The parallel data outputs of the HDMP-1636A/46A are
TTL compatible and are TTL +5 V tolerant. The high-speed
serial lines from the TX to the RX are Positive ECL (PECL)
connections. The TTL lines have rise/fall times that are
typically 1.1 to 1.5 ns and the high-speed lines have rise/
fall times that are in the range of 200 ps. Because of these
fast rise/fall times, interconnects should be treated as
transmission lines rather than simple wire connections.
Using transmission lines with a basic understanding of
line matching reduces signal reflection which degrades
overall performance of the part. Before discussing the various methods of connecting the I/Os, it is useful to briefly
cover the topics of microstrip and stripline transmission
lines since their characteristics determine layout practice.

Figure 1a defines the dimensions of the stripline. In this


case the signal transmission line is sandwiched between
the dielectric material of the PC board and two conducting ground planes. Impedance of the transmission line is
determined by the relative dielectric constant (r) of the PC
board material, thickness of the dielectric (h), and the width
of the copper transmission line strip (w). The impedance
is also affected when the thickness of the copper strip (t)
becomes significant compared to the value h.
Figure 1b defines the dimensions of the microstrip. In this
case the signal transmission line is open to air on the topside and has PC board material and a conducting ground
plane underneath it. Impedance of the transmission line
is determined by the relative dielectric constant (r) of
the PC board material, its thickness (h), and the microstrip
trace width (w). The thickness of the copper strip can also
be significant in the impedance calculation. Calculation of
the microstrip impedance is more difficult than for the stripline, because the electric fields from the transmission line
propagate through two different dielectric materialsair
and the PC board.
TRANSMISSION
LINE
W
t
b
GROUND PLANE

(a) STRIPLINE TRANSMISSION LINE

TRANSMISSION
LINE
t

h
GROUND PLANE

(b) MICROSTRIP TRANSMISSION LINE

Figure 1. Stripline and Microstrip Dimensions Defined

6077-01 AN 1205

The following equations for calculating microstrip and stripline


impedance are often referenced in
the literature.[3,4,5] These equations
are useful as a first order approximation. More accurate equations
exist,[6] but the approximation equations are adequate for most digital
Equations-1 AN 1205
design work.

Equations-1
AN 1205
The characteristic
impedance
Zo of
the microstrip is calculated using
the approximation:
Zo =

87
5.98h
ln
0.8w + t
r + 1.41
87

5.98h

Zo =
ln
The
delay
for microstrip
r + 1.41
tpd =propagation
1.017
0.475r +0.8w
0.67+ t
is:

tpd
Equations-1
AN 1205
1205
Co
(pF/ft)
tpd == 1.017
AN
0.475r + 0.67
ZoEquations-1
tpd
Co =
(pF/ft)
Zo

where:
4b
= 60 ln dielectric
Zo
constant
of
r = relative
+ t)
r 87 0.67(0.8w
5.98h
Zo =
the
PCB
board
ln
87
5.98h
Zo== 60r +
4b
0.8w
+t
Zo
ln1.41 ln 0.8w
Zo
= characteristic
impedance
of the
0.67(0.8w
++t)t
rr + 1.41
transmission line
tpd==capacitance
1.017 0.475rof
+ 0.67
Co
the transmistpd
= 1.017
r + 0.67
tpd = 1.017 0.475
r (ns/ft)
sion line
tpd
Co = tpd (pF/ft)
Zo
Co
tpd== Zo
1.017(pF/ft)
r (ns/ft)

of the transmission line shorter than


the rise or fall time of the driving
signal. This number is an approximation only, since it depends on the
dielectric constant (which can vary
over a wide range), the impedance
of the transmission line used, and
the load at the end of the line.
PC Board Layout
Proper PC board layout is important in order to minimize parasitic
capacitance and inductance which
can cause ringing and poor VSWR
match on the high-speed serial
lines. It is also important to use
transmission lines with controlled
impedance on all frame rate and
serial rate lines. Figure 2 shows a
4-layer PC board structure used to
build the HDMP-163K evaluation
board.[7] Standard FR4 material was
used with a typical relative dielectric
constant (r) of 4.4.
0.007 INCHES (0.178 mm) TYPICAL
LAYER 1
COMPONENT SIDE
(TRACES)

DIELECTRIC

The characteristic impedance for


stripline is calculated using the
equation:
4b
Zo = 60 ln
4b + t)
r ln 0.67(0.8w
Zo = 60
0.67(0.8w + t)
r

0.039 INCHES
(0.991 mm) TYPICAL
CORE

and propagation delay is:


tpd = 1.017 r (ns/ft)
tpd = 1.017 r (ns/ft)

Dielectric constant (r ) of glassepoxy board (FR4) varies from


about 4.4 to 5.0. As an example,
calculating the transmission line
impedance and propagation delay
for microstrip using the variables
r =4.4, h = 7 mils, w = 12 mils and t
=0.7mils results in Zo = 50.6 , tpd
= 140.8 ps/in. and Co = 2.78pF/in.
Reflections can be minimized by
keeping the total round trip delay

LAYER 2
GROUND
PLANE

LAYER 3 VCC (+5 V)


PLANE

DIELECTRIC
LAYER 4
TRACES

LAYERS 1 AND 4:

1/2 OZ. COPPER FOIL =


0.0007 INCHES (0.0178 mm)
THICK.

LAYERS 2 AND 3:

1 OZ. COPPER FOIL =


0.0014 INCHES (0.0356 mm)
THICK.

r = 4.4

Figure 2. Multilayer PC Board Structure.

6077-02 AN 1205

Input and output lines that require


controlled impedance are placed on
layers 1 and 4. The microstrip media
is formed from the combination of
layer 1, the dielectric material, and
the solid copper plane of layer 2.
The same scheme is used for layers
3 and 4. Transmission line widths are
0.012 inches (0.3048 mm) for 50
using the thickness and dielectric
constant of Figure 2. Data lines
should be of equal length in order
to minimize skew between lines.
The high-speed serial differential
lines should also be routed together
for the same reason.
The HDMP-1636A conforms to the
QFP 10x10 -64 package outline and
the HDMP-1646A conforms to the
QFP 14x14 -64 package outline. Figure 3 shows the recommended PC
board land pattern recommended
to conform to the package leads.[8]
Power Supply Decoupling
The HDMP-1636A/46A removes
much of the burden of high-frequency design from the designer,
but it does require that good layout
and bypass techniques be used to
get the best performance from the
IC. Bypass capacitors should be used
and placed as close as possible to
the appropriate power supply pins
of the HDMP-1636A/46A as shown
in the schematic of Figure 4. The
voltage into these pins should be
clean with minimum noise.
PLL Loop Filter Capacitors
The PLL loop filter capacitors and pin
locations on the transceiver IC are
shown in Figure 5. Notice that only
two capacitors are required, CPLLT
for the transmitter and CPLLR for
the receiver. Nominal capacitance is
0.1F. The maximum voltage across
the capacitors is on the order of
1volt, so the capacitor can be a low
voltage type and physically small.

VCC**

VCC

GND_RXA
VCC_RXA
RXCAP1

VCC_TXECL
VCC
GND
VCC
GND*
VCC*

GND_TXHS
VCC_TXHS

GND*

VCC*

CPLLR
RXCAP0
GND_RXTTL

VCC*

VCC_RXTTL

VCC

TOP VIEW
VCC*

B
C
D

12.00
14.2
17.8

E
X

6077-03
0.80
0.5

1.80

7.5
10.2
13.8

AN0.50
1205
0.30
1.80

All dimensions are in mm.

TXCAP1

VCC
VCC_RXTTL

12.00

GND

16.00

VCC

HDMP-1636A

VCC
GND

HDMP-1646A

TXCAP0
VCC_TXA

VCC_RXTTL

GND*
GND_TXA

GND_RXTTL

GND_RXTTL

CPLLT
VCC

VCC**

** SUPPLY VOLTAGE INTO VCC_RXA AND VCC_TXA SHOULD BE FROM A


LOW NOISE SOURCE. ALL BYPASS CAPACITORS = 0.1 F.

Figure 4. Power Supply Bypass.

Figure 3. HDMP-1636A/46A PC Board Land Pattern.

6077-04 AN 1205
The PLL capacitors are placed physically close to the appropriate pins on
the transceivers as shown in Figure 5.
Keeping the lines short prevent the
PLL loop capacitors from picking up
stray noise from surrounding lines or
components.
I/O Interfacing
The HDMP-1636A/46A has four
different I/O types as summarized
in Table 1. The I-TTL and O-TTL are
compatible to standard TTL. The
high-speed serial lines are Positive
ECL (PECL) output voltage swings,
but are designed to be AC coupled.
All I/O connections have ESD protection diodes. Figure 6 shows the
high-speed serial connections.
3

Resistors R1 and R2 (150 ) set the


DC bias current through Dout+/
Dout-. The value of R5 and R6 depends on the impedance of the
transmission line that the transmitter
drives. Their values are simply equal
to the transmission line impedance.
For Z0 = 75 , R5 and R6 = 75 ,
and for Z0 = 50 , R5 and R6 = 50
. The optional series padding resistors (R3 and R4) help dampen load
reflections. Typical padding resistor
values for mismatched loads range
from 25 to 75 . A single differential termination resistor can also
be used as shown in Figure 6b. Its
value is simply 2Zo or 100 for 50
transmission lines and 150 for 75
transmission lines. Notice that the

+DIN/-DIN input pins do not require


any external bias resistor. Bias is applied internally on the chip. Figure 7
shows an example of the PC board
layout highlighting the placement of
the high-speed terminations.
Thermal Considerations: HDMP-1636A/46A
The body of the package is composed of a high temperature plastic.
Because of the very low power dissipation of the +3.3 V parts (630 mW
typical), no internal heat spreader is
used in these plastic package parts.
The HDMP-1636A has a typical junction to thermal resistance number
of 11 C/W and the HDMP-1646A is
typically 8 C/W per the data sheet.

RXCAP0
RXCAP1
CPLLR

BYPASS CAPACITORS CAN BE PLACED


ON THE TOP OR BACKSIDE OF THE PC BOARD

49
48

0.1

TOP VIEW
GND

*VCC

*VCC

16
17

*GND
*GND

TXA

0.1

GND
GND
0.1
VCC

TXCAP0

VCC

TOP VIEW

GND

TXCAP1

GND_RXTTL

VCC_RXTTL

VCC_RXTTL

Zo

C1
R5

TX
-DOUT

Zo
R1

R2

-DIN

0.01
VCC_RXA

0.1

KEEP THE INPUT TERMINATION


RESISTOR AS CLOSE AS
POSSIBLE TO THE DIN LINES
0.1

+DIN
C3
RX

R6

R4

0.01
150

6077-05 AN 1205
R3

Rpad
150

+DIN
VCC
VCC_RXTTL
RBC1
RBC0
GND_RXTTL

Figure 5. Placement of the PLL Loop Filter Capacitors.

Rpad

0.1

0.1

CPLLR, CPLLT = 0.1 F PLL LOOP FILTER


CAPACITORS.

150

VCC_TXHS
+DOUT
-DOUT
VCC_TXECL

VCC_TXA
VCC

CPLLT

+DOUT

OPTIONAL SERIES
RESISTORS: SEE
TEXT

KEEP THE OUTPUT


BIAS RESISTORS AS
CLOSE AS POSSIBLE
TO THE DOUT LINES

Figure 7. Layout Example

-DIN

C2

Table 1. I/O Type Definitions and PIN Usage.


R1 = R2 = 150 OHMS, R3 = R4 = OPTIONAL
(SEE TEXT)

I/O Type

Definition

Used on Pins:

R5 = R6 = Zo

I-TTL

Input TTL.
6077-07 AN 1205
Floats high when left open

TX[0...9], LOOPEN,
REFCLK, ENBYTSYNC

O-TTL

Output TTL
BYTSYNC,

RX[0...9], RBC0, RBC1,

HS_OUT

High-Speed Output.
PECL Compatible.

+DOUT, -DOUT

HS_IN

High-Speed Input.
PECL Compatible.

+DIN, -DIN

C1 = C2 = C3 = 0.01 F

(a) HIGH SPEED Tx TO Rx CONNECTION.

+DOUT

R3

Zo

RX

R4
Zo

R1

+DIN

R5

TX
-DOUT

C1

R2

C2

-DIN

R1 = R2 = 150 OHMS, R3 = R4 = OPTIONAL


(SEE TEXT)
R3 = R4 = Zo

C1 = C2 = 0.01 F

R5 = 2Zo

(b) HIGH SPEED Tx TO Rx CONNECTION


WITH SINGLE TERMINATION RESISTOR.

Figure 6. High-Speed Serial Line Connection.

607706 1205

Applications Support
System designers can quickly
evaluate the HDMP-1636A or the
HDMP-1646A by ordering the
HDMP-163K evaluation board. This
is a completely assembled board
for the HDMP-1636A transceiver
(electrical performance is the same
as the HDMP-1646A). The evaluation
board is designed for a quick and
easy evaluation of the transceiver
chip. The board brings out all pins
from the chip to various connectors and jumper options. It can be
used in a stand-alone configuration
or connected to an external host.
The parallel interface to the host
is through a 2x10 ribbon header
on the input and a 2x14 ribbon
header on the output. SMA connectors are provided on all the
high-speed serial coax lines and on
the reference clock input (REFCLK).
A socket for an onboard reference
clock at 125MHz is also provided. A
BER much better than 1 x 10-14 can
be routinely measured using the
HDMP-163K evaluation board. This
is over 24hours of error free operation at 1.25 GB. Figure 8 shows the
eye diagram at 1.25 GB when measured using an Avago Technologies
83480A Communications Analyzer
connected to the Dout- coax port of
the HDMP-1636A.
Fiber-Optic Interface
Figure 9 shows how the HDMP1636A/46A can be connected to
the HFBR-53D5 multimode, 1-rowof-9-pins (1x9) VCSEL fiber-optic
transceiver. The following are some
suggested layout guidelines when
using the HDMP-1636A/46A and
HFBR-53D5.
Use controlled impedance transmission lines on the parallel and
high-speed serial lines.
Route the high-speed differential
lines together and keep them of
5

200.0 ps/DIV

107.6074 ns

f1 300 mV/DIV

(a) DIFFERENTIAL OUTPUT


(DOUTDOUT-).

200.0 ps/DIV

107.2954 ns

f1 150 mV/DIV

(b) DOUT+

200.0 ps/DIV

107.2954 ns

f1 150 mV/DIV

(c) DOUT-

Figure 8. Eye Diagrams of the high-speed serial outputs


from the HDMP-1636A as captured on the Avago
Technologies 83480A Digital Communications Analyzer.
The equipment setup of Figure 8 was used with a
6077-08
AN 1205
7-1.
PRBS=2

equal length to minimize pulsewidth distortion.


Use differential signals to interconnect components. Avoid
unbalanced, single-ended use of
the high-speed data lines which can
cause pulse-width distortion.
Place power supply filter circuits
as close as possible to the VCC pins
of the fiber optic transceiver and
SERDES for best noise filtering.

The SERDES can have a VCC island


of metal cut out from the common digital +3.3 volt VCC plane.
This island can be located under
the SERDES. The digital VCC can be
bridged over to the SERDES VCC island via the ferrite bead as shown
in Figure 9.
The HFBR-53D5 can have an
island of metal cut out of the common +5 volt VCC plane and located
under the receiver section of the
HFBR-53D5. The +5 volt digital VCC
can then be bridged over to the
receiver VCC island via the 1 h
inductor as shown in Figure 9. The
power supply bypass capacitors
must be as close as possible to the
transmitter VCC pin.
Keep high-speed load and source
resistors close to their respective
pins. A source or load resistor is
not as effective when positioned
physically far from its respective pin.
Using 0603 size components on the
high-speed terminations and series
capacitors makes the layout easier.
The 0603 size is smaller compared
to the 0805, thus reducing unwanted parasitics (less inductance) and
making it easier to position close to
the required pins.
Use short transmission lines between the SERDES parallel I/Os and
a MAC or protocol IC. Choose shorter parallel lines at the expense of
longer high-speed differential lines
between the SERDES and the fiberoptic module. The Tx high-speed
outputs can drive longer lengths of
microstrip transmission lines than
the Rx TTL outputs.
Mount the Tx and Rx PLL charge
pump capacitors close to their
respective pins and keep the connections to these capacitors short.

VEE
TD+
TDVCCT
VCCR
SD
RDRD+
VEE

SD

L7
1 H

9
8
7
6
5
4
3
2
1

C18
0.1 F

C23
0.01 F

8
7
6
5

R22
270

L8
1 H

R23
270

VDDSD

R25
191

R27
68

R26
191

R28
68

C17
0.01 F

C16
0.01 F

R29 0

C14
0.01 F

C15
0.01 F

VDDSD

0.1 F

0.1 F

0.1 F

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

C43
0.1 F

VDDSD

VDDSD

VDDSD

6077-09 AN 1205

0.1 F

R21
150

0.1 F

R20
150

R30
0

R42
100

C47
0.1 F

L10
1 H

CAPACITORS PLACED PER POWER


SUPPLY BYPASS FIGURE 4

VCC (5 V)

10 F
(TANTALUM)

RX_LOS

C108
10 F
(TANTALUM)
(OPTIONAL)

C21
0.1 F

C19
0.1 F

R31
0

VCC (5V)

C20
0.1 F

VCC (5V)

VCC
Q0
NC
GND

Figure 9. HDMP-1636A/46A and HFBR-53D5 Reference Schematic.

HFBR-53D5

U4

R24
270

1
NC
2
D0+
3
D04
VBB

US MC100ELT21

PECL TO TTL
CONVERSION (NON-INVERTING)

BYTSYNC

RX[9:0]

U3
HDMP-1636A

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

TX[9:0]

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

6
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
C42
0.1 F

VDDSD
7
14
XTAL 125
MHz

U2

LOOPEN

REFCLK

ENBYTSYNC

L9 1 H VDDSD

C46
0.1 F

N/C
N/C

RBC0
RBC1

FER BD-SMT-HF30ACB201209-600mA
VDDSD
L2
VDD
C109
(+3.3 V)
10 F (TANTALUM)
+

Jitter Transfer
Jitter transfer for the transmitter PLL
is shown in Figure 10. The curves are
generated by modulating REFCLK
(125 MHz) with a sinusoidal waveform and measuring the resulting
jitter transferred or imposed on the
high-speed 1.25 Gb/s transmitter
output lines. In this case, the sinusoidal waveform is swept from 10 KHz
to about 7 MHz. The PLL behaves
like a low-pass filter to any noise
present on REFCLK. Below the corner frequency (f - 3 dB) of about 1 to
2 MHz, frequencies are passed with
no attenuation. Only a slight 0.6 dB
amplification of the modulating signal occurs at the corner frequency.
The REFCLK modulation signal is
attenuated when it exceeds the corner frequency of the PLLs low pass
filter response. The vertical axis is
expressed in jitter gain (dB). Because
of the non-linear nature of the PLL,
the corner frequency is also a function of the jitter amplitude. The jitter
amplitude is varied from 0.05UI
to 1UI, resulting in the 4 different
curves shown in Figure 10. UI stands
for Unit Interval, and is a traditional
unit of measurement for jitter amplitude. One UI is defined as the 800 ps
time interval of one 1.25 GB symbol.
When jitter is equal to 800 ps, the
phase deviation of the clock is equal
to 1 UI.

100

10
TOLERANCE (UI)

JITTER GAIN (dB)

Jitter Performance
The HDMP-1636A/46A meets the
jitter budget in Table 38-10 of the
IEEE 802.3z Gigabit Ethernet specification.[9] Transmitter jitter transfer,
jitter tolerance and VCC jitter transfer
curves for the SERDES are provided
in the next sections. Although not
required by the Gigabit Ethernet
standard, the graphs are useful
information in understanding the
performance of the SERDES.

-5

-10

-15
-20
1 E+3

0.05 UI
0.15 UI
0.3 UI
1.0 UI
10 E+3 100 E+3 1 E+6 10 E+6
JITTER FREQUENCY (Hz)

0.1
TOLERANCE RESULTS
INSTRUMENT LIMIT

100 E+6

Figure 10. Tx Jitter Transfer for the HDMP-1636A/46A.


6077-10 AN 1205

Jitter Tolerance
Jitter tolerance is a measure of
design margin in a serial communications link. The purpose of the test
is to measure the transceivers error
performance as a function of sinusoidal jitter at various frequencies
and amplitude levels. There is no
jitter tolerance mask in the Gigabit
Ethernet standard. The following is
provided for information only. Sinusoidal jitter is added to REFCLK. In
this test, random and deterministic
jitter are added in order to simulate
a real system. Random jitter (0.287
UI) is added using a random noise
generator (noise diode generator),
and deterministic jitter (0.462 UI) is
added using a fixed amount of coax
cable. Detailed information on jitter
tolerance measurement techniques
is contained in the work done by the
Fibre Channel Jitter Working Group
and is a good reference.[10] Figure
11 shows the results of this test.
The lower curve is the measured
behavior of the HDMP-1636A/46A
transceiver. Note that below about
300 KHz, the transceiver can tolerate jitter above 1 UI. If viewed on
a digital oscilloscope, this corresponds to no eye opening. At these

0.01
1 E+0

100 E+0
10 E+0
1 E+6
JITTER FREQUENCY (Hz)

100 E+6

Figure 11. Jitter Tolerance for the HDMP-1636A/46A.


6077-11 AN 1205

frequencies, the PLL is capable of


tracking the input signal even when
jitter causes the data to move more
than 1 symbol time (800 ps). The
transceivers ability to track jitter
decreases as frequency increases.
A general discussion of measuring
jitter transfer, jitter tolerance, and
the equipment used for such tests is
available in the literature.[11,12]
VCC Jitter Transfer
Figure 12 shows the excellent noise
immunity that the transceiver has
against power supply noise. The
graph shows the Rx recovered clock
output (Rbc) jitter as the sinusoidal
VCC noise is increased in amplitude
from 100 mV pk-pk to about 800 mV
pk-pk. Curves are overlaid from 100
KHz to 800 KHz and show only 1.2 ns
pk-pk jitter on Rbc with a VCC noise
level of 800 mV pk-pk! It would be
difficult to create this much VCC supply noise in an actual system when
using the recommended bypass
techniques. The data taken for this
test used an evaluation board (HDMP-163K) with all bypass capacitors
removed from the PC board, leaving
only the intrinsic capacitance formed
by the VCC and ground plane layers.

1400

RBC JITTER (p-p, ps)

1200

References
[1] HDMP-T1636A/1636A/1646A
Gigabit Ethernet Transceiver Chip
Data Sheet, publication number
5968-3339E (5/99).

100 KHz TO 800 KHz

1000
800

[2] IEEE 802.3z Gigabit Ethernet Interface Specification.

600
400
200
0
0

200
400
600
VCC NOISE (p-p, mV)

800

Figure 12. VCC Noise Tolerance


forAN
the1205
HDMP-1636A/46A.
6077-12

Driving Copper Cable


The Gigabit Ethernet Standard[2]
calls out two types of high-speed
connectors: the 9 pin dB9 and the
HSSDC. The HDMP-1636A/46A transceiver is fully capable of directly
driving 25 meters of duplex Twinaxial copper cable. Twinaxial cable is a
form of shielded twin-lead.

[3] Kaupp, H.R., Characteristics of


microstrip transmission lines, IEEE
Trans. Electronic Computers, vol.
EC16, Apr. 1967.
[4] Springfield, W.K., Multilayer
Printed Circuitry in Computer Applications, presented at the fall
meeting on printed circuits, Chicago, Ill., Oct. 1964.
[5] Blood, Jr., William R., MECL System Design Handbook, Motorola
Inc., 1983
[6] Howard W. Johnson, Martin
Graham, High-Speed Digital Design, A Handbook of Black Magic,
Prentice Hall 1993

[7] HDMP-163K Evaluation Board


Users Guide, Avago Application
Note 1204.
[8]. SQFP/QFP(Square) land pattern
dimensions, Surface Mount Design
and Land Pattern Standard, Institute
for Interconnecting and Packaging
Electronic Circuits (IPC) IPC-SM-782
Rev A August 1993. 708-677-2850.
[9] IEEE Draft 802.3z Gigabit Ethernet Interface Specification, section
38.5 Table 38-10, 1000BASE-SX and
1000BASE-LX Jitter Budget.
[10] Fibre Channel Methodologies
of Jitter Specification (MJS)Jitter
Working Group Technical Report,
ANSI Rev 10.
[11] Avago 71501C Jitter Analysis
System Product Overview, publication number 5965-0801E
[12] Christopher Miller, David McQuate, Jitter Analysis of High-Speed
Digital Systems, HP Journal, Vol.
46A, no. 1, Feb 1995, pp 49-56.

Information in this application note is subject to change without notice.

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5980-0276E - July 28, 2010