QUESTION 1

Based on K-map of function Z in Figure 1;

(a) Derive minimum SOP and POS expression for function Z
(b) Draw the logic circuit of minimum POS expression obtain in (a) using
(i) NAND gates only
(ii) NOR gates only

Figure 1
QUESTION 2
Table 1
A

(a) State the function of Y(A,B,C,D) in;

(i) small m notation and write the standard SOP expression for the function
(ii) big M notation and write the standard POS expression for the function
(b) Simplify standard SOP expression obtain in (i) using Karnaugh Map
(c) Draw the simplified logic circuit of function Y
QUESTION 3
Convert ASCII code given in Table 2 below in 8 bit binary numbers
Table 2
ASCII
E
n
H
R
b
B
QUESTION 4
Sketch asynchronous counter that can be implemented having a
(a) Modulus 12 with binary sequence 0000 to 1011 using positive edge-triggered JK FF
(b) Modulus 9 with binary sequence 0000 to 1000 using negative edge-triggered JK FF
(c) Modulus 10 with binary sequence 0000 to 1001 using positive edge-triggered JK FF
(d) Modulus 13 with binary sequence 0000 to 1100 using positive edge-triggered JK FF

QUESTION 5
Add the two hexadecimal numbers given;
(a) D7A and 6B3
(b) C5 and 3F

(c) 3D5 and AB4

QUESTION 6
The numbers given below are represented in BCD code. Convert the number into
Hexadecimal.
1100 1001 0101 0110 0111 0010 0011
QUESTION 7
Figure 2 shows a logic circuit for output F.
(a) Develop the truth table that shows the output and input
(b) Derive standard SOP expression for output F
(c) Derive the simplified Boolean expression for output F using Boolean algebra
(d) Derive the simplified Boolean expression for output F using K-map
(e) Draw the simplified logic circuit
(f) Redraw the simplified using only
(i) NAND gates
(ii) NOR gates

Figure 2

QUESTION 8
Simplified logic circuit given in Figure 3 using Boolean algebra and DeMorgans Theorem

Figure 3
QUESTION 9
Block diagram in Figure 4 shows the full adder where it has 3 inputs, X, Y and carry in (Cin).
Full adder produces two outputs which are sum, S and carry out (Cout).
(a) Design a full adder using logic gates
(b) Show how to implement full adder by using two half adder

Figure 4

QUESTION 10
Figure 5 shows the block diagram of a system. The system has 2 inputs with 2-bit wide. The
outputs produces is set as follow;
Output Y is HIGH when input R is smaller than S
Output Z is LOW when input S is smaller than R
Both outputs Y and Z are HIGH when input R and S are equal
Design the system by considering the operational condition as given. Include truth table,
Karnaugh map, Boolean expression and also the simplified logic circuit.

Figure 5
QUESTION 11
Figure 6 shows 8:1 multiplexer
(a) Derive standard SOP expression of output X
(b) Develop the truth table that implements 8:1 multiplexer in Figure 6
(c) Simplify the expression of output X using Karnaugh Map
(d) Draw the logic circuit that implement the simplified expression obtain in (c)

Figure 6
QUESTION 12

Block diagram of a decoder that accepts 3-bit wide binary input and display the alphabet is
shown as in Figure 7. Design the decoder based on the input-output mapping given in Table
3.

Figure 7
Table 3
X2

X1

X0

7 segments output

Blank

Blank

QUESTION 13
Design a synchronous counter with the irregular binary count sequence as in state diagram
below. Use;
(a) Positive edge triggered JK Flip Flop
(b) Positive edge triggered D Flip Flop
(c) Positive edge triggered SR Flip Flop

00
0
10
1

01
0

01
1

11
1
10
0

QUESTION 14
Counter with Modulus 11 will count up or down from 0000 to 1010. Design a Modulus 11
synchronous counter that will count down 11 numbers from 1010 to 0000. Use
(a) Positive edge triggered D Flip Flop
(b) Positive edge triggered JK Flip Flop
(c) Positive edge triggered SR Flip Flop
Show all the steps required in designing the synchronous counter