Appendix A: Instruction Set Principles

1 / 17

Chapter Overview

Classification

Memory Addressing

Operand Types

Basic Operations

Encoding Instruction Sets

The Role of Compilers

Putting it all together: The MIPS Architecture

2 / 17

Classification

General-purpose register (GPR) architectures

I
I

Register-memory architectures
Load-store architectures

Stack architectures

Memory-memory architectures

Accumulator architecture

3 / 17

Memory Addressing

Little Endian (word address = rightmost byte address)

Big Endian (word address = leftmost byte address)

The significance of alignment

4 / 17

Addressing Modes/Operand Types

The book begins to really open up and clearly show examples

of quantitative measures to support design decisions. Examine
the graphs of quantitative measures and corresponding prose
closely. Establish this habit for the remainder of your studies in
this textbook.

5 / 17

Frequency of Addressing Modes

TeX 1%
6%
Memory indirect spice
1%
gcc
TeX 0%
Scaled spice
6%
gcc

16%
24%

TeX
Register indirect spice
gcc

3%
11%
43%

TeX
Immediate spice
gcc

17%
39%
32%

TeX
Displacement spice
gcc

55%
40%
0%

10%

20%
30%
40%
50%
Frequency of the addressing mode

60%

6 / 17

Distance of Operand Displacements

40%

Percentage of displacement

35%
Integer average
30%
25%
20%
Floating-point average
15%
10%
5%
0%
0

5
6
7
8
9 10 11
Number of bits of displacement

12

13

14

15

7 / 17

Frequency of Immediates

Floating-point average
Integer average

22%
23%

Loads
19%

ALU operations

25%
16%

All instructions
0%

21%
5%

10%

15%

20%

25%

30%

8 / 17

Size of Immediates
45%

Percentage of immediates

40%
35%
Floating-point average
30%
25%
20%
15%
Integer average
10%
5%
0%
0

4
5
6
7
8
9 10 11
Number of bits needed for immediate

12

13

14

15

9 / 17

Top 10 Instructions for 80x86

Rank

80x86 instr

1
2
3
4
5
6
7
8
9
10

load
conditional branch
compare
store
add
and
sub
move (reg-to-reg)
call
return

Frequency
(% total executed)
22%
20%
16%
12%
8%
6%
5%
4%
1%
1%

10 / 17

Control Flow Instructions

Call/return

Jump

Conditional branch
0%

Floating-point average

8%

Integer average

19%
10%
6%
82%
75%
25%
50%
75%
Frequency of branch instructions

100%

11 / 17

Bits of Branch Displacement

Percentage of distance

30%
25%
20%

Integer
average

15%

Floating-point average
10%
5%
0%
0

8
9 10 11 12 13
Bits of branch displacement

14

15

16

17

18

19

20

12 / 17

Relational Tests in Conditional Branches

Floating-point average
Integer average

5%
2%

Not equal

16%
18%

Equal
0%
Greater than or equal
Greater than

11%
0%
0%

Less than or equal

Less than
0%

44%
33%
34%
35%
10%
20%
30%
40%
50%
Frequency of comparison types in branches

13 / 17

Additional Comments

PC relative addressing

Indirect jumps

Caller saving/Callee saving

Instruction set encoding: 16-bit instrs vs compression

I

impact on caches

14 / 17

The Role of Compilers

Optimization (multi-pass [phases])

Effective optimization has dramatic impact: 25%-90%

Register allocation

How to help the compiler writer:

I

Provide regularity

Provide primitives not solutions

Simplify trade-offs among alternatives

Provide abilities to bind quantities known at compile time

15 / 17

Program, compiler optimization level

Impact of Compiler Optimization

lucas, level 3

11%

lucas, level 2

12%

Branches/calls
Floating-point ALU ops

lucas, level 1

Loads-stores

21%

Integer ALU ops

100%

lucas, level 0
mcf, level 3

76%

mcf, level 2

76%

mcf, level 1

84%
100%

mcf, level 0
0%

20%
40%
60%
80%
Percentage of unoptimized instructions executed

100%

16 / 17

The MIPS Architecture

The MIPS instruction set it used throughout the textbook in

examples and to discuss program structures that can impact
design decisions. You will not be examined on your knowledge
of the MIPS instruction set, but familiarity with it will assist you
in later chapters of this textbook.

17 / 17