TEXAS A&M UNIVERSITY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

ECEN-454/ECEN-714 Digital Integrated Circuit Design
Homework 4 total 60 points
Problem 1 (30 points) Consider the following buffered uniform RC line. The total wire
length, wire resistance and wire capacitance are L, R, and C, respectively. At the very
right end of the line, there is an additional load capacitance of CLoad, represented by the
purple square. The RC line is buffered by three identical buffers. Let us assume for the
purpose of delay analysis, each buffer is modeled using a buffer input pin capacitance of
Cb,in, an output pin capacitance of Cb,out , and an equivalent on-resistance of Rb,
respectively. For each line segment, use a one-segment model to characterize its
delay.

L/3

L/3

L/3

(a) (10 points) Draw a detailed RC model for the buffered RC line by plugging the model
for each buffer.
Answer:

Cb,out

Rb

Rb

Rb

R/3
C/6 C/6

Cb,in

Cb,out

R/3
C/6 C/6

Cb,in
Cb,out

R/3
C/6 C/6

CLoad

(b) (5 points) Derive the Elmore delay of the buffered line.

Answer:
First segment:
D1 = Rb(Cb,out +C/3 + Cb,in) + R/3 (C/6 + Cb,in)

Second segment:
D2 = D1
Third segment:
D3 = Rb(Cb,out +C/3 + CLoad) + R/3 (C/6 + CLoad)
Total Delay:
D_buf = D1 + D2 + D3 = Rb(3Cb,out + C + 2Cb,in + CLoad) + R/3 (C/2 + 2Cb,in+ CLoad)

(c) (10 points) Determine the Elmore delay of the un-buffered line (i.e. if we remove the
last two buffers).
Answer:
The RC model for the un-buffered line is:

The Elmore delay is:

D_unbuf
= Rb(Cb,out +C+ CLoad) + R(C/2 + CLoad)

(d) (5 points) Determine under what condition(s) buffering in fact reduces the RC line
delay and explain your finding.

Answer:
D_diff = D_unbuf - D_buf = Rb(Cb,out +C+ CLoad) + R(C/2 + CLoad) Rb(3Cb,out + C +
2Cb,in + CLoad) - R/3 (C/2 + 2Cb,in+ CLoad)
= - Rb(2Cb,out + 2Cb,in) + R(C/3 + 2/3CLoad - 2/3Cb,in)
If D_diff > 0, then buffering actually reduces the overall delay. This condition can be
alternatively expressed as:
R(C/3 + 2/3CLoad) > Rb(2Cb,out + 2Cb,in) + 2/3RCb,in

The smaller Rb, Cb,in, Cb,out, the more likely that there would a delay reduction. Also, for
longer RC lines and heavier loadings (large CLoad), buffering tends to be more effective.

Problem 2 (15 points) Compute the Elmore delays at node 1, 5 and 6 in the RC tree.

R6
6
C6
R4
R1

R2

R5
C5
5

R3
C4

1
C1

C2

C3

Answer:
Node 1:
The resistors that are on the signal path starting from the root to the node of interest:
R1.
Elmore delay: R1(C1 + C2 + C3 + C4 + C5 + C6)
Node 5:
The resistors that are on the signal path starting from the root to the node of interest:
R1, R2, R4, R5
Elmore delay: R1(C1 + C2 + C3 + C4 + C5 + C6) + R2 ( C2 + C3 + C4 + C5) + R4 (C4
+ C5) + R5 C5
Node 6:
The resistors that are on the signal path starting from the root to the node of interest:
R1, R6
Elmore delay: R1(C1 + C2 + C3 + C4 + C5 + C6) + R6 C6

Problem 3 (15 points) Now consider the buffered RC tree shown below. Suppose the
input and output pin capacitances and equivalent on-resistance for the inverter are Cinv,in,
Cinv,out and Rinv, respectively. Re-compute the Elmore delay at node 6.

Answer:
Delay from the input to the input of the inverter:
D1 = R1 * (C1 + C2 + C3 + C4 + C5 + Cinv,in )
Delay from the inverter to Node 6:
D2 = Rinv * (C6 + Cinv,out ) + R6 C6

Total: D = D1 + D2