ITBP205

Digital Design and Computer

Organization
Unit 7
Memory Elements
Prof. Walid Ibrahim

Outline
SR Latch
D Latch
Edge Triggered Flip Flops
Parallel and Shift Registers

Combinational circuits
The logic
circuits
considered so
far have been
combinational
circuits

Ex: 3 + 3 = 6
no matter
what is the
time or the
state of the
circuit

They have no
memory

Its output
levels at any
instant of time
depend on the
levels present
at the inputs
at that time

Any prior
input-levels or
conditions
have no effect
on 3the present
outputs

Sequential circuits
Sequen
tial
circuits
contain
memor
y
elemen
ts

Most
digital
system
s
contain
sequen
tial
elemen
ts

Basic
buildin
g
blocks
of
sequen
tial
circuits
are
flipflops
and
latches
4

General digital system

Combinational outputs

Memory outputs

Combinational logic
gates

Memory
elements

State
State

External inputs

SR Latch
0
1

1
0

1
0

0
1

Inputs
S
R
0
0
0
1
1
0
1
1

Logic symbol
S
R

Q
Q
6

Output
Q
Q
Invalid
1
0
0
1
No
Chan
ge

S-R latch with enable

S
E

01

10
1
S

No change

1
Q

R
R

10

01

0
1 1

10

Inputs

Output

S
X

R
X

E
0

1
7

Q
No
Chang
e
No
Chang
e7

Delay (D) Latch

D

10

01

10

01

1
R
R
01

10

Inputs
D E

Output
Q Q

0
1
X

0
1

1
1
0

1
0

No
change

Delay (D) Latch

S

D
E

1
Q

R
R

Latches are transparent

Output changes according to input while
enabled (i.e., output follows input)

Transparency can create a problem when:

Outputs are connected to inputs
9

Negative-Edge-Triggered
Flip-Flop
D
CLK

Inputs
D
CLK
1

q
d
Master
c

Output
Q
Q
1

Slave

Logic symbol
D

CLK

10

Negative-Edge-Triggered
Flip-Flop
CLK

q1, d1

CLK

Q
11

Example

12

Types of Flip Flops

Delay (D)
FF

Toggle (T)
FF

JK FF

Characteristics (Analysis) Tables

D

Q
(t+1)

Q
(t+1)

Q
(t+1)

Q(t)

Q(t)

Q(t)

Q(t)

13

Exercise
Draw the Q signal for the following ve Edge
FF assuming that Q(t) is Logic 1
CLK

D or T
QD

QT

14

Excitation (Design) Tables

Q(
t)

Q(t+
1)

Q(
t)

Q(t+
1)

Q(t Q(t+
)
1)
0

15

Registers
1

0
At the edge of the clock

1
Clock
16

4-bit register with parallel

load

Load

Q0

D0
CLK

Q1

Load

Q (t +
1)

Q(t)

D1
CLK

Q2

D2
CLK

D
D3
Clock

CLK

Q3

N bits
Parall
el
Regis
ter

N Flip Flops
N inputs
N output
1 clock to
load
1 clock to
unload
17

Shift Register
Serial Input
0 1 01

D0

Q0

D1

Q1

D2

Q2

D3

Clock

N bits
Shift
Regis
ter

N Flip Flops
One input
One output
N clock to load
N clock to unload
18

Q3

Serial
0 Output

4-bit Shift
Register
with
Parallel
Load
Shif
t

Loa
d

19

Function
Shift Left
Parallel load
No change

Bi-Directional Shift Register

with Parallel Load
4x1
S0
Mux
S1

0
1
2
3

Qi-1
S1 S Di

Function

Qi

no change

Di

Clock

Qi

Qi+1

0 Qi-1

shift left

1 Qi+1

shift right

0 D

parallel Load

20