FinFET

History,FundamentalsandFuture
TsuJaeKingLiu
DepartmentofElectricalEngineeringandComputerSciences
UniversityofCalifornia,Berkeley,CA947201770USA

June11,2012
2012SymposiumonVLSITechnologyShortCourse

ImpactofMooresLaw
Transistor
Scaling
Higher Performance,
Investment
Lower Cost

# DEVICES (MM)

Market
Growth

CMOSgeneration:1um 180nm 32nm

Source: ITU, Mark Lipacis, Morgan Stanley Research

YEAR

http://www.morganstanley.com/institutional/techresearch/pdfs/2SETUP_12142009_RI.pdf

1996:TheCallfromDARPA
0.25mCMOStechnologywasstateoftheart
DARPAAdvancedMicroelectronics(AME)ProgramBroad
AgencyAnnouncementfor25nmCMOStechnology
1998InternationalTechnologyRoadmapforSemiconductors(ITRS)
TechnologyNode
GateOxide
Thickness,TOX (nm)
DriveCurrent,IDSAT

1999

2002

2005

2008

2011

2014

2017

2020

180
nm

130
nm

100
nm

70
nm

50
nm

35
nm

25
nm

18
nm

1.92.5

1.51.9

1.01.5

0.81.2

0.60.8

0.50.6

Solutions
beingpursued

Noknown
solutions
EndofRoadmap

UCBerkeleyprojectNovelFabrication,DeviceStructures,
andPhysicsof25nmFETsforTerabitScaleElectronics
June1997throughJuly2001
3

MOSFETFundamentals
MetalOxideSemiconductor
FieldEffectTransistor:

0.25micronMOSFETXTEM

GATELENGTH,Lg
Gate
Source

Drain

Sisubstrate
http://www.eetimes.com/design/automotivedesign/4003940/LCDdriverhighlyintegrated

GATEOXIDETHICKNESS,Tox

MOSFETOperation:GateControl
NchannelMOSFET
Desired
crosssection
characteristics:
HighONcurrent
Gate
LowOFFcurrent
gateoxide
Leff

N+

Source

Body

CurrentbetweenSourceandDrain
iscontrolledbytheGatevoltage.

Nchannel&PchannelMOSFETs
operateinacomplementarymanner
N+
CMOS=ComplementaryMOS

Drain
log ID

increasingE

n(E) exp(E/kT)

Sourceincreasing
VGS
distance

ION

DRAINCURRENT

ElectronEnergyBandProfile

Inverseslopeis
subthreshold swing,S
[mV/dec]

IOFF

Drain

VTH

GATEVOLTAGE

VDD
5

CMOSDevicesandCircuits
CIRCUITSYMBOLS
Nchannel Pchannel
MOSFET
MOSFET

INVERTER
LOGICSYMBOL

VDD

CMOSINVERTERCIRCUIT
VOUT
VDD
S
D
V
D OUT

VIN
GND

S
0

CMOSNANDGATE

VDD

VIN

STATICMEMORY(SRAM)CELL
NOTAND(NAND)
TRUTHTABLE

WORDLINE

BITLINE

0
or
1

1
or
0

BITLINE
6

ImprovingtheON/OFFCurrentRatio
Gate

logID

Cox
Cdep
Source

Body

ION

Ctotal
Cox

Drain

VDD

VGS

ThegreaterthecapacitivecouplingbetweenGateandchannel,the
bettercontroltheGatehasoverthechannelpotential.
higherION/IOFF forfixedVDD,orlowerVDD toachievetargetION/IOFF
reduceddraininducedbarrierlowering(DIBL):
logID
Source

increasing
VDS

Drain

increasing
VDS
IOFF

VGS
7

MOSFETinONState(VGS >VTH)
width velocity inversionlayerchargedensity

I D W v Qinv
v eff

gateoxide
capacitance

Qinv Cox (VGS VTH )

gateoverdrive

mobility

DRAINCURRENT,ID

Gate
Source

Drain

Substrate

DRAINVOLTAGE,VDS
8

EffectiveDriveCurrent(IEFF)
CMOSinverterchain:

VDD

V2

S
D

VIN

D
GND

VOUT

V3

NMOSDRAINCURRENT

V1

VDD
VDD/2

V2
V1

tpLH

tpHL

IH +IL
IEFF = 2

V3
TIME

IDSAT

IH (DIBL=0)

VIN=VDD

IH

VIN=0.83VDD
VIN=0.75VDD

IL

0.5VDD

VIN=0.5VDD

VDD

NMOSDRAINVOLTAGE=VOUT
M.H.Naetal.(IBM),IEDMTechnicalDigest,pp.121124,2002

CMOSTechnologyScaling
XTEMimageswiththesamescale
courtesyV.Moroz (Synopsys,Inc.)

90nmnode

T.Ghani etal.,
IEDM 2003

65nmnode

(afterS.Tyagi etal.,IEDM 2005)

45nmnode 32nmnode

K.Mistry etal.,
IEDM 2007

P.Packan etal.,
IEDM 2009

Gatelengthhasnotscaledproportionatelywithdevice
pitch(0.7xpergeneration)inrecentgenerations.
Transistorperformancehasbeenboostedbyothermeans.

10

MOSFETPerformanceBoosters
Strainedchannelregions eff
Highkgatedielectricandmetalgateelectrodes Cox
CrosssectionalTEMviewsofIntels32nmCMOSdevices

P.Packan etal.(Intel),IEDMTechnicalDigest,pp.659662,2009

11

ProcessInducedVariations
Subwavelengthlithography:
Resolutionenhancement
techniquesarecostlyandincrease
processsensitivity

Gatelineedgeroughness:

courtesyMikeRieger (Synopsys,Inc.)

photoresist

Randomdopant fluctuations(RDF):
Atomisticeffectsbecome
significantinnanoscale FETs

SiO2
Source

Gate
Drain

A.Brownetal.,
IEEETrans.
Nanotechnology,
p.195,2002
A.Asenov,Symp.VLSITech.Dig.,p.86,2007
12

AJourneyBackthroughTime

WhyNewTransistorStructures?
Offstateleakage(IOFF)mustbesuppressedasLg isscaleddown
allowsforreductionsinVTH andhenceVDD
Leakageoccursintheregionawayfromthechannelsurface
Letsgetridofit!
Lg
UltraThinBody
MOSFET:

Gate
Gate
Source
Source

Drain
Drain

BuriedOxide
Substrate

Siliconon
Insulator(SOI)
Wafer
14

ThinBody MOSFETs
IOFF issuppressedbyusinganadequatelythinbodyregion.
Bodydopingcanbeeliminated
higherdrivecurrentduetohighercarriermobility
Reducedimpactofrandomdopantfluctuations(RDF)
UltraThinBody(UTB)

DoubleGate(DG)

Lg
Gate
Gate
Source

Drain

BuriedOxide

TSi

Drain

Source

TSi

Gate

Substrate

TSi <(1/4) Lg
B.Yuetal.,ISDRS1997

TSi <(2/3) Lg
R.H.Yanetal.,IEEETED1992

15

EffectofTSi onLeakage
Lg =25nm;Tox,eq =12
TSi =10nm

TSi =20nm

106

SiThickness[nm]
0.0

3x102

8.0
12.0

16.0
20.0

101
LeakageCurrent
Density[A/cm2]
@VDS =0.7V

4.0

Ioff =2.1nA/m

Ioff =19A/m
16

DoubleGateMOSFETStructures
PLANAR:

VERTICAL

FIN:

L.Geppert,IEEESpectrum,October2002

17

DELTAMOSFET
D.Hisamoto,T.Kaga,Y.Kawamoto,andE.Takeda(HitachiCentralResearchLaboratory),
Afullydepletedleanchanneltransistor(DELTA) anovelverticalultrathinSOIMOSFET,
IEEEElectronDeviceLetters Vol.11,pp.3639,1990

Improvedgatecontrol
observedforWg <0.3m
Leff=0.57m

Wl =0.4m

18

DoubleGateFinFET
Selfalignedgatesstraddlenarrowsiliconfin
Currentflowsparalleltowafersurface
Gate Length, Lg
Source

S
G
D

Gate 1
Drain

Current
Flow

Gate 2

Fin Height, Hfin

Fin Width, Wfin
19

1998:FirstNchannelFinFETs
D.Hisamoto,W.C.Lee,J.Kedzierski,E.Anderson,H.Takeuchi,K.Asano,T.J.King,J.Bokor,andC.Hu,
AfoldedchannelMOSFETfordeepsubtenthmicronera,
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.10321034,1998

PlanView

Lg =30nm
Wfin =20nm
Hfin =50nm
Lg =30nm
Wfin =20nm
Hfin =50nm

DeviceswithLg downto17nm
weresuccessfullyfabricated
20

1999:FirstPchannelFinFETs
X.Huang,W.C.Lee,C.Kuo,D.Hisamoto,L.Chang,J.Kedzierski,E.Anderson,H.Takeuchi,Y.K.Choi,
K.Asano,V.Subramanian,T.J.King,J.Bokor,andC.Hu,Sub50nmFinFET:PMOS,
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.6770,1999

Lg =18nm
Wfin =15nm
Hfin =50nm

Transmission
Electron
Micrograph

21

2000:VestedInterestfromIndustry
SemiconductorResearchCorporation(SRC)& AMDfundproject:
DevelopmentofaFinFET processflowcompatiblewitha
conventionalplanarCMOSprocess
DemonstrationofthecompatibilityoftheFinFET structure
withaproductionenvironment
(October2000throughSeptember2003)
DARPA/SRCFocusCenterResearchProgramfundsprojects:
ApproachesforenhancingFinFET performance
(MSDCenter,April2001throughAugust2003)
FinFETbasedcircuitdesign
(C2S2Center,August2003throughJuly2006)
22

FinFETStructures
Original:
Gatelast
processflow

Gate

Source

Si Fin
Drain
Gate

Improved:
Gatefirst
processflow
Source

Drain

23

FinWidthRequirement
MeasuredFinFET DIBL

Toadequately
suppressDIBL,
Lg/Wfin >1.5
Challengefor
lithography!

N.Lindert etal.(UCBerkeley),IEEEElectronDeviceLetters,Vol.22,pp.487489,2001

24

SubLithographicFinPatterning
SpacerLithography
a.k.a.SidewallImageTransfer(SIT)andSelfAlignedDoublePatterning(SADP)
1. Deposit & pattern sacrificial layer

3. Etch back mask layer

to form spacers

SOI

SOI

BOX

BOX

2. Deposit mask layer (SiO2 or Si3N4)

4. Remove sacrificial layer;

etch SOI layer to form fins

SOI

fins

BOX

BOX

Note that fin pitch is 1/2 that of patterned layer

25

BenefitsofSpacerLithography
Spacerlitho.providesforbetterCDcontrolanduniformfinwidth

SEMimageof
FinFET with
spacerdefinedfins:
Y.K.Choietal.(UCBerkeley),IEEETrans.ElectronDevices,Vol.49, pp.436441,2002

26

SpacerDefinedFinFETs
Y.K.Choi,N.Lindert,P.Xuan,S.Tang,D.Ha,E.Anderson,T.J.King,J.Bokor,andC.Hu,
"Sub20nmCMOSFinFET technologies,
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.421424,2001

Lg =60nm,Wfin =40nm
TransferCharacteristics
OutputCharacteristics

27

2001:15nmFinFETs
-2

10

-4

10

-6

10

-8

10

TransferCharacteristics

-2

Vd=-1.0 V P+Si0.4Ge0.6 Vd=1.0 V

Gate
Vd=0.05 V

Vd=-0.05 V
N-body=
18
-3
2x10 cm

10

-6

10
10

-10

10

-4

-8

-10

10

-12

10

10

NMOS

PMOS

-1.0 -0.5 0.0

0.5

1.0

1.5

Gate Voltage, Vg [V]

-12

10
2.0

Drain Current, Id[uA/um]

Drain Current, Id [A/um]

Y.K.Choi,N.Lindert,P.Xuan,S.Tang,D.Ha,E.Anderson,T.J.King,J.Bokor,C.Hu,
"Sub20nmCMOSFinFET technologies,
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.421424,2001

OutputCharacteristics
600
500

600

PMOS

400

|Vg-Vt|=1.2V

NMOS

400

Voltage step
: 0.2V

300

500

300

200

200

100

100

0
-1.5 -1.0 -0.5 0.0

0.5

1.0

0
1.5

Drain Voltage, Vd [V]

Wfin =10nm;Tox =2.1nm

28

2002:10nmFinFETs
SEM
image:

B.Yu,L.Chang,S.Ahmed,H.Wang,S.Bell,C.Y.Yang,C.Tabery,
C.Hu,T.J.King,J.Bokor,M.R.Lin,andD.Kyser,
"FinFET scalingto10nmgatelength,"
InternationalElectronDevicesMeetingTechnicalDigest,pp.251254,2002

OutputCharacteristics
TEMimages

Thesedeviceswere
fabricatedatAMD,using
opticallithography.
29

HoleMobilityComparison
MeasuredFieldEffectHoleMobility
Mobility(cm2/V-sec)

160
140

Vg-Vth=.8V

120

<100> channel

DGFEThashigherhole
mobilityduetolower
transverseelectricfield

100
80

FinFET

Forthesamegate
overdrive,holemobility
inDGFinFET is2 thatin
acontrolbulkFET

60
Bulk FET

40
20
0
0

0.5
Effective Field (MV/cm)

30

FinFET ProcessRefinements
Y.K.Choi,L.Chang,P.Ranade,J.Lee,D.Ha,S.Balasubramanian,A.Agarwal,T.J.King,andJ.Bokor,
"FinFET processrefinementsforimprovedmobilityandgateworkfunctionengineering,"
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.259262,2002

Finsidewallsmootheningfor
improvedcarriermobilities

Gateworkfunctiontuning
forVTH adjustment

31

FinFETReliability

Id / Id [%]

Y.K.Choi,D.Ha,J.Bokor,andT.J.King,ReliabilitystudyofCMOSFinFETs,
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.177180,2003

30

StressBiasCondition:Vg=Vd=2.0V

20

Narrowerfin improved
hotcarrier(HC) immunity

Lg=80nm

10

HClifetimeandoxideQBD
arealsoimprovedby
smootheningtheSifin
sidewallsurfaces(byH2
annealing)

VT / VT [%]

0
-10
-20
-30
0
10

W fin=18nm
W fin=34nm
1

W fin=26nm
W fin=42nm
2

10
10
Stress Time [sec]

10

32

TriGateFET

Lg =60nm
Wfin =55nm
Hfin =36nm

B.Doyleetal.(Intel),IEEEElectronDeviceLetters,Vol.24,pp.263265,2003

33

SOIMultiGateMOSFETDesigns
TriGateFET
Relaxedfindimensions
WSi >Lg/2;HSi >Lg/5

HSi /Leff

FinFET
Narrowfin
WSi ~Lg/2

bodydimensions
requiredfor
DIBL=100mV/V
Tox =1.1nm

WSi /Leff

UTBFET
UltrathinSOI
HSi ~Lg/5

afterYangandFossum,IEEETrans.ElectronDevices,Vol.52,pp.11591164,2005

34

DoubleGatevs.TriGateFET
TheDoubleGateFETdoesnotrequireahighlyselective
gateetch,duetotheprotectivedielectrichardmask.
Additionalgatefringingcapacitanceislessofanissuefor
theTriGateFET,sincethetopfinsurfacecontributesto
currentconductionintheONstate.
DoubleGateFET

TriGateFET

channel
afterM.Khare,2010IEDMShortCourse

35

IndependentGateOperation
ThegateelectrodesofadoublegateFETcanbeisolated
byamaskedetch,toallowforseparatebiasing.
Onegateisusedforswitching.
TheothergateisusedforVTH control.

Drain

Gate1
Gate2

Back
Gated
FET

Source

D.M.Friedetal.(CornellU.),
IEEEElectronDeviceLetters,
Vol.25,pp.199201,2004

L.Mathewetal.(Freescale Semiconductor),
2004 IEEEInternationalSOIConference
36

BulkFinFET
FinFETs canbemade
onbulkSiwafers
lowercost
improvedthermal
conduction

withsupersteep
retrogradewell
(SSRW)orpunch
throughstopperat
thebaseofthefins
90nmLg FinFETs
demonstrated
Wfin =80nm
Hfin =100nm
DIBL=25mV
C.H.Leeetal. (Samsung),SymposiumonVLSITechnologyDigest, pp.130131,2004

37

Bulkvs. SOIFinFET
(comparedtoSOIFinFET)

H.Bu (IBM),2011IEEEInternationalSOIConference

38

2004:Highk/MetalGateFinFET
D.Ha,H.Takeuchi,Y.K.Choi,T.J.King,W.Bai,
D.L.Kwong,A.Agarwal,andM.Ameen,
MolybdenumgateHfO2 CMOSFinFET technology,
IEEEInternationalElectronDevicesMeetingTechnical
Digest,pp.643646,2004

39

IDSAT BoostwithEmbeddedSiGe S/D

Processflow:

IOFF vs.ION

Lg =50nm
Wfin =35nm
Hfin =65nm

25%improvementinIDSAT
isachievedwithsilicon
germaniumsource/drain,
dueinpart toreduced
parasiticresistance

P.Verheyen etal.(IMEC),SymposiumonVLSITechnologyDigest,pp.194195,2005

40

FinDesignConsiderations
FinWidth

GateLength

Limitedbyetchtechnology
Tradeoff:layoutefficiency
vs. designflexibility

Drain

FinHeight

Source

DeterminesDIBL

FinPitch
Determineslayoutarea
FinHeight
Pfin
FinWidth
LimitsS/Dimplanttiltangle
Tradeoff:performancevs.layoutefficiency
41

FinFETLayout
LayoutissimilartothatofconventionalMOSFET,except
Pfin
thatthechannelwidthisquantized:
Source

Gate

Source

Gate
Drain

Drain

Source

Source

BulkSiMOSFET

FinFET

TheS/Dfinscanbemergedbyselectiveepitaxy:

M.Guillorn etal.(IBM),Symp.VLSITechnology2008

Intel
Corp.
42

ImpactofFinLayoutOrientation

Ifthefinisoriented||or to
thewaferflat,thechannel
surfacesliealong(110)planes.
lowerelectronmobility
higherholemobility
(Seriesresistanceismore
significantatshorterLg.)

Ifthefinisoriented45 tothe
waferflat,thechannelsurfaces
liealong(100)planes.

L.Changetal.(IBM),SISPAD 2004

43

FinFETBasedSRAMDesign
BestPaperAward:Z.Guo,S.Balasubramanian,R.Zlatanovici,T.J.King,andB.Nikolic,
FinFETbasedSRAMdesign,IntlSymposiumonLowPowerElectronicsandDesign,pp.27,2005

6TSRAMCellDesigns

CellLayouts

ButterflyCurves

Reducedcellareawith
independentlygatedPGs

44

StateoftheArtFinFETs
22nm/20nmhighperformance
CMOStechnology
Lg =25nm
XTEMImagesofFin

C.C.Wuetal.(TSMC),IEDM 2010

45

LookingtotheFuture
2010InternationalTechnologyRoadmapforSemiconductors(ITRS)
2012
GateLength

2014

2016

2018

2020

2022

2024

24nm 18nm 15nm 13nm 11nm 10nm

7nm

GateOxide
Thickness,TOX (nm)
DriveCurrent,IDSAT

EndofRoadmap
(always~15yrs away!)

46

FinFET vs.UTBBSOIMOSFET
CrosssectionalTEMviews
of25nmUTBSOIdevices
NFET

TSi =5nm

PFET

TSi =5nm

K.Chengetal.(IBM),SymposiumonVLSI
TechnologyDigest,pp.128129,2011

B.Doris(IBM),2011
IEEEInternational
SOIConference

*C.C.Wuetal.
(TSMC),IEDM
2010

47

ProjectionsforFinFET vs. UTBBSOIMOSFETs

NMOS:
Electron
Mobility

Electron Mobility (cm2/V.s)

300

FDSOI

Open: FinFET
Closed: FDSOI

250

Unstrained
Longi.
Trans.
Vertical

200

150

Unstrained
Longi.
Trans.
Vertical

FinFET
100
12

12

12

Unstrained
Longi.
Trans.
Vertical

12

13

2x10
4x10 6x10 8x10 10
-2
Inversion Charge Concentration (cm )

Hole
Mobility

Hole Mobility (cm2/V.s)

TechnologyNode:

PMOS:

Open: FinFET
Closed: FDSOI

300
270
240
210
180

20nm
tSOI =7nm; tFIN =10nm
Unstrained
Longi.
Trans.
Vertical

12

12

12

12

13

2x10
4x10 6x10 8x10 10
-2
Inversion Charge Concentration (cm )

14/16nm
tSOI =5nm; tFIN =7.5nm

FinFET

Unstrained
Longi.
Trans.
Vertical

12

12

12

13

10/12nm
tSOI =3.5nm; tFIN =5nm
0
0
0
0
0

FinFET

12

2x10
4x10
6x10 8x10 10
-2
Inversion Charge Concentration (cm )

150

120

90

Unstrained
Longi.
Trans.
Vertical

FinFET
FDSOI

FDSOI

60

12

12

FDSOI
12

12

13

2x10
4x10 6x10 8x10 10
-2
Inversion Charge Concentration (cm )

12

12

12

12

13

2x10
4x10 6x10 8x10 10
-2
Inversion Charge Concentration (cm )

12

12

12

12

13

2x10
4x10 6x10 8x10 10
-2
Inversion Charge Concentration (cm )

N.Xu etal. (UCBerkeley),IEEEElectronDeviceLetters,Vol.33,pp.318320,2012

48

RemainingFinFET Challenges
VTH adjustment
Requiresgateworkfunction(WF)orLeff tuning
DynamicVTH controlisnotpossibleforhighaspectratiomultifindevices

Fringingcapacitancebetweengateandtop/bottomofS/D
Mitigatedbyminimizingfinpitchand
usingviacontacted,mergedS/D
M.Guillorn,Symp.VLSITechnology2008

Parasiticresistance
UniformS/Ddopingis
difficulttoachievewith
conventionalimplantation

Conformaldopingisneeded
e.g.Y.Sasaki,IEDM2008

H.Kawasaki,IEDM2008

Variability
Performanceisverysensitivetofinwidth
WFvariationdominantforundoped channel
T.Matsukawa,Symp.VLSITechnology 2008
49

RandomDopantFluctuationEffects
Channel/bodydopingcanbeeliminatedtomitigateRDFeffects.
However,duetosource/draindoping,atradeoffexistsbetween
performance&RDFtoleranceforLg <10nm:
IONvs.TSi

IOFF andVT vs.TSi

1E-4

SD = 3nm

75
VT (mV)

IOFF (A / m)

1E-6

50

1E-8

Lg =9nm,EOT=0.7nm

1E-10

25
4.5

SD = 3nm

100

5.5

TSi (nm)

6.5

ION (mA / m)

SOIFinFET w/atomistic
S/Dgradientregions:

0.8

0.4

4.5

5.5

TSi (nm)

V. Varadarajan et al. (UC-Berkeley), IEEE Silicon Nanoelectronics Workshop, 2006

6.5

50

HSi /Leff

Bulkvs.SOIMultiGateFETDesign
Toeasethefinwidth
requirement,thefin
heightshouldbe
reduced.
trigateSOI(thickBOX)
[J.G.Fossum etal.,IEDM 2004]

WSi /Leff

Thebulktrigatedesign
hasthemostrelaxed
bodydimension
requirements.
SSRW(atthebaseof
thefin)improves
electrostaticintegrity

X.Sunetal.(UCBerkeley),IEEEElectronDeviceLetters, Vol.29,pp.491493,2008

51

SOIMOSFETEvolution
TheGateAllAround(GAA)structureprovidesforthegreatest
capacitivecouplingbetweenthegateandthechannel.

http://www.electroiq.com/content/eiq-2/en/articles/sst/print/volume-51/issue-5/features/nanotechnology/fully-gate-all-around-silicon-nanowire-cmos-devices.html

52

ScalingtotheEndoftheRoadmap
32nm
planar

22nm
multigate
segmentedchannel

beyond10nm
stackednanowires

3D:

IntelCorp.

quasiplanar:

P.Packanetal.(Intel),
IEDM2009

B.Ho(UCB),ISDRS 2011

C.Dupretal.(CEALETI)
IEDM2008

Stackedgateallaround
(GAA)FETsachievethe
highestlayoutefficiency.
53

Summary
TheFinFET wasoriginallydevelopedformanufactureof
selfaligneddoublegateMOSFETs,toaddresstheneed
forimprovedgatecontroltosuppressIOFF,DIBLand
processinducedvariabilityforLg <25nm.
TriGateandBulkvariationsoftheFinFET havebeen
developedtoimprovemanufacturabilityandcost.
Ithastaken~10yearstobring3Dtransistorsintovolume
production.

MultigateMOSFETsprovideapathwaytoachieving
lowerpowerand/orimprovedperformance.
FurtherevolutionoftheMOSFETtoastackedchannel
structuremayoccurbytheendoftheroadmap.
54

Acknowledgments
CollaboratorsatUCBerkeley
Profs.Hu,King,Bokor

Prof.
Subramanian Digh Hisamoto

Hideki Takeuchi Xuejue Huang

Wen-Chin Lee Jakub Kedzierski

YangKyu
Choi

Stephen Tang

Peiqi Xuan

Leland Chang

Nick Lindert

Sriram
Kyoungsub
Balasubramanian Zheng Guo Pushkar Ranade, Charles Kuo, Daewon Ha
Shin

Radu
Zlatanovici

Prof. Nikolic

Earlyresearchfunding:DARPA,SRC,AMD
UCBerkeleyMicrofabrication Laboratory
(birthplaceoftheFinFET)
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