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T. Esther Rani,

M. Asha Rani,

Dr. Rameshwar rao,

ECE Department,CVR College of

Hyderabad, India

ECE Department,JNT University

Hyderabad, India

ECE Department,Osmania
Hyderabad, India

signal lines (such as fire alarm wires) lowering the cost of

the end-product. As a result, low power consumption has
become a key parameter of microcontroller designs.
Large gains, in terms of performance and silicon area,
have been made for digital processors, microprocessors,
DSPs (Digital Signal Processors), ASICs (Application
Specific integrated circuits), etc. In general, "small area" and
"high performance" are two constraints for any design. The
IC designers activities have been involved in trading off
these constraints. In fact, power considerations have been the
ultimate design criteria in special portable applications such
as wristwatches and pacemakers for a long time. The
objective in these applications is minimum power for
maximum battery life time[12].
Low-power design is not only needed for portable
applications but also to reduce the power of highperformance systems. With large integration density and
improved speed of operation, systems with high frequencies
are emerging. These systems are using high-speed products
such as microprocessors. The cost associated with
packaging, cooling and fans required by these systems to
remove the heat are increasing significantly[3]. Existing
leakage-reduction techniques are targeting circuits that are
not constrained by delay requirements, so that the delay
margin can be used up for power reduction. Being aware of
the leakage current of advanced processes, leakage should be
reduced by increasing Vth of some MOS devices.

Abstract In this paper, we proposed a low power 1-bit full

adder (FA) with 10-transistors and this is used in the design
ALU. Various 16-bit ALUs are designed and compared. By
using low power 1-bit full adder in the implementation of ALU,
the power and area are greatly reduced to more than 70%
compared to conventional design and 30% compared to
transmission gates. So, the design is attributed as an area
efficient and low power ALU. This design does not compromise
for the speed as the delay of the full adder is minimized thus
the overall delay. The leakage power of the design is also
reduced by designing the full adder with less number of power
supply to ground connections. In fact, power considerations
have been the ultimate design criteria in special portable
applications. For large number of computations, efficient ALU
is to be designed for minimum area and low-power without
compromising the high speed.
Keywords-ALU;CMOS; transmission gates; 10TFA, leakage



Integrated circuit technology is the enabling technology

for a whole host of innovative devices and systems that have
changed the way we live. In the past, the major concerns of
the VLSI designer were area, performance, cost and
reliability. Power consideration was mostly of only
secondary importance. In recent years, however, this has
begun to change and increasingly power is being given
comparable weight to area and speed considerations. Several
factors have contributed to this trend. Perhaps the primary
driving factor has been the remarkable success and growth of
the class of personal computing devices like portable
desktops, audio and video-based multimedia products,
wireless communications systems like personal digital
assistants and personal communicators which demand highspeed computation and complex functionality with low
power consumption. In the future, it can be extrapolated that
a 10cm microprocessor, clocked at 500 MHz (which is a not
too aggressive estimate for the next decade) would consume
about 300W. The cost associated with packaging and cooling
of such devices is going too high. In addition to cost, there is
an issue of reliability. High power systems often run hot, and
high temperature tends to exacerbate several silicon failure
mechanisms. Every 10C increase in operating temperature
roughly doubles a components failure rate[11].
Low power also leads to smaller power supplies, less
expensive batteries, and enables products to be powered by



Power can be minimized at either system level or

architecture level or algorithm level or micro architecture
level or gate level or circuit level. Here, we made an attempt
to reduce the power at circuit level.
Each design consists of number of micro architectures.
Each micro architecture consists of number of gates. For
CMOS implementation of the gate, the pull-up and pulldown of the circuit must be realized. A conventional full
adder with XOR gates, AND gates and OR gates must be
realized with corresponding pull-up networks, and pull-down
networks. A conventional CMOS full adder consists of 28
transistors[1]. But, here we have designed a full adder only
with 10 number of transistors, which occupies very less area
and also consumes very less power.
The adder is one of the most important components of a
CPU. Arithmetic logic unit (ALU), floating-point unit and
address generation like cache or memory access unit use it.
In addition, full-adders are important components in other

978-1-4244 -8679-3/11/$26.00 2011 IEEE


applications such as digital signal processors (DSP)

architectures and microprocessors also it is useful.
Arithmetic functions such as addition, subtraction,
multiplication and division are some examples, which use
adder as a main building block[7]. As a result, design of a
high-performance full-adder is very useful and important. On
the other hand, increasing demand for portable equipment
such as cellular phones, personal digital assistant (PDA), and
notebook personal computer, shows the need of using area
and power efficient VLSI circuits. Low-power and highspeed adder cells are used in battery operation based devices.
The full adder performs the computing function of the
ALU. A full adder could be defined as a combinational
circuit that forms the arithmetic sum of three input bits. It
consists of three inputs and two outputs[2]. Figure 1 Shows
the logic level diagram of a full adder. The Boolean
expressions for the SUM and CARRY bits are as shown

The conventional full adder which consists of 28

transistors is shown in figure2. Another full adder circuit
which consists of 14 transistors using transmission gates is
also shown in figure3. In ALU, full adder forms the core of
the entire design.

Figure2. Static complementary CMOS adders using 28 transistors.


SUM bit is the EXOR function of all three inputs and

CARRY bit is the AND function of the three inputs. The
truth table of a full adder is shown in Table 2.1. The truth
table also indicates the status of the CARRY bit. If carry bit
has been generated or deleted or propagated, depending on
the status of input bits A and B, the CARRY bit is either
generated or deleted or propagated. If either one of A or B
input is 1, then the previous carry is just propagated, as the
sum of A and B is 1[5].

Figure3. Fourteen Transistor (14T) Full adder with Transmission Gates

A. 10 Transistor Full Adder Design(10TFA)

The proposed 10TFA also takes the three inputs A, B and
Cin.. The third input Cin represents carry input to the first
stage. The outputs are SUM and CARRY. The adder circuit
diagram of the new 1-bit full adder is shown in figure4. The
designed adder implements equations 1 and 2 using
complementary CMOS and MUX based design logic with 10

Figure1. Logic level diagram of a full adder.

Table I Truth table of full adder

Figure4. 10 Transistor Full Adder(10TFA)

The full adder circuit uses 0.18m CMOS process

technology, which provides transistors with three
characteristics, namely high-speed, low-voltage and lowleakage. As the main target of this design is to minimize
Power, so the transistors are selected for it accordingly. The
typical supply voltage for this process is 1.8 V. The 10transistor 1-bit full adder is designed at transistor level, using
0.18m CMOS process technology. Based on the simulation,
the 10-transistor 1-bit full adder consumes 6.2995W Power
where as a conventional full adder consumes 16.675W,
which shows a 62.2% of power savings.

Table1 shows the carry status of full adder. If both A and
B are 1s then carry is generated because summing A and B
would make output SUM 0 and CARRY 1. If both A and
B are 0s then summing A and B would give us 0 and any
previous carry is added to this SUM making CARRY bit 0.
This is in effect deleting the CARRY[6].


The arithmetic logic unit (ALU) is one of the main
components inside a microprocessor. It is responsible for


performing arithmetic and logic operations such as addition,

subtraction, increment, decrement, logical AND, logical OR,
logical XOR and logical XNOR. An ALU is a digital circuit
that performs arithmetic and logical operations. The ALU is
a fundamental building block of the Central Processing Unit
(CPU) of a computer, and even the simplest microprocessors
contain one. The processors found inside modern CPUs and
Graphics Processing Units (GPUs) have inside them very
powerful ALUs.
A. ALU Design and Operation
We have designed ALU in three different ways by using
multiplexers and full adder circuit. The input and output
sections consist of 4x1 and 2x1 multiplexers and logic is
implemented by using full adder. In the first design
multiplexers and full adder are implemented using the
CMOS logic. In the second design the multiplexers are
implemented using transmission gates to reduce the area. In
the third design the multiplexers are designed with pass
transistors and full adder is designed with 10TFA both for
minimum area and low power. The pass transistor design
reduces the parasitic capacitances and results in fast circuits.
A set of three select signals have been incorporated in the
design to determine the operation being performed and the
inputs and outputs being selected. Figure 5 shows the block
diagram of 4-bit ALU with the CARRY bit cascading all the
way from first stage to fourth stage. The ALU consists of
eight 4x1 multiplexers, four 2x1 multiplexers and four full
adders. The 4-bit ALU is designed in 180nm, n-well CMOS
technology. For the INCREMENT and DECREMENT
operations logic 1 and logic 0 are applied as inputs
respectively. The complement of B is used for
SUBTRACTION operation. The full adder performs the
SUBTRACT operation by twos complement method. An
INCREMENT operation is analyzed as adding 1 to the
addend and DECREMENT is seen as a subtraction
The outputs from the full adder are SUM, EXOR,
EXNOR, AND & OR. Based on the condition of the select
signals, the multiplexer stage selects the appropriate inputs
and gives it to the full adder. The full adder computes the
results. The multiplexer at the output stage selects the
appropriate output and sends it out. Table 2 shows the truth
table for the operations performed by the ALU based on the
status of the select signals.


Table II 4-bit ALU










A. Multiplexer Design
The multiplexers have been used in the ALU design for
input and output signals selection. The multiplexer is
implemented using pass transistors. This design is simple
and efficient in terms of area and timing. Figure6 shows the
circuit level diagram of the 2x1 MUX. The output of the 4x1
multiplexer stage is passed as input to the full adder. A
combination of the 2x1 MUX and 4x1 MUX at the input and
output stage selects the signals depending on the operation
being performed.

Figure6. Circuit level diagram of a 2x1 multiplexer.

Transmission gates select one of the inputs based on the

value of the control signal. The input and select signals have
been named as S0 and S1 respectively, with the subscript n
indicating the correct signal number.
Table III

2x1 Multiplexer

The input and the output stages have a combination of

2x1 multiplexer and 4x1 multiplexer to select one signal
from a set of four signals. The select signals are S0, S1 and
S2. Signal S2 determines if the operation being performed is
arithmetic or logical. The select signals S0 and S1 pick one
of the four inputs or output signals and hence determine
which of the four arithmetic or logical operations should be
performed. For S2=0, one of the four arithmetic operations is
performed and for S2=1, one of the four logical operations is
performed. Figure 7 and figure 8 represents the block
diagram of multiplexer logic at the input and output stages.

Figure5. Block diagram of a 4-bit ALU.


Figure7. Block diagram of multiplexer logic at the input stage.

Figure11. Symbol of 16-bit ALU.

Figure8. Block diagram of multiplexer logic at the output stage

Figure12. Test bench of 16-bit ALU.

B. Schematic design of 4-bit ALU

For the schematic of arithmetic and logic unit, we have
used the schematic editor i.e., Virtuoso Composer
Schematic. It describes the transistor level or higher
abstraction levels of the circuit. It also can be drawn
connectivity between the components and describes aspect
ratios of the transistor can be modified along with the design.
The figure 9 represents the complete schematics view of

C. Simulation Results of 16-bit ALU

The ALU consists of 16-outputs(f0-f15), carry output
(Cout) and two 16-bit inputs, three selection lines s0,s1 and
s3. Depending on s2=1 arithmetic operation will be
performed and s2=0 logical operation will be performed.
The simulation results are observed to be correct for different
D. Power Consumption
The total Power Consumption of a CMOS circuit
includes : dynamic Power Consumption, static Power
Consumption and short circuit power consumption. The last
two items are neglected due to their low contribution to the
power. The dominant factor is the dynamic power based on
the equation,
P= CLfVdd2.
The instantaneous power P (t) drawn from the power
supply is proportional to the supply current Idd (t) and the
supply voltage Vdd (t). P (t) =Idd (t) Vdd (t)
The energy consumed over that time interval T is the
integral of instantaneous power.E= Idd (t) Vdd (t)
This is the area under the current multiplied by voltage at
the power supply. The average power used over this interval
is the energy divided by the time. So in order to measure the
power in the circuit we need to able to measure the current
from the power supply, plot that curve over time, integrate
under that curve and multiply with Vdd.The energy and
power values for the individual cells of the ALU and the
total energy and power values of the ALU designed in
different ways is listed in the following tables IV and V.

Figure 9. Schematic of 4-bit ALU.

A symbol can be used as a building block to simplify the

design of another module at the hierarchical level. It is
equivalent to a black box when only inputs and outputs pins
are seen and this symbol is also used for simulation. The 4bit ALU consists of two 4-bit inputs, three selecting lines,
and one carry input one carry output and 4-output bits. So the
symbol of ALU is created by COMPOSER SYMBOL in
Cadence tool. It consists of four outputs and one carryout
(out0, out1, out2, out3, cout) and two 4-bit inputs (a0, a1,
a2, a3, b0, b1, b2, b3) and three selection lines (s0,s1,s2)
depends on selection line (s2) either arithmetic or logical
will be performed. The results are observed to be correct for
various inputs. The schematic, symbol and test bench of 16bit ALU is shown in figure 10, figure 11 and figure 12

Table IV. Power and Energy for the individual cells of ALU.
y (pJ)
2x1 MUX
4x1 MUX
Logical MUX
Carry generator
Conventional Full
2x1 MUX with
transmission gates
4x1 MUX with
transmission gates
6. Gates
Logical MUX with
transmission gates
Carry generator
with transmission

Figure10. Schematic of 16-bit ALU.



n & p- type

10 Transistor full





Table V Comparison of Power and Energy for different ALUs

ALU with
ALU with
ALU with




CMOS gates

Transmission gates



&10-Transistor full


full adder













In this work, a 16-bit ALU is designed at transistor level

for low power and minimum area. In this work much efforts
are spent on the design of full adder circuit. Different
topologies of full adders are studied and compared. A 1-bit
full adder with 10-transistors is chosen for its lowest Power
Consumption and minimum possible area. With this full
adder, the leakage power is also very less as the number of
power supply to ground connections are greatly reduced. The
power consumption of 16-bit ALU with 10 transistor full
adder is observed to be 1197.5w.





The authors would like to thank the management, Prof.

Magdy A Bayomi center for VLSI design,CVR College of
Engineering for providing the Cadence tools.



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