IJSTE - International Journal of Science Technology & Engineering | Volume 2 | Issue 11 | May 2016

ISSN (online): 2349-784X

High Voltage Junctionless FET with Improved

DC Performance Compared to LDMOS
Ashish Kumar
Department of Electrical Engineering
Indian Institute of Technology, Delhi, 110 016 India

Palash Nag
Department of Electrical Engineering
Indian Institute of Technology, Delhi, 110 016 India

M. Jagadesh Kumar
Senior Member, IEEE
Department of Electrical Engineering
Indian Institute of Technology, Delhi, 110 016 India

Abstract
In this paper, using 2D simulations, we propose a high voltage double gate junction less field effect transistor (JLFET) with an
OFF-state breakdown voltage similar to that of a conventional LDMOS. Our simulation results indicate that the proposed JLFET
shows approximately twice the ON-state current compared to the LDMOS and has a high ON-state breakdown voltage (~200V).
It also exhibits a lower ON-resistance and a better trans conductance. Therefore, the proposed JLFET is expected to be a low cost
and better performing replacement to the LDMOS.
Keywords: Junction less FET (JLFET), LDMOS, Power, High Voltage, ON-Resistance, Trans conductance, Breakdown
Voltage, ON-state current
________________________________________________________________________________________________________
I.

INTRODUCTION

Laterally double diffused metal oxide semiconductor (LDMOS) transistors are widely used for high power applications due to
their good breakdown characteristics and high ON-state current [1], [2]. However, the fabrication of an LDMOS involves creation
of junctions and regions with variable doping. This requires ion implantation and expensive ultrafast annealing which increases
the thermal budget. Reported methods used to improve the characteristics of an LDMOS complicate the device structure further
and fabrication becomes even more challenging [3]-[8].
Recently, there has been a lot of interest in studying the junction less field effect transistors (JLFETs) due to their low thermal
budget and simpler fabrication process compared to the conventional MOSFETs [9], [10]. These transistors use the bulk conduction
mechanism and are free from any junctions. They also exhibit high ON-state currents due to the heavy channel doping(~1019cm3
). The low voltage characteristics of JLFETs have been studied extensively [11]-[14]. Although the high voltage characteristics
of JLFETs have been reported recently [15], there has been no study on the possibility of using the high voltage JLFETs as a
replacement for LDMOS. The aim of this study is, therefore, to explore if JLFETs with an OFF-state breakdown voltage similar
to that of an LDMOS would exhibit an improved electrical performance. Using 2D- TCAD simulations, we demonstrate for the
first time that a high voltage JLFET exhibits twice the ON-state current, better

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High Voltage Junctionless FET with Improved DC Performance Compared to LDMOS

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Fig. 1: Schematic view of (a) conventional LDMOS and (b) JLFET used in our study.

trans conductance and lower ON-resistance compared to an LDMOS with a corresponding OFF-state breakdown voltage. Our
results may provide the incentive for further experimental exploration of the proposed device.
II. DEVICE STRUCTURE AND OPERATION
The schematic view of a conventional LDMOS and that of the junction less transistor is shown in Fig. 1. The device parameters
used in our simulations are given in Table I. The LDMOS parameters are taken from [4]. The JLFET parameters are chosen to
give an OFF-state breakdown voltage similar to that of an LDMOS in [4].
In any conventional MOSFET, the majority of applied voltage drops across the depletion region at the junctions. If the electric
field at these junctions reaches a critical value, it can lead to the breakdown of the device. However, in a junction less FET, the
situation is different. In the ON-state, the potential due to the applied voltage is uniformly distributed throughout the length of the
silicon film in a JLFET. Also, the doping gradient between the channel and the source or drain region is lower in a JLFET compared
to that of a conventional MOSFET. Therefore, in the OFF-state, the JLFET has a lower electric field in the silicon film leading to
a much higher breakdown voltage [15].
Table 1
Simulation Parameters
PARAMETER
JLFET
Gate Oxide Thickness, tOX 12 nm (HfO2)
Gate Length, LG
3 m
Gate Material
P + Poly
Channel Length
3 m
Drift Region Length
Silicon Film Thickness
5 nm
Buried Oxide Thickness
Silicon Film Doping
21019 cm-3
Source/Drain Doping
21019 cm-3
P-body Doping
Drift Region Doping
Threshold Voltage
0.3 V

LDMOS [4]
50 nm (SiO2)
2.25 m
N + Poly
0.5 m
3.5 m
200 nm
400 nm
11019 cm-3
11017 cm-3
41016 cm-3
1.85 V

Fig. 2: Breakdown voltage characteristics of (a) the JLFET and (b) the conventional LDMOS.

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High Voltage Junctionless FET with Improved DC Performance Compared to LDMOS

(IJSTE/ Volume 2 / Issue 11 / 133)

Fig. 3: Output characteristics of (a) the JLFET and (b) the conventional LDMOS.

III. RESULTS AND DISCUSSION

All the simulations were done in Sentaurus TCAD [17]. Mobility effects are taken into account by using a doping and field
dependent model in our simulations. We have used avalanche breakdown model for simulating the breakdown characteristics.
Band gap narrowing (BGN), Shockley-Read-Hall (SRH) recombination models and band to band tunnelling model have also been
enabled. Simulation models have been calibrated by reproducing the LDMOS results and JLFET results reported in [4] and [16],
respectively.
The OFF-state breakdown voltage for both the JLFET and the conventional LDMOS is shown in Fig. 2. The JLFET has a

Fig. 4: ON-resistance of (a) the JLFET and (b) the conventional LDMOS.

Fig. 5: Trans conductance variation of the JLFET and the conventional LDMOS.

Breakdown voltage of 28.5 V (Fig. 2(a)) whereas the conventional LDMOS has a breakdown voltage of 29.6 V (Fig. 2(b)). The
output characteristics of the two devices are shown in Fig. 3. The ON-state current for the junction less transistor is twice that of
the conventional LDMOS and it also shows high breakdown voltages (>200V) in the ON-state. This can be attributed to the fact
that when the JLFET is turned ON, it behaves like a resistor due to the absence of junctions [15]. Therefore, the electric field is
uniformly distributed and reduces the impact-ionization. Hence, the ON-state breakdown voltage is much higher than that of the
conventional LDMOS.
The ON-resistance of the proposed device is improved by 27.82% as compared to the conventional LDMOS as shown in Fig.
4. This is because of the significantly high channel doping in the JLFET.
While estimating the trans conductance, we need to consider both the peak trans conductance and the gate voltage range for
which the transistor responds. A higher value of both these attributes is desirable [4]. As shown in Fig. 5, the peak trans conductance

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High Voltage Junctionless FET with Improved DC Performance Compared to LDMOS

(IJSTE/ Volume 2 / Issue 11 / 133)

has improved by 54% and the range of gate voltage has increased by 133% compared to the LDMOS. These improvements are
attributed to the reduced ON-resistance in the case of JLFETs.
IV. CONCLUSION
Using 2D simulations, we demonstrate in this work, that a JLFET with an OFF-state breakdown voltage similar to that of an
LDMOS performs better on parameters such as output characteristics, ON-resistance and trans conductance. Our results indicate
that for a JLFET, the ON-state current improves by about 100%, the ON-resistance decreases by 27.82%, the peak trans
conductance increases by 54% and the gate voltage range for which the transistor responds increases by 133%. Further, unlike the
LDMOS, the JLFET exhibits a high ON-state breakdown voltage. This makes the JLFET a possible replacement to the LDMOS
as a power transistor.
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