*

*
* HC12 I/O register locations (9s12dp256)
*
*
porta:
equ 0 ;port a = address lines a8 - a15
portb:
equ 1 ;port b = address lines a0 - a7
ddra:
equ 2 ;port a direction register
ddrb:
equ 3 ;port a direction register
porte:
ddre:
pear:
mode:
pucr:
rdriv:
ebictl:

equ
equ
equ
equ
equ
equ
equ

8
9
$a
$b
$c
$d
$e

;port e = mode,irqandcontrolsignals
;port e direction register
;port e assignments
;mode register
;port pull-up control register
;port reduced drive control register
;e stretch control

initrm:
initrg:
initee:
misc:
mtst0:
itcr:
itest:
mtst1:

equ
equ
equ
equ
equ
equ
equ
equ

$10
$11
$12
$13
$14
$15
$16
$17

;ram location register

;register location register
;eeprom location register
;miscellaneous mapping control
; reserved
;interrupt test control register
;interrupt test register
; reserved

partidh:
partidl:
memsiz0:
memsiz1:
intcr:
hprio:

equ
equ
equ
equ
equ
equ

$1a
$1b
$1c
$1d
$1e
$1f

;part id high
;part id low
;memory size
;memory size
;interrupt control register
;high priority reg

bkpct0:
bkpct1:
bkp0x:
bkp0h:
brp0l:
bkp1x:
bkp1h:
brp1l:
ppage:

equ
equ
equ
equ
equ
equ
equ
equ
equ

$28
$29
$2a
$2b
$2c
$2d
$2e
$2f
$30

;break control register

;break control register
; break 0 index register
; break 0 pointer high
; break 0 pointer low
; break 1 index register
; break 1 pointer high
; break 1 pointer low
;program page register

portk:
ddrk:
synr:
refdv:
ctflg:
crgflg:
crgint:
clksel:
pllctl:
rtictl:
copctl:
forbyp:
ctctl:
armcop:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$32
$33
$34
$35
$36
$37
$38
$39
$3a
$3b
$3c
$3d
$3e
$3f

;port k data
;port k direction
; synthesizer / multiplier register
; reference divider register
; reserved
; pll flags register
; pll interrupt register
; clock select register
; pll control register
;real time interrupt control
;watchdog control
;
;
;cop reset register

tios:

equ $40 ;timer input/output select

cforc:
oc7m:
oc7d:
tcnt:
*tcnt:
tscr:
ttov:
tctl1:
tctl2:
tctl3:
tctl4:
tmsk1:
tmsk2:
tflg1:
tflg2:
tc0:
tc1:
tc2:
tc3:
tc4:
tc5:
tc6:
tc7:
pactl:
paflg:
pacn3:
pacn2:
pacn1:
pacn0:
mcctl:
mcflg:
icpar:
dlyct:
icovw:
icsys:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$41
$42
$43
$44
$45
$46
$47
$48
$49
$4a
$4b
$4c
$4d
$4e
$4f
$50
$52
$54
$56
$58
$5a
$5c
$5e
$60
$61
$62
$63
$64
$65
$66
$67
$68
$69
$6a
$6b

;timer compare force

;timer output compare 7 mask
;timer output compare 7 data
;timer counter register hi
;timer counter register lo
;timer system control register
;reserved
;timer control register 1
;timer control register 2
;timer control register 3
;timer control register 4
;timer interrupt mask 1
;timer interrupt mask 2
;timer flags 1
;timer flags 2
;timer capture/compare register 0
;timer capture/compare register 1
;timer capture/compare register 2
;timer capture/compare register 3
;timer capture/compare register 4
;timer capture/compare register 5
;timer capture/compare register 6
;timer capture/compare register 7
;pulse accumulator controls
;pulse accumulator flags
;pulse accumulator counter 3
;pulse accumulator counter 2
;pulse accumulator counter 1
;pulse accumulator counter 0
;modulus down conunter control
;down counter flags
;input pulse accumulator control
;delay count to down counter
;input control overwrite register
;input control system control

timtst:

equ $6d ;timer test register

pbctl:
pbflg:
pa3h:
pa2h:
pa1h:
pa0h:
mccnt:
*mccntl:
tcoh:
tc1h:
tc2h:
tc3h:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$70
$71
$72
$73
$74
$75
$76
$77
$78
$7a
$7c
$7e

;
;
;
;
;
;
;
;
;
;
;
;

atd0ctl0:
atd0ctl1:
atd0ctl2:
atd0ctl3:
atd0ctl4:
atd0ctl5:
atd0stat:
*atd0stat
atd0test:

equ
equ
equ
equ
equ
equ
equ
equ
equ

$80
$81
$82
$83
$84
$85
$86
$87
$88

;adc
;adc
;adc
;adc
;adc
;adc
;adc
;adc
;adc

pulse accumulator b control

pulse accumulator b flags
pulse accumulator holding register
pulse accumulator holding register
pulse accumulator holding register
pulse accumulator holding register
modulus down counter register
low byte
capture 0 holding register
capture 1 holding register
capture 2 holding register
capture 3 holding register
control 0 (reserved)
control 1 (reserved)
control 2
control 3
control 4
control 5
status register hi
status register lo
test (reserved)

3
2
1
0

*atd0test

equ $89 ;

atd0dien:

equ $8d ;

portad:
adr00h:
adr01h:
adr02h:
adr03h:
adr04h:
adr05h:
adr06h:
adr07h:

equ
equ
equ
equ
equ
equ
equ
equ
equ

$8f
$90
$92
$94
$96
$98
$9a
$9c
$9e

;port adc =
;adc result
;adc result
;adc result
;adc result
;adc result
;adc result
;adc result
;adc result

pwme:
pwmpol:
pwmclk:
pwmprclk:
pwmcae:
pwmctl:
pwmtst:
pwmprsc:
pwmscla:
pwmsclb:
pwmscnta:
pwmscntb:
pwmcnt0:
pwmcnt1:
pwmcnt2:
pwmcnt3:
pwmcnt4:
pwmcnt5:
pwmcnt6:
pwmcnt7:
pwmper0:
pwmper1:
pwmper2:
pwmper3:
pwmper4:
pwmper5:
pwmper6:
pwmper7:
pwmdty0:
pwmdty1:
pwmdty2:
pwmdty3:
pwmdty4:
pwmdty5:
pwmdty6:
pwmdty7:
pwmsdn:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$a0
$a1
$a2
$a3
$a4
$a5
$a6
$a7
$a8
$a9
$aa
$ab
$ac
$ad
$ae
$af
$b0
$b1
$b2
$b3
$b4
$b5
$b6
$b7
$b8
$b9
$ba
$bb
$bc
$bd
$be
$bf
$c0
$c1
$c2
$c3
$c4

;pwm enable
;pwm polarity
;pwm clock select register
;pwm prescale clock select register
;pwm center align select register
;pwm control register
;reserved
;reserved
;pwm scale a
;pwm scale b
;reserved
;reserved
;pwm channel 0 counter
;pwm channel 1 counter
;pwm channel 2 counter
;pwm channel 3 counter
;pwm channel 4 counter
;pwm channel 5 counter
;pwm channel 6 counter
;pwm channel 7 counter
;pwm channel 0 period
;pwm channel 1 period
;pwm channel 2 period
;pwm channel 3 period
;pwm channel 4 period
;pwm channel 5 period
;pwm channel 6 period
;pwm channel 7 period
;pwm channel 0 duty cycle
;pwm channel 1 duty cycle
;pwm channel 2 duty cycle
;pwm channel 3 duty cycle
;pwm channel 0 duty cycle
;pwm channel 1 duty cycle
;pwm channel 2 duty cycle
;pwm channel 3 duty cycle
;pwm shutdown register

sc0bdh:
sc0bdl:
sc0cr1:
sc0cr2:
sc0sr1:
sc0sr2:
sc0drh:
sc0drl:

equ
equ
equ
equ
equ
equ
equ
equ

$c8
$c9
$ca
$cb
$cc
$cd
$ce
$cf

;sci
;sci
;sci
;sci
;sci
;sci
;sci
;sci

0
0
0
0
0
0
0
0

input only
0 register
1 register
2 register
3 register
4 register
5 register
6 register
7 register

baud reg hi byte

baud reg lo byte
control1 reg
control2 reg
status reg 1
status reg 2
data reg hi
data reg lo

sc1bdh:
sc1bdl:
sc1cr1:
sc1cr2:
sc1sr1:
sc1sr2:
sc1drh:
sc1drl:
spi0cr1:
spi0cr2:
spi0br:
spi0sr:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$d0
$d1
$d2
$d3
$d4
$d5
$d6
$d7
$d8
$d9
$da
$db

sp0dr:

equ $dd ;spi 0 data reg

ibad:
ibfd:
ibcr:
ibsr:
ibdr:

equ
equ
equ
equ
equ

$e0
$e1
$e2
$e3
$e4

;i2c
;i2c
;i2c
;i2c
;i2c

dlcbcr1:
dlcbsvr:
dlcbcr2:
dlcbdr:
dlcbard:
dlcbrsr:
dlcscr:
dlcbstat:
spi1cr1:
spi1cr2:
spi1br:
spi1sr:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$e8
$e9
$ea
$eb
$ec
$ed
$ee
$ef
$f0
$f1
$f2
$f3

;bdlc control regsiter 1

;bdlc state vector register
;bdlc control register 2
;bdlc data register
;bdlc analog delay register
;bdlc rate select register
;bdlc control register
;bdlc status register
;spi 1 control1 reg
;spi 1 control2 reg
;spi 1 baud reg
;spi 1 status reg hi

sp1dr:

equ $f5 ;spi 1 data reg

spi2cr1:
spi2cr2:
spi2br:
spi2sr:

equ
equ
equ
equ

sp2dr:

equ $fd ;spi 2 data reg

fclkdiv:
fsec:

equ $100 ;flash clock divider

equ $101 ;flash security register

fcnfg:
fprot:
fstat:
fcmd:

equ
equ
equ
equ

eclkdiv:

equ $110 ;eeprom clock divider

ecnfg:
eprot:
estat:
ecmd:

equ
equ
equ
equ

atd1ctl0:
atd1ctl1:

equ $120 ;adc1 control 0 (reserved)

equ $121 ;adc1 control 1 (reserved)

$f8
$f9
$fa
$fb

;sci
;sci
;sci
;sci
;sci
;sci
;sci
;sci
;spi
;spi
;spi
;spi

$103
$104
$105
$106

;spi
;spi
;spi
;spi

$113
$114
$115
$116

1
1
1
1
1
1
1
1
0
0
0
0

baud reg hi byte

baud reg lo byte
control1 reg
control2 reg
status reg 1
status reg 2
data reg hi
data reg lo
control1 reg
control2 reg
baud reg
status reg hi

bus
bus
bus
bus
bus

2
2
2
2

address register
frequency divider
control register
status register
message data register

control1 reg
control2 reg
baud reg
status reg hi

;flash
;flash
;flash
;flash

;eeprom
;eeprom
;eeprom
;eeprom

configuration register
protection register
status register
command register

configuration register
protection register
status register
command register

atd1ctl2:
atd1ctl3:
atd1ctl4:
atd1ctl5:
atd1stat:
*atd1stat
atd1test:
*atd1test

equ
equ
equ
equ
equ
equ
equ
equ

$122
$123
$124
$125
$126
$127
$128
$129

;adc1
;adc1
;adc1
;adc1
;adc1
;adc1
;adc1
;

control 2
control 3
control 4
control 5
status register hi
status register lo
test (reserved)

atddien:

equ $12d ;adc1 input enable register

portad1:
adr10h:
adr11h:
adr12h:
adr13h:
adr14h:
adr15h:
adr16h:
adr17h:
can0ctl0:
can0ctl1:
can0btr0:
can0btr1:
can0rflg:
can0rier:
can0tflg:
can0tier:
can0tarq:
can0taak:
can0tbel:
can0idac:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$12f
$130
$132
$134
$136
$138
$13a
$13c
$13e
$140
$141
$142
$143
$144
$145
$146
$147
$148
$149
$14a
$14b

;port
;adc1
;adc1
;adc1
;adc1
;adc1
;adc1
;adc1
;adc1
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0

adc1 = input only

result 0 register
result 1 register
result 2 register
result 3 register
result 4 register
result 5 register
result 6 register
result 7 register
control register 0
control register 1
bus timing register 0
bus timing register 1
receiver flags
receiver interrupt enables
transmit flags
transmit interrupt enables
transmit message abort control
transmit message abort status
transmit buffer select
identfier acceptance control

can0rerr:
can0terr:
can0ida0:
can0ida1:
can0ida2:
can0ida3:
can0idm0:
can0idm1:
can0idm2:
can0idm3:
can0ida4:
can0ida5:
can0ida6:
can0ida7:
can0idm4:
can0idm5:
can0idm6:
can0idm7:
can0rxfg:
can0txfg:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$14e
$14f
$150
$151
$152
$153
$154
$155
$156
$157
$158
$159
$15a
$15b
$15c
$15d
$15e
$15f
$160
$170

;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0
;can0

receive error counter

transmit error counter
identifier acceptance register 0
identifier acceptance register 1
identifier acceptance register 2
identifier acceptance register 3
identifier mask register 0
identifier mask register 1
identifier mask register 2
identifier mask register 3
identifier acceptance register 4
identifier acceptance register 5
identifier acceptance register 6
identifier acceptance register 7
identifier mask register 4
identifier mask register 5
identifier mask register 6
identifier mask register 7
rx foreground buffer thru +$16f
tx foreground buffer thru +$17f

can1ctl0:
can1ctl1:
can1btr0:
can1btr1:
can1rflg:
can1rier:

equ
equ
equ
equ
equ
equ

$180
$181
$182
$183
$184
$185

;can1
;can1
;can1
;can1
;can1
;can1

control register 0
control register 1
bus timing register 0
bus timing register 1
receiver flags
receiver interrupt enables

can1tflg:
can1tier:
can1tarq:
can1taak:
can1tbel:
can1idac:

equ
equ
equ
equ
equ
equ

$186
$187
$188
$189
$18a
$18b

;can1
;can1
;can1
;can1
;can1
;can1

transmit flags
transmit interrupt enables
transmit message abort control
transmit message abort status
transmit buffer select
identfier acceptance control

can1rerr:
can1terr:
can1ida0:
can1ida1:
can1ida2:
can1ida3:
can1idm0:
can1idm1:
can1idm2:
can1idm3:
can1ida4:
can1ida5:
can1ida6:
can1ida7:
can1idm4:
can1idm5:
can1idm6:
can1idm7:
can1rxfg:
can1txfg:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$18e
$18f
$190
$191
$192
$193
$194
$195
$196
$197
$198
$199
$19a
$19b
$19c
$19d
$19e
$19f
$1a0
$1b0

;can1
;can1
;can1
;can1
;can1
;can1
;can1
;can1
;can1
;can1
;can1
;can1
;can1
;can1
;can1
;can1
;can1
;can1
;can1
;can1

receive error counter

transmit error counter
identifier acceptance register 0
identifier acceptance register 1
identifier acceptance register 2
identifier acceptance register 3
identifier mask register 0
identifier mask register 1
identifier mask register 2
identifier mask register 3
identifier acceptance register 4
identifier acceptance register 5
identifier acceptance register 6
identifier acceptance register 7
identifier mask register 4
identifier mask register 5
identifier mask register 6
identifier mask register 7
rx foreground buffer thru +$1af
tx foreground buffer thru +$1bf

can2ctl0:
can2ctl1:
can2btr0:
can2btr1:
can2rflg:
can2rier:
can2tflg:
can2tier:
can2tarq:
can2taak:
can2tbel:
can2idac:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$1c0
$1c1
$1c2
$1c3
$1c4
$1c5
$1c6
$1c7
$1c8
$1c9
$1ca
$1cb

;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2

control register 0
control register 1
bus timing register 0
bus timing register 1
receiver flags
receiver interrupt enables
transmit flags
transmit interrupt enables
transmit message abort control
transmit message abort status
transmit buffer select
identfier acceptance control

can2rerr:
can2terr:
can2ida0:
can2ida1:
can2ida2:
can2ida3:
can2idm0:
can2idm1:
can2idm2:
can2idm3:
can2ida4:
can2ida5:
can2ida6:
can2ida7:
can2idm4:
can2idm5:
can2idm6:
can2idm7:
can2rxfg:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$1ce
$1cf
$1d0
$1d1
$1d2
$1d3
$1d4
$1d5
$1d6
$1d7
$1d8
$1d9
$1da
$1db
$1dc
$1dd
$1de
$1df
$1e0

;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2
;can2

receive error counter

transmit error counter
identifier acceptance register 0
identifier acceptance register 1
identifier acceptance register 2
identifier acceptance register 3
identifier mask register 0
identifier mask register 1
identifier mask register 2
identifier mask register 3
identifier acceptance register 4
identifier acceptance register 5
identifier acceptance register 6
identifier acceptance register 7
identifier mask register 4
identifier mask register 5
identifier mask register 6
identifier mask register 7
rx foreground buffer thru +$1ef

can2txfg:

equ $1f0 ;can2 tx foreground buffer thru +$1ff

can3ctl0:
can3ctl1:
can3btr0:
can3btr1:
can3rflg:
can3rier:
can3tflg:
can3tier:
can3tarq:
can3taak:
can3tbel:
can3idac:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$200
$201
$202
$203
$204
$205
$206
$207
$208
$209
$20a
$20b

;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3

control register 0
control register 1
bus timing register 0
bus timing register 1
receiver flags
receiver interrupt enables
transmit flags
transmit interrupt enables
transmit message abort control
transmit message abort status
transmit buffer select
identfier acceptance control

can3rerr:
can3terr:
can3ida0:
can3ida1:
can3ida2:
can3ida3:
can3idm0:
can3idm1:
can3idm2:
can3idm3:
can3ida4:
can3ida5:
can3ida6:
can3ida7:
can3idm4:
can3idm5:
can3idm6:
can3idm7:
can3rxfg:
can3txfg:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$20e
$20f
$210
$211
$212
$213
$214
$215
$216
$217
$218
$219
$21a
$21b
$21c
$21d
$21e
$21f
$220
$230

;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3
;can3

receive error counter

transmit error counter
identifier acceptance register 0
identifier acceptance register 1
identifier acceptance register 2
identifier acceptance register 3
identifier mask register 0
identifier mask register 1
identifier mask register 2
identifier mask register 3
identifier acceptance register 4
identifier acceptance register 5
identifier acceptance register 6
identifier acceptance register 7
identifier mask register 4
identifier mask register 5
identifier mask register 6
identifier mask register 7
rx foreground buffer thru +$22f
tx foreground buffer thru +$23f

ptt:
ptit:
ddrt:
rdrt:
pert:
ppst:

equ
equ
equ
equ
equ
equ

$240
$241
$242
$243
$244
$245

;portt
;portt
;portt
;portt
;portt
;portt

data register
input register
direction register
reduced drive register
pull device enable
pull polarity select

pts:
ptis:
ddrs:
rdrs:
pers:
ppss:
woms:

equ
equ
equ
equ
equ
equ
equ

$248
$249
$24a
$24b
$24c
$24d
$24e

;ports
;ports
;ports
;ports
;ports
;ports
;ports

data register
input register
direction register
reduced drive register
pull device enable
pull polarity select
wired or mode register

ptm:
ptim:
ddrm:
rdrm:
perm:
ppsm:
womm:
modrr:
ptp:

equ
equ
equ
equ
equ
equ
equ
equ
equ

$250
$251
$252
$253
$254
$255
$256
$257
$258

;portm
;portm
;portm
;portm
;portm
;portm
;portm
;portm
;portp

data register
input register
direction register
reduced drive register
pull device enable
pull polarity select
wired or mode register
module routing register
data register

ptip:
ddrp:
rdrp:
perp:
ppsp:
piep:
pifp:
pth:
ptih:
ddrh:
rdrh:
perh:
ppsh:
pieh:
pifh:
ptj:
ptij:
ddrj:
rdrj:
perj:
ppsj:
piej:
pifj:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$259
$25a
$25b
$25c
$25d
$25e
$25f
$260
$261
$262
$263
$264
$265
$266
$267
$268
$269
$26a
$26b
$26c
$26d
$26e
$26f

;portp
;portp
;portp
;portp
;portp
;portp
;portp
;porth
;porth
;porth
;porth
;porth
;porth
;porth
;porth
;portj
;portj
;portj
;portj
;portj
;portj
;portj
;portj

can4ctl0:
can4ctl1:
can4btr0:
can4btr1:
can4rflg:
can4rier:
can4tflg:
can4tier:
can4tarq:
can4taak:
can4tbel:
can4idac:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$280
$281
$282
$283
$284
$285
$286
$287
$288
$289
$28a
$28b

;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4

control register 0
control register 1
bus timing register 0
bus timing register 1
receiver flags
receiver interrupt enables
transmit flags
transmit interrupt enables
transmit message abort control
transmit message abort status
transmit buffer select
identfier acceptance control

can4rerr:
can4terr:
can4ida0:
can4ida1:
can4ida2:
can4ida3:
can4idm0:
can4idm1:
can4idm2:
can4idm3:
can4ida4:
can4ida5:
can4ida6:
can4ida7:
can4idm4:
can4idm5:
can4idm6:
can4idm7:
can4rxfg:
can4txfg:

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$28e
$28f
$290
$291
$292
$293
$294
$295
$296
$297
$298
$299
$29a
$29b
$29c
$29d
$29e
$29f
$2a0
$2b0

;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4
;can4

receive error counter

transmit error counter
identifier acceptance register 0
identifier acceptance register 1
identifier acceptance register 2
identifier acceptance register 3
identifier mask register 0
identifier mask register 1
identifier mask register 2
identifier mask register 3
identifier acceptance register 4
identifier acceptance register 5
identifier acceptance register 6
identifier acceptance register 7
identifier mask register 4
identifier mask register 5
identifier mask register 6
identifier mask register 7
rx foreground buffer thru +$2af
tx foreground buffer thru +$2bf

* end registers

input register
direction register
reduced drive register
pull device enable
pull polarity select
interrupt enable register
interrupt flag register
data register
input register
direction register
reduced drive register
pull device enable
pull polarity select
interrupt enable register
interrupt flag register
data register
input register
direction register
reduced drive register
pull device enable
pull polarity select
interrupt enable register
interrupt flag register