Device Monte Carlo Simulation Methodology

of Two-dimensional FinFET Slices

Abstract
This TCAD Sentaurus project provides a template setup for the Monte Carlo
simulation of a two-dimensional (2D) FinFET using the single-particle device
Monte Carlo simulator in Sentaurus Device (referred to as Sentaurus Device Monte
Carlo). A three-dimensional (3D) FinFET is built using process simulation with
stress, and a 2D FinFET is generated by cutting the 3D FinFET horizontally. The
effective thickness of the gate insulator and the effective workfunction of the gate
are calibrated through a series of drift-diffusion device simulations, with and
without quantum correction, before the device Monte Carlo simulation occurs to
account for the quantum confinement effect.
Both n-type and p-type devices are simulated with various channel lengths. Linear
and saturation IdVg curves are simulated by Sentaurus Device Monte Carlo down
to the threshold voltage.

Version Information
This application note has been designed and verified using TCAD Sentaurus
Version G-2012.06.
Running it with previous or future versions may possibly require minor adjustments.

Synopsys, the Synopsys logo, and SolvNet are registered trademarks of Synopsys, Inc.
All other products or service names mentioned herein are trademarks of their respective holders and should be treated as such.
Copyright 2012 Synopsys, Inc. All rights reserved.

Introduction
FinFET simulations pose new challenges because different
crystallographic orientations and quasiballistic transport in
short-channel devices must be treated, while keeping
computation times at reasonable levels for TCAD
applications.
This project addresses these challenges in a hybrid manner.
The Sentaurus Workbench project starts with the generation
of the 3D structure in Sentaurus Process. The preparation
for device simulation is finalized by a 2D cut through the
FinFET. The device simulation starts with 2D densitygradient (DG) and classical drift-diffusion (DD) device
simulations, which also serve to extract the effective oxide
thickness and the effective workfunction for the quantum
correction used in the 2D device Monte Carlo simulation,
where, IdVg curves of the 2D FinFET are obtained.

Sentaurus Device
The first four tool instances of Sentaurus Device (DD_QC,
DD_NoQC, DD_noQC_EpsCorrected, and DD_for_MC)
perform DD with or without quantum correction (QC), and
with or without effective oxide thickness and effective
workfunction adjustments. The results from these
simulations are used in the Sentaurus Device Monte Carlo
simulation to account for the quantum confinement effect.
The methodology is discussed in the following sections.
The last two tool instances of Sentaurus Device (MC and
MC_IV) perform the Sentaurus Device Monte Carlo
simulations based on the solution and correction obtained
from the previous DD Sentaurus Device simulations.

The Sentaurus Workbench project allows users to obtain

very fast estimates for, for example, threshold voltage and
on-current based on 2D DD results and enables users to
quantify the influence of quantization and quasiballistic
transport as a function of geometric parameters.

The Sentaurus Workbench parameter Strain specifies

whether the stress simulation is included in the DD and MC
simulations. Vg is the maximum gate voltage, and Vd is the
maximum drain voltage in the simulations. Threads and
IVThreads specify the number of threads to be used in the
single drain-voltage device Monte Carlo simulation (MC)
and the IdVg sweeping device Monte Carlo simulation
(MC_IV), respectively.

General Simulation Setup

Inspect

This section describes the tool flow of the Sentaurus

Workbench project. For each tool, the associated Sentaurus
Workbench input parameters are discussed.

The Inspect tool instances are:

StrainExtraction converts the average stress

extracted in Sentaurus Process to strains for the
subsequent Monte Carlo simulations. (Note that
Sentaurus Device Monte Carlo only supports constant
average strain.)

QC_VT extracts the threshold voltage (VT) of the IdVg

obtained in DD_QC.

Epsilon_Correction extracts the centroids of the

inversion charge obtained in DD_QC and DD_NoQC to
calculate the dielectric constant adjustment required to
account for the quantum confinement effect.

Vt_adjustment
extracts
DD_noQC_EpsCorrected.

Although only <100> and <110> are supported in this

project, you can extend this to other directions if device
parameters are calibrated correctly. You can choose either
TN or TP as the Domain value to simulate an n-type FinFET
or a p-type FinFET, respectively.

DD_IV plots the IdVg curves of the four DD tool

instances and extracts the on-current (IDDMax) in
DD_for_MC.

Inspect_transient plots the transient result

(independent variable is simulation time) of MC and
extracts the on-current (IMCMax) and IMCMax/
IDDMax.

Sentaurus Mesh

inspect_IV plots the IdVg curves of MC_IV.

Sentaurus Process
A 3D FinFET is constructed using Sentaurus Process with
stress simulation switched on. The Sentaurus Workbench
parameter ZCut specifies the z-coordinate where a 2D
FinFET slice is cut horizontally for the Sentaurus Device
simulation. The parameters tox and thk are the physical
thicknesses of the interfacial oxide and the high-k (HfO2)
dielectric, respectively. The gate length and the fin width
can be adjusted with the Delta_Lg and Delta_W
parameters. The channel direction (transport direction) of
the FinFET is specified with channel.

the

VT

of

Sentaurus Mesh is used to slice the 3D FinFET and

performs the appropriate transformation for the 2D
Sentaurus Device and Sentaurus Device Monte Carlo
simulations.

Copyright 2012 Synopsys, Inc. All rights reserved.

Tool-specific Setups

coordinate system is used by the tools that follow Sentaurus

Process.

Device Generation and Stress Extraction

Using Sentaurus Process

In addition, since the device Monte Carlo simulation is

based on the Boltzmann transport equation, reflective
boundary conditions cannot be used if the band structure is
anisotropic. Therefore, a full structure instead of a halfstructure must be created either in Sentaurus Process or in
the subsequent Sentaurus Mesh node for the device Monte
Carlo simulation.

Sentaurus Process simulates and generates the 3D FinFET.

Scripts are included in the input file to extract the average
stress in the channel for device simulation. Since this
project emphasizes the methodology to perform accurate
device Monte Carlo simulations, details of the process
simulation are not discussed here. Refer to another
project [1] in which a similar structure is simulated as well
as the Sentaurus Process User Guide [2] for details.
In this project, a generic SRAM layout is already created
with IC WorkBench EV Plus. Three layout-related files are
present in the project directory:

FinSRAM.gds GDSII layout file

FinSRAM_mkp.mac SRAM markup file

FinSRAM_lyt.mac SRAM TCAD layout file

The markup file contains TCAD-specific information: the

simulation domain (TN or TP) and the stretch lines
(GateWidth, NFinWidth, and PFinWidth). In the layout,
the gate length and the fin width of both domains are 25 nm
and 17 nm, respectively. They can be adjusted by setting the
Sentaurus Workbench parameters Delta_Lg and Delta_W,
which are used to stretch or shrink the layout.

In this project, the following commands create the full

structure in Sentaurus Process:
transform reflect front
transform reflect right

If the layout does not result in the required channel

orientation, before the structure is saved into the DFISE
coordinate system, you can use the following command to
rotate the structure:
transform rotate axis=x angle=90

NOTE Ensure the extracted stress components are

assigned to be consistent with the final structure
coordinates if a rotation is performed.
StressXX [Pa]

1.0e+09
6.0e+08
X

2.0e+08
-2.0e+08
-6.0e+08
-1.0e+09

In this project, two types of device are simulated:

Gate length = 45 nm, fin width = 17 nm (long-channel)

Gate length = 15 nm, fin width = 6 nm (short-channel)

Note that the gate width in the 2D slice depends also on the
sidewall angle and the cut location, ZCut. For example, to
simulate a gate length of 45 nm, Delta_Lg is set to 20 nm
( 0.02 m ) in the project.
The TCAD layout file contains only the domains and
information necessary for process simulation and is read by
Sentaurus Process.
Then, 3D raised sourcedrain FinFETs (n-type or p-type)
are built based on the layout. Stress simulation is included.
The stress source is mostly from the SiGe pocket in the ptype device and from the SiC stressor in the n-type
device [1]. You can use your own layout and process to
construct devices for Monte Carlo simulation.
Currently, Sentaurus Device Monte Carlo only supports the
DFISE coordinate system with the channel direction
(source to drain) along the x-axis in both two and three
dimensions. Therefore, the 3D structure must be created in
such a way that, after the 2D cut, the 2D structure is in the
supported orientation. In this project, the DFISE
4

Figure 1

Final short-channel 3D structure built by Sentaurus Process with

StressXX plotted: (left) n-type FinFET and (right) p-type FinFET

At the end of the simulation, average stresses in the silicon

fin along the x-, y-, and z-axes at the ZCut location are
extracted using the select command. Since during the
stress extraction, Sentaurus Process is still using the unified
coordinate system (UCS), it is necessary to swap the x- and
z-axes components so that they are used properly in the DF
ISE coordinate system during device simulations:
set intXX [lindex [integrate name=StressZZtmp
Silicon] 0]
set intZZ [lindex [integrate name=StressXXtmp
Silicon] 0]

Then, the extracted results are printed as Sentaurus

Workbench variables for later use in the Sentaurus Device
simulation:
LogFile "DOE: Sxx_Pa [format %.2e $intXX]"
LogFile "DOE: Syy_Pa [format %.2e $intYY]"
LogFile "DOE: Szz_Pa [format %.2e $intZZ]"

Copyright 2012 Synopsys, Inc. All rights reserved.

2D Structure Creation Using Sentaurus Mesh

Sentaurus Mesh reads the 3D structure in DFISE format
created in Sentaurus Process and slices a 2D FinFET
horizontally at the ZCut location. It also shifts the 2D
FinFET so that the center of the device is at (0, 0) to
increase flexibility (so that the layout does not have to be
centered about the origin).

Strain Extraction Using Inspect

MaxAngle=1.e-5
-Outside
)
}

IdVg of the 2D FinFET then is simulated using DD without

DG in DD_NoQC with the inversion charge distribution under
the gate similarly saved as well. Then, the centroids of both
simulations (with and without DG) are extracted in
Epsilon_Correction. The centroids are computed as:
xm

The stress components extracted by Sentaurus Process are

along the x, y, z of the device coordinate. However,
Sentaurus Device Monte Carlo only can read strain (instead
of stress), and also the strain must be converted to the
principal axes of the crystallographic coordinates (that is,
<100>, <010>, and <001>).

xn ( x ) dx
0
---------------------------xm
n ( x ) dx
x0

where:

Therefore, an Inspect script was written to convert the stress

extracted by Sentaurus Process along the device coordinates
to the crystallographic axes based on the channel
orientation. As a result, for the same StressXX, StressYY,
and StressZZ extracted from Sentaurus Process, the channel
orientation <110> will have different strain values from the
channel orientation <100>. The script in this project only
supports <110> and <100>.

Preparing for Device Monte Carlo Simulation

Using Sentaurus Device and Inspect:
Extracting Quantum Confinement Effect
Sentaurus Device Monte Carlo does not simulate the
quantum confinement effect in the inversion layer. To
include a potential quantum threshold-voltage shift and
inversion-layer centroid shift, a modified effective oxide
thickness (in terms of a modified effective permittivity for
the interfacial oxide) and a modified workfunction are
extracted from the DG and classical DD simulations [3][4].
The following describes the methodology and procedure.
First, IdVg of the 2D FinFET is simulated using DD with
DG (that is, with quantum correction of potential) in DD_QC,
and the VT is extracted in QC_VT. The inversion charge
distribution at high |Vg| and Vd = 0 V also is saved during
the IdVg ramp, using the NonLocalPlot section, for
example:
NonLocalPlot ((0 0)) { eDensity }

which means the electron density along the nonlocal line

closest to the coordinate (0,0) will be saved. Nonlocal lines
are constructed perpendicularly to the gate interface using
the commands:
Math(MaterialInterface="Oxide/Silicon") {
NonLocal(
Length=5e-06
Permeation=5e-06
Direction=(0 1 0)

Copyright 2012 Synopsys, Inc. All rights reserved.

(1)

x is the coordinate between x 0 (gate interface) and x m

(middle of the fin).
n ( x ) is the inversion carrier density as a function of x .

Then, the centroids are used to compute the new effective

dielectric constant of the interfacial oxide, based on the
following formula:
EPSOXNEW = t ox ( t ox ox + Si )

(2)

where:

tox is the physical interfacial oxide thickness.

ox and Si are the dielectric constants of interfacial
oxide and silicon, respectively.
is the difference between the centroids of the
inversion charge with and without DG.

Then, the corrected oxide dielectric constant is used in

DD_noQC_EpsCorrected to perform the IdVg ramp
without DG. Due to the correction, it is expected that the
inversion charge density now is similar to that with DG
using an uncorrected dielectric constant, for the same gate
overdrive. Then, VT is extracted in Vt_adjustment.
Finally, the VT difference in DD_noQC_EpsCorrected and
DD_QC is used in DD_for_MC, where the gate workfunction
is adjusted, based on the VT difference. IdVg is simulated
using DD without DG and with the corrected dielectric
constant. In the ideal case, it should reproduce the IdVg of
DD_QC. The solution is saved and ready to be used as the
starting solution for the Monte Carlo simulation.
In summary, this methodology creates a new setup (new VT
and new oxide dielectric constant) at the end, which uses
only DD without DG, giving a simulation result as if DG is
included.

Figure 2 and Figure 3 show the IdVg curves of the shortchannel n-type and p-type FinFETs resulting from this
procedure.
DD_for_MC
DD_noQC_EpsCorrected
DD_NoQC
DD_QC

0.002

Id [A/m]

Normal2OxideDirection = (0:0:1)
ChannelDirection = (1:0:0)
SurfScattRatio = 0.85
CurrentErrorBar = 2.5
MinCurrentComput = 5
DrainContact = "drain"
SelfConsistent(FrozenQF)
Window = Rectangle[ (-0.075, -0.025)
(0.075, 0.025) ]
FinalTime = 1.2e-06
Plot {Range=(0,1.2e-05) intervals=100}
}

0.001

MCStrain
specifies
the
strain
(extracted
in
StrainExtraction) on the device in the crystallographic
orientation.
0

Figure 2

0.2

0.4
Vg [V]

0.6

0.8

IdVg curves of short-channel n-type FinFET in <110> direction

ChannelDirection and Normal2OxideDirection are

the crystallographic orientations of the x-axis and y-axis,
respectively, because the DFISE coordinate system is used.

Id [A/m]

SurfScattRatio is the percentage of specular scattering.

The surface roughness scattering is modeled by a
combination of specular and diffusive scattering.
-0.001

CurrentErrorBar is the relative error (in percent) of the

drain current, below which the simulation stops.
DD_for_MC
DD_noQC_EpsCorrected
DD_NoQC
DD_QC

-0.002
-0.8

Figure 3

-0.6

-0.4
Vg [V]

-0.2

IdVg of short-channel p-type FinFET in <110> direction

Device Monte Carlo Simulation

In the Sentaurus Device tool instance MC, the solution in
DD_for_MC is loaded as the initial solution. This solution
provides the initial electrostatic potential and the carrier
density for the Monte Carlo simulation. MC performs a
single biased point simulation at |Vg| = 0.8 V and
|Vd| = 0.05 V or 0.8 V (that is, linear or saturation,
respectively).
In the Solve section, the initial DD solution first is
recomputed to ensure consistency, followed by the Monte
Carlo simulation:
Solve {
coupled {poisson Electron}
montecarlo
}

Since the DD solution is recomputed initially, the Physics

section in DD_for_MC must be present in the input file. For
Monte Carlo settings, they are specified in the MonteCarlo
section:
MonteCarlo {
MCStrain = (...)

MinCurrentComput specifies the minimum number of

iterations after steady state that are performed, irrespective
of whether the relative error of the drain current is less than
CurrentErrorBar.
SelfConsistent(FrozenQF) defines the Monte Carlo
simulation as self-consistent. FrozenQF defines the
parameters that are frozen during the Poisson solve as the
quasi-Fermi (QF) potentials.
The Window statement specifies the region where the Monte
Carlo simulation is performed.
NOTE If there is a poly gate, it must be excluded from the
window. If there is a bulk substrate contact, it must
be included in the window.
FinalTime is the simulation time after which the steady
state is assumed to be reached. The gathering of cumulative
averages begins only after FinalTime.
Plot {Range=(0,1.2e-05) intervals=100} specifies
the time points at which the Poisson equation is solved
(updated). For Range, the two float values denote the start
time (first value) and the maximum simulation time (second
value). The start time must be zero here.
Figure 4 and Figure 5 on page 7 show the cumulative
averages of the drain currents and errors at
|Vg| = |Vd| = 0.8 V of the short-channel n-type and p-type
FinFETs in the <110> direction.

Copyright 2012 Synopsys, Inc. All rights reserved.

0.002

4
0.001
2
MCdrain Error
MCdrain Current

4
6
Number of Iterations

2
Figure 4

Id [A/m]

0.002

Average Drain Error [%]

Average Drain Current Estimate [A/m]

0.001

0.2

Cumulative average (and error) over the drain-current estimations

as a function of number of iterations of short-channel n-type
FinFET in <110> direction

Figure 6

1
-0.002

Id [A/m]

Average Drain Error [%]

Average Drain Current Estimate [A/m]

MCdrain Error
MCdrain Current

-0.001

0.4
Vg [V]

0.6

0.8

Comparison of IdVg curves of MC and DD (DD_for_MC) of shortchannel n-type FinFET in <110> direction

MC
DD

-0.001

-0.002
-0.8

0
1
Figure 5

MC
DD

3
4
Number of Iterations

Cumulative average (and error) over the drain-current estimations

as a function of number of iterations of short-channel p-type
FinFET in <110> direction

You also can simulate the IdVg curves in MC. MC_IV

demonstrates the setup, which is very similar to a single
biased point Monte Carlo simulation. However, in the
Solve section, you are advised to follow the Plugin
strategy with the Save and Load commands to improve
convergence:
Solve {
Coupled {poisson electron}
QuasiStationary(
Goal{name="gate" voltage=0.142}
maxstep=0.1 doZero)
{Plugin(iterations=0 breakOnFailure)
{ poisson Coupled {poisson electron}
Save(filePrefix="n285_beforeMC")
Montecarlo
Load(filePrefix="n285_beforeMC")
}
}
}

Figure 6 and Figure 7 show the IdVg curves of the shortchannel n-type and p-type FinFETs in the <110> direction
using Sentaurus Device Monte Carlo at |Vd| = 0.8 V.

Copyright 2012 Synopsys, Inc. All rights reserved.

Figure 7

-0.6

-0.4
Vg [V]

-0.2

Comparison of IdVg curves of MC and DD (DD_for_MC) of shortchannel p-type FinFET in <110> direction

At the far right of the Sentaurus Workbench project layout,

the currents at |Vg| = 0.8 V of DD (IDDMax) and MC
(IMCMax) and their ratios (CurrentRatio) are displayed.
It shows that, in general, DD overpredicts the current in
linear mode (|Vg| = 0.05 V) as discussed in [4] and
underpredicts the current in saturation mode because the
quasiballistic overshoot effect is not captured.

Notes on Calibration
Monte Carlo simulation itself does not require any special
calibration because transport and scatterings are calculated
based on microscopic physics (for example, the phonon
scattering parameters are calibrated to measured bulk
velocity-field characteristics). The interface scattering
difference in different crystal orientations is handled
automatically by the specular scattering (because a band
structure table is used during specular scattering to conserve
parallel
momentum
and
total
energy).
Using
SurfScattRatio=0.85 (that is, 85% of the scattering is
specular and 15% is diffusive) to model the surface
roughness has been found to be in good agreement with

experimental results with high-k dielectrics. You can finetune this ratio if required, but it is usually not necessary.
On the other hand, to meaningfully compare the driftdiffusion and Monte Carlo simulation results, the interface
degradation parameters (Lombardi_highk) of driftdiffusion must be calibrated consistently.

Download Instructions
The
Sentaurus
Workbench
template
FinFET_MC_2D.gzp can be downloaded.
To download the project:
1.

This has been done in this project for the (100) and (110)
interfaces. The calibration procedure is as follows:
1.

2.

3.

Calibrate Lombardi model parameters based on

experiment for drift-diffusion with quantum correction
(DD_QC) for a long-channel device at low drain bias.
(Note that long-channel refers to, for example, 0.5 m
instead of the "long-channel" split in this project.)

References

Start an FTP session to ftp.synopsys.com, for

example:
>ftp ftp.synopsys.com

2.

Enter your Synopsys SolvNet user name.

3.

Enter your Synopsys SolvNet password.

4.

If not already in passive mode, type passive at the

FTP prompt:

Calibrate Lombardi model parameters for driftdiffusion without quantum correction, such that it has
the same effective mobility curves (mobility versus Vg)
as drift-diffusion with quantum correction.
Further calibrate Lombardi model parameters so that
drift-diffusion without quantum correction but with
corrected dielectric constant (that is, DD_for_MC) and
Monte Carlo have the same drive current at low drain
bias. This is because drift-diffusion and Monte Carlo
should have the same result in the long channel (low Efield) as there is no velocity overshoot. (Note that longchannel refers to, for example, 0.5 m instead of the
"long-channel" split in this project.)

project

ftp> passive

NOTE The passive command switches the passive

mode on and off.
5.

Type binary at the FTP prompt to set the transfer

mode to binary:
ftp> binary

6.

Type the following commands to obtain the project:

ftp> cd cafe
ftp> cd TCAD_Sentaurus_Applications_G-2012.06
ftp> get FinFET_MC_2D.gzp

7.

To log off, type quit:

ftp> quit

8.

Three-dimensional Simulations of Raised Source

Drain FinFET, TCAD Sentaurus application note,
available
from
SolvNet
at
<https://
solvnet.synopsys.com/retrieve/034407.html>, August
2012.

Copy the project to any directory under your Sentaurus

database root directory $STDB.

9.

Double-click the project file in the Sentaurus

Workbench projects browser to start the unpacking
process.

[2]

Sentaurus Process User Guide, Version G-2012.06,

Mountain View, California: Synopsys, Inc., 2012.

Assistance with Downloads

[3]

F. M. Bufler, R. Hud, and A. Erlebach, On a simple

and accurate quantum correction for Monte Carlo
simulation, Journal of Computational Electronics,
vol. 5, no. 4, pp. 467469, 2006.

[1]

[4]

C. Jungemann et al., Failure of Moments-Based

Transport Models in Nanoscale Devices Near
Equilibrium, IEEE Transactions on Electron Devices,
vol. 52, no. 11, pp. 24042408, 2005.

If you experience download problems:

In the USA:
Email est-adm@synopsys.com
Call the EST Hotline at (650) 584 1631

In Europe:
Call the Synopsys EST Support Center in Ireland:
+353 1 436 8880

Copyright 2012 Synopsys, Inc. All rights reserved.