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Introduction to ARCHITECTURE of
Fixed point DSPs (TMS320C54X series)
Bit size of the processor: What do you infer from the bit size?
I - 16-bit fixed point DSP
1. The instruction word (IW) - 16-bits (IW opcode combined with operand)
The size of Program bus (PB)
16 bits
16 bits
16 bits
16 bits
16 bits
Data from
memory (DM)
Data from
Memory (DM)
16
16
Data from
memory(DM)
16
16
32
CPU/
ALU
(16-bits)
16
Result to Data
memory
16
ALU (16)
16
CPU/ALU
(>16-bits)
(32,40,64-bits)
Result to Data
memory
ALU of Ps and Cs
32
Accumulator (32)
ACCH (16)
Accumulator (16)
16
ALU (32)
16
Result to Data
memory
ACCL(16)
16
Result to Data
memory
ALU of DSPs
Why it is so? What are the benefits due to increased processing size?
Major Blocks
1.
2.
3.
4.
CPU
On-chip Memory
Internal Buses
On-chip Peripherals
1.
2.
3.
4.
5.
6.
7.
Control Unit
8.
CPU
Bit size
ii)
Number of buses
Design specifications
i) Bit size - 16 bit ii) Number of buses - 1 (DB) iii) Number of Accumulators - 1
Data from
memory(DM)
16
of the processor.
16
ALU (16)
16
Accumulator (16)
16
Result to Data
memory
32
ALU (32)
32
Accumulator (32)
ACCH (16) ACCL(16)
16
16
16 line 2:1
Multiplexer
16
Result to Data
memory
10
16
32
16
32
32
ALU (32)
32
Accumulator (32)
ACCH (16) ACCL(16)
16
16
16 line 2:1
Multiplexer
16
Result to Data
memory
32 line 2:1
Multiplexer
11
16 line 2:1
Multiplexer
12
B(32)
A(32)
Data from
memory(DM)
16
32
32 line 2:1
Multiplexer
32
ALU (32)
32
ACCU- A (32)
ACCU- B (32)
BH (16)
32 line 1:2
De-Multiplexer
AH (16)
AL(16)
16
16
BL(16)
16
16
16 line 2:1
16
16 Multiplexer
16 line 2:1
Multiplexer
16
16
16 line 2:1
16 Multiplexer
Result to Data
memory
32
13
14
Multiplicand
16
16
Multiplier
16 x 16 bits
32
Product
Data from memory
16
16 line 1:2
De-Multiplexer
16
16
TREG
16
Multiplier
16 x 16 bits
32
Product Register
(PREG) (32)
15
16
Data from DM
(DB)
16
Data from DM
(DB1)
16 line 1:2
De-Multiplexer
16
16
16
TREG
16
16 line 2:1
Multiplexer
16
16
Multiplier
16 x 16 bits
32
Product Register
(PREG) (32)
Data from
DM (DB2)
16
16 line 2:1
Multiplexer
17
Data from
(DM)
16
16 line 2:1
Multiplexer
16
16
16 line 1:2
De-Multiplexer
16
16
TREG
16
Multiplier
16 x 16 bits
32
Product Register
(PREG) (32)
18
Design specifications Dual operand Multiplier 2 operand from DM and one from PM
i) Bit size - 16 bit (ALU size > 16 bits)
ii) Number of buses - 2 (DB1 & DB2) ; 1 (PB)
PREG (32)
Data from
memory
40
Data from
memory
16
16 line 1:2
De-Multiplexer
40 line 2:1
Multiplexer
16
40
40
16
ALU (40)
16
40
TREG
Accumulator (40)
16
Multiplier
16 x 16 bits
32
Product Register
(PREG) (32)
32
16
16
16
Result to Data
memory
16 line 2:1
Multiplexer
Points to be remembered
for the design
Size of multiplier is same as bit
size of the processor 16 x 16
bits.
The product is 32 bits, the ALU
size should be more than the
product
MAC instruction uses multiplier
followed by ALU
The product is accumulated in
ALU
Single Operand multiplier and
ALU
19
20
Data from
(DM)
16
16
16 line 1:2
De-Multiplexer
32
16
ALU (32)
16
32
TREG
Accumulator (32)
16
Multiplier
16 x 16 bits
16
16
16 line 2:1
Multiplexer
40
32
16
Adder (40)
40
40
Result to Data
memory
ALU unit
Regiter1 (40)
40
MAC unit
MAC output
ALU unit
21
MAC unit
22
23
Registers (INDX)
Circular Buffer one
ARU can process only the address of
24
25
26
27
28
End of Part-2