Anue Systems

INTELLIGENTLY DESIGNED TO SIMPLIFY THE COMPLEX

The Challenge in Synchronizing Mobile Backhaul
Copyright 2002-2011 Anue Systems, Inc.

Outlook
Infonetics

Research: Between 2010 and 2014, service providers are

expected to spend a cumulative $36 billion worldwide on mobile
backhaul equipment < based mainly on the strength of Ethernet
equipment>

Synchronization
Mobile

Backhaul providers are moving to Ethernet networks to

improve bandwidth and scalability

Carrier Grade Ethernet is lower cost, high bandwidth

Requires 50ppb (GSM, CDMA 2000, TD-SCDMA, WCDMA, LTE)
and 3s accuracy (TD-SCDMA, CDMA 2000, LTE)
Packet networks do not offer sufficient timing and synchronization for circuitswitched services

Poor synchronization at Wireless network causes

Channel interference which reduce call quality and network capacity
Clicks or dropped calls during handover between base stations
Decreased data throughput
The problem is addressed by SyncE, ToP, or both
SyncE solves this problem at the physical layer
ToP and Circuit Emulation solves this problem at the protocol layer
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Timing Requirements
Transport

and Service Requirements Drive Synchronization

Service

Freq. offset

QoE Impact

Voice (human speech)

< ~32 ppm

Snap, Crackle, Pop possible if slips

occur

Voice-band Fax/Modem

< ~50 ppb

Specks and dots, white lines,

streaks, dropped connection. Slips
and Pitch Modification Effect.

Ethernet (conventional)

< 100 ppm

Not applicable

Video, Two Way (e.g.

video conference)

Jury is still out. Likely to be <

50ppb

Blocks, freeze frames, jerkiness,

Video, One Way: MPEG

HDTV, IPTV, VoD, DVB,
etc

Jury is still out. Likely to be <

50ppb and may depend on service

Blocks, freeze frames, jerkiness,

audio-video-synch,

Wireless backhaul

< 50 ppb

Dropped calls

ISDN (PRI/BRI); DS1

Stratum 1 Traceable

Various depending on application

Stratum

1 Traceability Satisfies Entire Service Spectrum

Synchronous Ethernet can deliver timing (freq.) effectively
PTP can support wireless requirements
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Precision Timing Protocol (PTP) IEEE 1588

Designed:
to synchronize clocks across packet based networks
as an improvement to NTP (hundreds of s accuracy)
Originally developed for industry applications in 2002
Extended with the Telecom Profile to 1588v2 in 2008
Frequency synchronization AND time-of-day over PSN
End to End (only Master, Slave need to be exchanged)
Affected by network load (PDV)

1588v2 One Step Clock

PTP Master
t1

PTP Slave
Timestamps
known by Slave

Sync

Delay-Req

t2

t1; t2

t3

t1; t2; t3

t4

Delay-Resp

PTP Operation
1.
2.
3.
4.
5.

t1; t2; t3; t4

One-Step Clock
- Timestamp t1 is already
embedded in Sync message

PTP Master sends a Sync packet to the slave and notes the time t1
PTP Slave receives the Sync packet and notes the time of reception t2
PTP Slaves sends a Delay-Request packet to the PTP Master and notes the time t3 at which it was sent
PTP Master receives the Delay-Request packet and notes the time of reception t4
PTP Master conveys to the PTP Slave the timestamp t4 by embedding it in a Delay-Response packet

1588v2 Two Step Clock

PTP Master
t1

PTP Slave
Timestamps
known by Slave

Sync
Follow-Up

t2

t2
t1; t2

Delay-Req

t3

t1; t2; t3

t4

Delay-Resp

t1; t2; t3; t4

PTP Operation
1.
2.
3.
4.
5.
6.
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PTP Master measures when the Sync packet is leaving the master clock
PTP Master sends a Follow-Up packet with the measured time t1 to the PTP Slave
PTP Slave receives the Follow-Up packet and notes the time of reception t2
PTP Slaves sends a Delay-Request packet to the PTP Master and notes the time t3 at which it was sent
PTP Master receives the Delay-Request packet and notes the time of reception t4
PTP Master conveys to the PTP Slave the timestamp t4 by embedding it in a Delay-Response packet

1588v2 Protocol (Transparent Clock)

PTP Master
t1

Transparent Clock

PTP Slave

Sync
1

Timestamps
known by
Slave

Sync

Follow-Up

Follow-Up

t2 t2

2
t3

Delay-Req
3

t4
Delay-Resp

t1; t2
t1; t2; t3

Delay-Req

Delay-Resp
t1; t2; t3; t4

Transparent Clock Operation

1. Sync packets traverses the Transparent Clock while its residence time will be measured
2. These values are added to the Follow-Up packet for use by the PTP Slave to account queuing delays
3. Similar to the Follow-Up packets in the opposite direction, happens to the Delay-Request packets

Network Topology & Boundary Clock

Grandmaster

Boundary Clock

PTP
Slave

Clock
Correction

PTP
Master

Oscillator

Transparent
Clock

Slave
Clock

Boundary Clock
Boundary clocks have more than two network interfaces and separates different PTP domains.
Against the Grandmaster the boundary clock is seen as Slave while it acts within his domain as
Master.
It is not recommended to cascade boundary clocks as this would cause none linear errors
accumulating.
Synchronization messages from the Grandmaster will be used to synchronize the boundary clock and
not forwarded to the clocks within the domain.
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1588v2 Advantages & Challenges

Transfer

Time-of-Day
Allow timing to be supported in non-synchronous packet network
(i.e. already deployed packet switched networks)
Can operate thru/over another service provide network

It provides a method for sending independent

service timing flow

Easier

to adapt over existing infrastructure

Accuracy

limited by network delay asymmetry between

forward and reverse paths

Time-of-Delay calculations as based on symmetric path delay

Performance

is dependent on network topology and on

network loading conditions

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Synchronous Ethernet (SyncE)

Synchronous

11

Ethernet (SyncE)

Physical layer technology

Based on well understood SONET/SDH model
Point to point
Provides Frequency synchronization (no time of day)
Not affected by network load

Looking back to understand the future

1 0
1 0

1 0 0

1 1 0
t

1 0 0

1 1 0

Data goes through

the higher layers in the
switch
while timing goes to the
Ethernet Equipment Clock
(EEC) for clock recovery

In PDH and SDH the clock is based on the physical link.

Line-codes has been developed to avoid long series of 1 and 0
for a better clock (frequency) recovery at the remote end.
Standard Ethernet is transmitting data depending on the load and
even at 100% load is still an Inter Frame Gap of 12 bytes (96 bit).
This does not work out.
Solution:
IEEE has defined physical Ethernet Signals that are continuously transmitting (e.g.
keep alive Signal at 100M, GE and 10GE).
Only these Signals can be used for SyncE.
10M Ethernet is not capable for SyncE

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PRC, SSU and EEC

PRC

EEC
max 20x

SSU

EEC
max 20x

13

SSU

Similar to SDH networks the root of the

synchronization tree is the Primary Reference
Clock (PRC). In most of the cases this is a
Cesium clock. The clock will be distributed
through the network with the help of the
Ethernet Equipment Clock (EEC). This is the
internal clock of a SyncE Network Element that
is locked in frequency to the incoming signal
from the root side by clocking the outgoing
signals to the leaves. A maximum of 20 EEC
can be built up in a chain before a
max
60x EEC Synchronization Supply Unit (SSU) need to be
implemented. The main reason therefor is the
accumulated Jitter and Wander thought the
chain. SSU are usually built up with Rubidium
clocks inside that will be used as backup if the
chain to the PRC is broken up. In total a
maximum of 10 SSU can be built up in a chain
by maintaining a maximum of 60 EEC. EEC
does not measure the quality of the received
clock. The decision from which interface the
clock will be taken is depending on the
priority and the ESMC message

ESMC Regular Case

PRC

Port 1
EEC
Port 2

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The configuration of each node and the clock quality

distributed in the Ethernet Synchronization Messaging
Channel (ESMC) is the base the node is taking the clock
from. The yellow arrows contains the information Quality
Level: PRC (QL-PRC). As this has been setup as first
priority the resulting structure is as displayed. In order to
avoid clock loops QL-DNU (Do Not Use) will be
transmitted in the backward direction. This stays forever
if no link errors occur.

ESMC Switch Over

PRC

Port 1

EEC
Port 2

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A digger driver has decided to break the link in-between

the node A and B. The synchronization path would be
broken and node B, C and D would loose synchronization
to the PRC. In order to prevent this a second priority has
been defined for each node. In the very first moment node
B is loosing his 1st reference and from node C QL-DNU
is received. This leads node B to switch in holdover
mode. QL-PRC that has been sent to node C will be
replaced by QL-EEC1. Node C is receiving from B QLEEC1 and from node D still QL-DNU. With that node C
will also fall into holdover and changes QL-PRC
towards node D to QL-EEC1. Node D receives from
node E QL-PRC since only in the backward direction to
node F QL-DNU is distributed (to avoid clock loops).
Node D is very happy about QL-PRC from node E and
switches from holdover in taking the clock from node E.
Towards Node E QL-DNU will be transmitted but towards
node C QL-PRC This leads node C taking the clock from
node D. This goes on till node B took the clock from node
C and all nodes are now back synchronized to the PRC
again. (Remark from the presenter: That was hard work,
dammed digger driver).

SyncE Advantages & Challenges

Clock

accuracy similar to what is achieved today using

SONET/SDH and PDH timing
Performance is independent of network configuration and traffic
Consented standards
G.8262 defining the SyncE clock specifications
G.8264 defining the Ethernet Synchronization Messaging Channel

Requires

Provides synchronization only between two directly

connected devices supporting SyncE

Cannot

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new or upgraded hardware at both ends of Ethernet link

transfer Time-of-Day information

Single path timing hence cannot calculate round-trip delays

Jitter and Wander

Jitter

Generally associated with short-term effects

Commonly associated with phase fluctuations
Inherent in all clock-recovery (CDR) mechanisms
Usually can be filtered out using PLLs and thus considered benign
Excessive jitter can cause clock-recovery malfunctions
Unless properly attenuated jitter can give rise to wander

Wander

Generally associated with long-term effects

Manifests itself as (short-term) frequency offset
Cannot be filtered by common PLLs
Determining factor in the size of buffers and pointer adjustments
Can cause jitter problems in clock-multiplication scenarios
Wander and jitter are the same but different.
Arbitrary distinction: > 10Hz is jitter; <10Hz is wander

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Time Error and Time Interval Error

Reference
clock
Clock under
test

Basic

premises:
Both the reference and clock being analyzed have same nominal period
This nominal period may require that one (or both) are divided down
The nominal value for x(n) is zero (or a constant)

The

discrete-time signal {x(n)} is the Time Error (TE) and is the basis for
quantifying the performance of the clock (relative to reference)

{x(n)}

can be viewed as the samples of a (analog) signal, x(t), taken every T0

seconds (sampling rate = fs = 1/T0); such a sequence is considered a
discrete-time signal (or digital signal)

[x(n+k)

x(n)] is the time interval error the error in measuring an interval of

duration kT0 starting at time n

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18

Wander - MTIE
MTIE

MTIE is a useful indicator of the size of buffers and for

predicting buffer overflows and underflows.

Buffer

Write into buffer with clock A

Read out of buffer with clock B

Buffer size > MTIE() implies that overflow/underflow unlikely in any interval <

MTIE()

Buffer size = MTIE() implies that overflow/underflow occurs approx. every seconds

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Observations:
monotonically increasing with
linear increase indicates freq. offset
for very small , MTIE() related to jitter
for medium , MTIE() related to wander
for large , indicates whether locked

Wander - TDEV
TDEV

A measure of stability expected over a given observation interval,

( is a parameter).

Given a set of N observations {x(k); k=0,1,2,,(N-1)} with underlying sampling

interval 0, let = n0 (window = n samples; n = 1,2,,N).

x ( ) = TDEV ( ) =
for n=1, 2,...,

1
6n 2 ( N 3n + 1)

N 3n

j =0

+
(
x
2
x
x
)
i +2n
i+ n
i
i
=
j

n + j 1

N3

TVAR = square of TDEV

Modified Allan Variance (related to TDEV) : y ( ) =

Conventional
Definition
Note: x(k) xk

x ( )

TDEV suppresses initial phase and frequency offset and quantifies the
strength of the frequency drift and noise components
TDEV is related to the power-spectrum of the noise

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Some Important Standards (Timing Related)

21

ITU-T G.811: Timing Characteristics of Primary Reference Clocks

ITU-T G.812: Timing requirements of slave clocks suitable for use as node clocks in
synchronization networks
ITU-T G.813: Timing characteristics of SDH equipment slave clocks (SEC)
ITU-T G.823: The control of jitter and wander within digital networks which are based on
the 2048 kbit/s hierarchy (i.e. E1)
ITU-T G.824: The control of jitter and wander within digital networks which are based on
the 1544 kbit/s hierarchy (i.e. T1)
ITU-T G.8261/Y.1361 Timing and synchronization aspects in packet networks
ITU-T G.8262/Y.1362 Timing characteristics of synchronous Ethernet Equipment slave
clocks (EEC)
ITU-T G.826x/G.827x more standards (in various stages of completion)
ANSI T1.101-1999: Synchronization Interface Standard
GR-1244-CORE, Clocks for the Synchronized Network: Common Generic Criteria
Generic Requirements
GR-378-CORE, Timing Signal Generator Generic Requirements
GR-436-CORE: Digital Network Synchronization Plan
GR-436-CORE: Primary Reference Sources
PTP Precision Time Protocol: IEEE-1588-2002; PTPv2 IEEE-1588- 2008
NTP Network Time Protocol: (NTPv3 RFC 1305, NTPv4 RFC 5905)

Verify PTP Master and PTP Slave simultaneously

Measure PTP Packet Delay Variation (PTP Master) and recovered Slave Clock

Slave Clock
T1/E1/10MHz

T1/E1/10MHz
Ref to Master
1G/10G Ethernet

PTP Master

timing flow

PTP Slave

Test scenario:
1.
2.
3.
4.

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PTP Master and 3500 are synchronized to a common reference clock

PTP Master is linked through 3500 (Inline Mode) with PTP Slave
3500 verifies PDV coming from the PTP Master and perform a minTDEV analysis
3500 is measuring the recovered Slave Clock for TIE and calculates MTIE and TDEV values

Conformance Test on PTP Slave

Generate PTP Packet Delay Variation and measure recovered Slave Clock

Slave Clock
T1/E1/10MHz

T1/E1/10MHz
Ref to Master
1G/10G Ethernet

PTP Master

timing flow

PTP Slave

Test scenario:
1.
2.
3.

4.

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PTP Master and 3500 are synchronized to a common reference clock

PTP Master is linked through 3500 (Inline Mode) with PTP Slave
Generate PDV
Recovered from a real world or test network
Standards based on G.8261 / MEF 18
Custom designed
3500 is measuring the recovered Slave Clock for TIE and calculates online MTIE and TDEV values

Example Anue 3500 Use Case

Verify PTP Slave / CES IWF compliance
T1/E1
source

Ref Clk
Slave
PEC/IWF

100M/1G/10G
Ethernet (PTP/CES)

100M/1G/10G
Ethernet (PTP/CES)

PEC/IWF

Master
E1/T1
timing flow

Test scenario:
1.
2.
3.

4.
5.
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PEC = Packet Equipment Clock

IWF = Inter-Working Function

Master and 3500 are synchronized to a common reference clock

Master is linked through 3500 (Inline Mode) with Slave
Generate PDV
Recovered from a real world or test network
Standards based on G.8261 / MEF 18
Custom designed
3500 measures Wander (TIE) at the recovered E1/T1 interface
3500 is calculating online the MTIE and TDEV values and compares it with selectable tolerance masks

Verify Synce E Source EEC

Measure Wander Generation of Source EEC

T1/E1/10MHz
Ref to Master
1G/10G Ethernet

SyncE EEC (Source)

SyncE EEC (Sink)

timing flow

Test scenario:
1.
2.
3.
4.

25

Source EEC and 3500 are synchronized to a common reference clock

Source EEC and Sink EEC are linked together through 3500 (Inline Mode)
3500 measures Wander (TIE) generated by the EEC Source
3500 is calculating online the MTIE and TDEV values and compares it with selectable tolerance masks
for an immediate pass/fail analysis

Wander Tolerance Test

Generate SyncE EEC Wander and measure recovered Slave Clock

Slave Clock
T1/E1/10MHz

T1/E1/10MHz
Ref to Master
1G/10G Ethernet

SyncE EEC (Source)

SyncE EEC (Sink)

timing flow

Test scenario:
1.
2.
3.
4.
5.

26

Source EEC and 3500 are synchronized to a common reference clock

Source EEC and Sink EEC are linked together through 3500 (Inline Mode)
3500 is generating Wander with the help of the built in Wander Generator
3500 measures Wander (TIE) on the recovered Slave Clock
3500 is calculating online the MTIE and TDEV values and compares it with selectable tolerance masks
for an immediate pass/fail analysis

Wander Transfer Test

Generate Wander at the Receiver and measure the Wander at the Transmitter

T1/E1/10MHz
Ref to Master
1G/10G Ethernet

1G/10G Ethernet

SyncE EEC

Test scenario:
1.
2.
3.
4.
5.

27

SyncE EEC and 3500 are synchronized to a common reference clock

The DUT is connected on both sides to 3500 (Terminate Mode)
3500 is generating Wander at the Receiver with the help of the built in Wander Generator
3500 measures Wander (TIE) at the Transmitter
3500 is calculating online the MTIE and TDEV values and compares it with selectable tolerance masks
for an immediate pass/fail analysis

Anue Systems Overview

Founded in 2002

Headquartered in Austin, TX

Over 1,000 customers worldwide

Inc 500 fastest growing private company list

Deep technical expertise in:

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Networking technologies and testing techniques

Packet filtering and modification

Line rate performance hardware

Network visibility solutions

Network Emulators test networked applications before

deployment

Net Tool Optimizers - monitor to maintain uptime, security, and

performance

Its question time!

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