Beruflich Dokumente
Kultur Dokumente
and
Embedded Systems
MOHIT TYAGI
ARVIND KUMAR GUPTA
ESCS LABS-Gr. NOIDA
Mohit Tyagi
B.Tech., M.Tech. (MANIT-Bhopal)
(Training and R&D cell, ESCS Labs-Greater Noida)
Edited by
PREFACE
This text book is intended for a course entitled Microcontrollers and Embedded
Systems written for engineering students (GBTU, MMTU, KU, RTU, PTU, IP, MDU,
RGPV etc.).
Now-a-days the microcontrollers have become the most powerful tools available to
the engineers. A small microcontroller in the fan control provides programmable
speed control and temperature level of the room. High end industrial products can
contain over fifty embedded microcontrollers. A typical middle class household has
over fifty embedded devices. For every PC, smart phone in the world there are over
one hundred embedded devices. Millions of PCs are manufactured each year, but
billions of microcontrollers manufactured annually. While a great deal of attention is
given to personal computers, the vast majority of new designs are for embedded
applications. For every PC designer, there are thousands of designers using
microcontrollers in embedded applications. The number of embedded designs is
growing quickly.
Architecture of the Microcontroller, especially assembly programming seems quiet
complex to understand. Therefore, this book is designed to provide the desirable
balance among the basic concepts of architecture design, programs and interfacing.
The main objectives of this book are to teach students the fundamental concepts of
the 8051 microcontroller, and logical programming oriented approach, which will
help students who want to firm grasp on microcontroller applications, assembly
programming and interfacing to the memory and I/O devices.
The I/O devices such as motors, sensors, ADC, DAC, keyboard, memory, buzzer,
speaker, programmable chips, LCD, LED, seven segment display etc., are magnify
microcontroller operations and applications.
Assembly programming is an important aspect, without the knowledge of the
internal architecture, it is not possible to make a good assembly program. Emphasis
is given to the microcontrollers and entire peripherals architecture, pin
configuration and mode of operations.
This book contains twenty two chapters. The objectives of the course and the book
are the same to describe the right way to design embedded systems. While no prior
knowledge of microcontrollers or microprocessors is required, but the reader should
be familiar with basics of electronics, logic, and computer organization.
Learning to design and develop a microcontroller system without any practical
hands-on experience is a bit like trying to learn to drive a car from reading book.
Thus, another goal is to provide a practical example of a complete working module.
Students are advised to work out all the review questions and then proceed to the
next chapter. The review questions will refresh the contents of that chapter
discussed. This way will help you a lot for embedded systems design.
Authors
CONTENTS
CHAPTER 1
INTRODUCTION TO DIGITAL SYSTEM
1.1
Number system
1.2
Logic Gate
1.3
Flip-Flop
1.4
Mux and De-mux
1.5
Basic input and output logic devices for interface
1.6
Registers
1.7
Arithmetic and Logical unit
Review Questions
CHAPTER 2
INTRODUCTION TO THE COMPUTER SYSTEM
2.1
Explanation of terms related to the microprocessors
2.2
Microprocessor
2.3
Introduction to Microprocessor based system
2.4
Microcontroller
2.5
Computer Architectures
CISC
RISC
2.6
Memory Architecture
Von-Neumann or Princeton
Harvard
2.7
The 8, 16 and 32-bit Microcontrollers
CHAPTER 3
INTRODUCTION TO MICROCONTROLLER, EMBEDDED PROCESSOR AND SYSTEM
3.1
Introduction to the microcontroller
3.2
Embedded Processor and Application Awareness
3.3
Selecting the right Microcontroller Unit
3.4
Processor Technologies
3.5
Selection Process
3.6
Choosing the Right Processor Technology
3.7
What does the MCU Need to do in the System?
3.8
Finalizing the Selection
CHAPTER 4
THE 8051 MICROCONTROLLER
Introduction to the 8051 Microcontroller Family
4.1
Development/Classification of Microcontrollers
4.2
The 8051 Microcontroller Architecture
4.3
The Functional Block Diagram for the 8051
4.4
A Small 8051 Microcontroller (AT89C2051)
4.5
1
4
6
6
7
8
9
11
12
13
14
15
16
17
17
18
18
18
19
19
CHAPTER 5
5.5.2
5.6
5.7
5.8
Internal ROM
Inside the 8051 Microcontroller
Internal Working of the Microcontroller
The 8051 Microcontroller Instruction Set Summary
CHAPTER 6
DATA TRANSFER INSTRUCTIONS, I/O PORT PROGRAMMING
6.1
Data Transfer (Copy) Instructions and Programs
6.2
The 8051 I/O Parallel Port Programming
CHAPTER 7
ADDRESSING MODES
7.1
7.2
7.3
Immediate/constant addressing
Register addressing
Direct addressing
Register indirect addressing
Indexed addressing
Implied addressing mode
Timing Effect of Addressing Modes
Flow Chart symbols and description
CHAPTER 8
BRANCHING INSTRUCTIONS, LOOPS AND PROGRAMS
8.1
Jump Instructions, Loop and Programs
Unconditional Jump Instructions
Conditional Jump Instructions
Nested Loop (Loop within a Loop)
Call Instructions and Programs
Time Delay Calculation (Software Method)
CHAPTER 9
ARITHMETIC INSTRUCTIONS AND PROGRAMS
9.1
9.2
9.3
9.4
9.5
Addition
Subtraction
BCD (Binary Code Decimal) Number System
Multiplication and Division
Increment/Decrement
ii
CHAPTER 10
LOGIC INSTRUCTIONS AND PROGRAMS
Logical Instructions
10.1
Rotate
Accumulator
10.2
Swap Nibbles within Accumulator
10.3
ASCII and BCD Code for Decimal Digits
10.4
CHAPTER 11
SINGLE BIT HANDLING INSTRUCTIONS
11.1
11.2
11.3
11.4
11.5
11.6
CHAPTER 12
TIMER/COUNTER IN THE 8051
Timers Programming
12.1
Time Delay Generation (Hardware Approach)
12.2
Large Time Delay Generation (Mixed Approach)
12.3
Using Timers as Counters (Counter Programming)
12.4
CHAPTER 13
8051 SERIAL COMMUNICATION, SPI, I2C AND USB INTERFACE
Synchronous And Asynchronous Serial Communications
13.1
Asynchronous Serial Data Bit Format
13.2
The Rs-232 Standards
13.3
DCE and DTE Devices
13.4
Voltage Converters
13.5
Universal Asynchronous Receiver Transmitter (Uart)
13.6
Baud Rate Generation
13.7
Serial Port Programming to Transmitting and Receiving Data
13.8
Power Mode Control (Pcon) Register
13.9
SPI Bus Interface
13.10
I2C Bus Interface
13.11
The Universal Serial Bus (USB)
13.12
iii
CHAPTER 14
THE 8051 INTERRUPTS
14.1
Polling and Interrupt Based Data Handling Input/Output Devices
14.2
The 8051 Interrupts
14.3
Enabling and Disabling of Interrupts
14.4
Timer Interrupts
14.5
External Interrupts
14.6
Internal Interrupts
14.7
Interrupts Structure for the 8051
14.8
Interrupt Priority in the 8051
14.9
Nested Interrupt (Interrupt with an Interrupt)
14.10 Interrupt Latency
CHAPTER 15
DATA CONVERTERS AND INTERFACING
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
CHAPTER 16
INTERFACING WITH THE KEYBOARD, SEVEN SEGMENT DISPLAY, LCD AND MOTORS
Simple Keyboard and Seven Segment Display Interface
16.1
Matrix Keyboard Interfacing with the 8051
16.2
Interfacing To LCD Display
16.3
The 8051 Interfacing With THe Motors
16.4
Pulse Width Modulation (PWM)
16.5
CHAPTER 17
INTERFACING TO EXTERNAL MEMORY
Decoder as Address Decoder
17.1
Flip-Flop or Latch as the Basic Output Interface
17.2
Memory Expansion
17.3
Introduction to Address Decoding
17.4
External Memory Interfacing in 8051/8031
17.5
External Program ROM Interfacing
17.6
17.7
External Data Memory RAM
iv
CHAPTER 18
THE 8051/31 INTERFACING WITH 8255 (EXPENDING I/O PORTS)
18.1
18.2
18.3
CHAPTER 19
INTRODUCTION TO ADVANCED MICROCONTROLLERS
19.1
19.2
19.3
CHAPTER 20
INTRODUCTION TO EMBEDDED SYSTEM DESIGN
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
20.9
CHAPTER 21
INTRODUCTION TO REAL-TIME OPERATING SYSTEM (RTOS)
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
21.10
APPENDIX A
MODEL QUESTION PAPER
QUESTION BANK
232-244
252
vi
CHAPTER-1
INTRODUCTION TO DIGITAL SYSTEMS
The basic concepts of digital are necessary to understand the software logic and hardware design of a
microprocessor/microcontroller based system. In this chapter, we are focusing on logic gates, number
systems, conversion and inside a CPU.
Binary
(0-1)2
Ternary
(0-2)3
Quintal
(0-4)5
Octal
(0-7)8
Hexadecimal
(0-F)16
Base 36
number
(0-Z)36
0
1
2
3
4
0
1
10
11
100
0
1
2
10
11
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
5
6
101
110
12
20
10
11
5
6
5
6
5
6
7
8
9
111
1000
1001
21
22
100
12
13
14
7
10
11
7
8
9
7
8
9
10
11
1010
1011
101
102
20
21
12
13
A
B
A
B
12
13
1100
1101
110
111
22
23
14
15
C
D
C
D
14
15
16
1110
1111
10000
112
120
121
24
30
31
16
17
20
E
F
10
E
F
G
17
18
10001
10010
122
200
32
33
21
22
11
12
H
I
19
.
10011
.
201
.
34
.
23
.
13
.
J
.
.
98
99
.
1100010
1100011
.
10122
10200
.
343
344
.
142
143
.
62
63
.
2Q
2R
100
101
1100100
1100101
10201
10202
400
401
144
145
64
65
2S
2T
.
.
.
.
.
.
.
.
.
.
.
.
.
.
999
1000
1001
1111100111
1111101000
1111101001
1101000
1101001
1101010
12444
13000
13001
1747
1750
1751
3E7
3E8
3E9
RR
RS
RT
Step 1
Divide 13 by 2,
2) 13 ( 6 ------ Quotient is 6
12
1
remainder = 1
LSB
Step 2
2) 6 ( 3 ------ Quotient is 3
6
0
remainder = 0
Step 3
2) 3 ( 1 ------ Quotient is 1
2
1
remainder = 1
Step 4
2) 1 ( 0 ------ Quotient is 0
0
1
remainder = 1
MSB
In final division, 1 does not divide by 2, therefore, the quotient is 0 with a remainder of 1. Hence, the binary
equivalent of 1310 is 11012.
Example 1.1: Express the decimal number 5410 as a binary number.
Solution:
54/2 = 27
; remainder 0
27/2 = 13
; remainder 1
13/2 = 6
; remainder 1
6/2 =3
; remainder 0
3/2 =1
; remainder 1
1/2 =0
; remainder 1
Thus 54 decimal = 110110B and in an 8-bit register the value would be 00110110B. It may be easier to use the weighted
values of an 8-bit register to determine the binary equivalent of a decimal number i.e. to break the decimal number down
to those weighted elements, which have logic 1 level as given in following lines:
3000 + 800 + 50 + 6
Here each digit position has a weight or value. The sum of all the digits multiplied by their weights gives the total amount
being represented.
Binary Weight
In a similar way we can rewrite any binary number in terms of weights. For example binary number 111 B (7D) becomes
1112
In decimal it is
710
710
=
4+2+1
2
1
o
=
1(2) + 1(2) + 1(2)
=
1(4) + 1(2) +1
Procedure for Binary to decimal conversion
i)
Write the binary number
ii)
Directly under the binary number, write weights from right to left.
iii)
Multiply the weight with corresponding binary digit.
iv)
Add the remaining weights to obtain the decimal equivalent.
Example 1.2: Convert a binary number 1012 into equivalent decimal number.
Solution:
Step i)
Binary Number
:
1
0
1
Step ii)
Binary Weight
:
4
2
1
Step iii)
Equivalent weight
:
4
0
1
Step iv)
Weight Sum
:
4 + 0 + 1 = 510
Example 1.3: Convert binary number 101012 into equivalent decimal number.
Solution:
Step i)
:
1
0
1
0
1
Step ii)
:
16
8
4
2
1
Step iii)
:
16
0
4
0
1
Step iv)
:
16 + 0 + 4 + 0 + 1
=
2110
Conversion of Binary Fractions into decimal Fraction
How we calculate the decimal equivalent of 0.1012? In this case, the weight of digit positions to the right of the binary
point is given by 1/2, 1/4, 1/8, 1/16, 1/32 and so on. In power of 2, the weights are given below:
-1
-2
-3
-4
2 , 2 , 2 , 2 and so on
or in decimal form
0.5, 0.25, 0.125, 0.0625 and so on
Hence, the decimal equivalent for the binary fraction 0.101 2 can be calculated as bellow:
0.1
0
1
0.5 + 0 + 0.125
0.62510
1
2-4
0.0625
0.0625
=0.812510
Hence, for conversion of binary number into decimal number we should remember the following format:
.
23 22 21 20 2-1 2-2 2-3
Binary point
Table 1.2: Binary Addition
A+B
0+0
0+1
1+0
1+1
Carry
0
0
0
1
Sum
0
1
1
0
Decimal
5
x 6
30
AB
00
01
10
11
Hex
5
x6
1E
Multiplication
0
0
0
1
AND Gate
The AND Gate has two or more inputs but only one output. When all the inputs are high (1), the output is high (1)
otherwise it is low (0). This gate can be implemented with simple switches as shown in figure 1.2(a).
Figure 1.2: (a) AND gate drawn with simple switches A and B
In the figure 1.2 (a), the switches A and B are connected in series with the supply. When both the switches are ON (i.e. 1
or High), the bulb is ON (1 or High). If any of the switches is OFF (0 or Low), the bulb is OFF (0 or Low). Hence the
combination of switches A and B is known as AND gate. The symbol of AND gate is shown in figure 1.2(b).
Truth Table
A truth table gives details of various combinations of inputs and corresponding outputs. The truth table of AND gate is
given in table 1.4.
Table 1.4: Truth Table of AND Gate
Inputs
0
0
1
1
0
1
0
1
0
0
0
1
Figure 1.3: The AND gate drawn with diodes
AND Gate can also be implemented with diodes as shown in figure 1.3. When either A or B input is low (0), D1 or D2 is
forward biased and output Y is low (0). When both inputs A and B are high (1) together, the output Y is High (1). In the
same way AND Gate can also be designed with the combinations of diodes and transistors or only transistors. The AND
gate designed in IC form is shown in figure 1.4. This gate works on the logic of 'this and that' hence the name is AND
gate.
OR Gate
This gate has two or more inputs and one output. When any one or all the inputs are high (1), the output is high (1).
Figure 1.5(a) and (b) show the OR gate designed with the help of switches and diodes, respectively.
Table1.5: Truth table for OR gate
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
1
Figure 1.5: (a) The OR gates drawn with switches
From figure 1.5 (a), the bulb is glowing when switch A or/and B is ON (1 or High). In figure 1.5 (b) output Y is High (1)
when either input A or B is high (1) making D1 or D2 to conduct. The symbol of OR Gate is shown in figure 1.6(a). The
OR gates in IC form shows in figure 1.6 (b). This gate works on the logic of 'This or that', hence the name is OR gate.
NOT Gate
The NOT gate has one input and one output. When the input is High (1), the out is low (0) and vice versa. The figure 1.7
shows NOT gate designed with a switch and a transistor.
Table 1.6: Truth table for NOT gate
A (I/O)
0
1
Y(O/P)
1
0
Figure 1.7: (a) The NOT gate drawn with a switch
In figure 1.7(a), When the switch is ON (1 or High) the bulb is shorted and hence it does not glow (OFF or 0 or LOW).
When switch is OFF (open or 0) the bulb is ON (1 or High).
In figure 1.7 (b), When the input A is high (1) the transistor is forward biased and so it conducts making Y low (0). When
the input A is low (0), the transistor is cut off and hence the output Y is high (1). Since the NOT gate inverts the sense of
the output with respect to input, it is also called as an inverter. Figure 1.7 (c) and (d) shows NOT gates symbol and IC
form. This gate works on the logic of negative; hence the name is NOT gate.
NAND Gate
A NAND gate has two or more inputs and a single output. It is a combination of an AND gate and a NOT gate. The output
of a NAND gate assumes the 0 state if and only if all the inputs assume the 1 state. Figure 1.8 shows the NAND gate
designed with the help of switches, symbol of NAND gate and NAND gates in IC form.
Input
A
B
0
0
1
1
Output
Y
0
1
0
1
1
1
1
0
Figure 1.8: (a) NAND gate drawn with switches (b) NAND gate Symbol
NOR Gate
A NOR gate has two or more inputs and a single output. It is a combination of an OR gate followed by a NOT gate. The
output of a NOR gate assumes the 1 state if and only if all the inputs assume the 0 state. Figure 1.9 shows the NOR
gate designed with the help of switches. NOR gate symbol and IC form in given in figure 1.9.
Table 1.8: Truth table for NOR gate
Input
A
B
0
0
0
1
1
0
1
1
Output
Y
1
0
0
0
Figure 1.9: (a) NOR gate drawn with switches (b) Symbol of NOR gate (c) Quad 2-input NOR gates
The NAND and NOR gates are known as 'Universal Gates' as any gate or logical circuit can be implemented with them.
Exclusive OR Gate
EX-OR gate (see figure 1.10) has two or more inputs and one output. The EX-OR gate produces a high output when
either of the inputs is high, but not both. This is different from the traditional OR gate, which produces a 1 output when
either one or both of the inputs are 1. The opposite of Ex-OR gate is Ex-NOR gate.
Table 1.9: Truth Table for EX-OR gate
Input
A
B
0
0
1
1
0
1
0
1
Output
Y
0
1
1
0
1.3 FLIP-FLOP
A flip-flop (FF) is a bi-stable electronic circuit that has two stable states. The flip-flop also has memory unlike gates
described in previous Sections, since its output will remain as set until something is done to change it. FF has two
outputs, defined as Q and Q .Q and Q are complementary.
D Flip-Flop: The RS flip-flop has two data inputs R and S. To store a high bit, we need a high S; to store a low bit, we
need a high R. Generation of two signals to drive has disadvantages in many applications. Furthermore, something
forbidden condition of both R and S high may occur in advertently. These problems are avoided in D flip-flop, which only
a single data needs as input. Logic diagram, symbol and truth table of D-FF are shown in figure 1.11.
MUX. A MUX has an arbitrary number of data inputs, often an even power of two, and a smaller number of selector
inputs. According to the binary state of the selector inputs, a specific data input is transferred to the output.
A truth table for a 4-to-1 MUX is shown in Table 1.10. Each selector input value maps to one, and only one, data input.
A de-multiplexer, also called a DEMUX, performs the opposite operation of a MUX by transferring a single input to the
output that is selected by select inputs. A DEMUX is drawn similarly to a MUX, as shown in figure 1.12 (b).
Table 1.10: Four-to-One Multiplexer Truth Table
A popular use for a DEMUX is as a decoder. A decoder produces a unique output corresponding to each input pattern. If
the input line in figure 1.12 (b) is set to logic 0 (i.e., Din = 0), the 1-to-4 de-multiplexer will act as a decoder. For example,
A = 0, B = 0 will give an output of 0 on line Y0; lines Y1, Y2, and Y3 will be at logic 1. Similarly, A = 0, B = 1 will give an
output of 0 on line Y1; A = 1, B = 0 will give an output of 0 on line Y2; and A = 1, B = 1 will give an output of 0 on line Y3.
Thus the 1-to-4 de-multiplexer can function as a 2-to-4 decoder. This function has great utility in microprocessor address
or op-code decoding, which involves selecting one of multiple devices (e.g., a memory chip) at a time for access. The
truth table for a 2- to-4 decoder is shown in table 1.12 and in figure 1.12 (c). The decoders outputs are active-low,
because most memory and microprocessor peripheral chips use active-low enable signals.
Table 1.12: Two-to-Four Decoder Truth Table
Y0
A
B
DECODER
24
Y1
Y2
Y3
The only difference between tri-state buffer and two-state buffer (simply buffer) is that buffer does have high impedance
state. Therefore, there is no need of third line to enable buffer as shown in figure 1.14.
Input B
Output Q
Low Enable E
Input B
Output Q
High Enable E
input
Input B
Output Q
High Enable E
(b) Active high, inverted output tri-state buffer (c) Active high, non inverted
output tri-state buffer
output
Figure 1.14: A buffer
Active low, inverted O/P tri-state buffer: When enable E is low the gate is enabled and the output Q can be 1 or 0 (if B
is 0, Q is 1, otherwise Q is 0). However, when E is high the gate is disabled and the output Q enters into a high
impedance state. Table 1.13 is described the function of each pin of Low enabled tri-state buffer with inverting output.
Table 1.13: Functional table for active low, inverted output tri-state buffer
E ( Low Enable)
1(High)
1
0(Low)
0
B (Input)
0
1
0
1
Q (Output)
z
z
1
0
State description
High impedance (Open Circuit)
High impedance (Open circuit)
High
Low
Active High, inverted O/P tri-state buffer: When enable E is high the gate is enabled and the output Q can be 1 or 0 (if
B is 0, Q is 1, otherwise Q is 0). However, when E is low the gate is disabled and the output Q enters into a high
impedance state.
Active High, non-inverted O/P tri-state buffer: When enable E is high the gate is enabled and the output Q can be 1
or 0 (if B is 0, Q is 0, otherwise Q is 1). However, when E is low the gate is disabled and the output Q enters into a high
impedance state.
The advantages of using tri-state buffer and two-state (normal) buffer
1- It can avoid undesirable change in input and control the read operation of the output of flip-flop.
2- Tri-state buffer have three states as high, low, and high impedance (open circuit). If any flip-flop
or register is not involved in any read or/and write operations, tri-state (high impedance
state) buffer disconnect this flip-flop or register from memory circuit by making open
circuit or high impedance so that there is no flow of any current in the circuit hence we
can save power dissipation.
3- Tri-state buffers or two state buffers are used to amplify current or power driving capacity of buses
to avoid loading effect. Loading effect means that when the microprocessor draws high load current
from input device is may cause overloading. Input device gives some fake or inaccurate output
value to the microprocessor as the overloading change the characteristics of the input device.
1.6 REGISTERS
Registers are collections of multiple flip-flops arranged in a group with a common function. They are a
common synchronous-logic building block and are commonly found in multiples of 8-bit widths, thereby
representing a byte, which is the most common unit of information exchange in digital systems. An 8-bit
register provides a common clock and clock enable for all eight internal flip-flops. The clock enable allows
external control of when the flip-flops get reloaded with new D-input values and when they retain their
current values. It is common to find registers that have a built-in tri-state buffer, allowing them to be
placed directly onto a shared bus without the need for an additional tri-state buffer component.
Whereas normal registers simply store values, synchronous elements called shift registers manipulate
groups of bits. Shift registers exist in all permutations of serial and parallel inputs and outputs. The role of
a shift register is to somehow change the sequence of bits in an array of bits. This includes creating arrays
of bits from a single bit at a time (serial input) or distributing an array of bits one bit at a time (serial
output). A serial-in, parallel-out shift register can be implemented by chaining several flops together as
shown in figure 1.14.
On each rising clock edge, a new serial input bit is clocked into the first flop, and each flop in succession
loads its new value based on its predecessors value. At any given time, the parallel output of an N-bit
shift register reflects the state of the last N bits shifted in up to that time. In this example (N = 4), a serial
stream of bits collected in four clock cycles can be operated upon as a unit of four bits once every fourth
cycle. As shown, data is shifted in MSB first, because Dout[3] is shown in the last bit position. Such a
simple transformation is useful, because it is often more practical to communicate digital data in serial
form where only one bit of information is sent per clock cycle, but impractical to operate on that data
serially. An advantage of serial communication is that fewer wires are required as compared to parallel.
A parallel-in, serial-out shift register is very similar, as shown in figure 1.15, with the signals connected
for MSB first operation to match the previous example. Four flops are used here as well. However, instead
of taking in one bit at a time, all flops are loaded when the load signal is asserted. The 2-to-1 muxes are
controlled by the load signal and determine if the flops are loaded with new parallel data or shifted serial
data. Over each of the next four clock cycles, the individual bits are shifted out one at a time. If these two
shift register circuits were connected together, a crude serial data communications link could be created
whereby parallel data is converted to serial and then back to parallel at each end.
A typical ALU is given in figure consists of various digital circuits such as decoder, multiplexer, demultiplexer, adder, subtractor, multiplication, division, logical AND, OR, NAND, NOR, EX-OR etc. The opcode 01112= 7H enables the register A, register B and full adder circuit. To generate enable signal for it, a
decoder (control circuit) is used. An 8-bit ALU can be implemented (shown in figure 1.17) for the functions
as given in table 1.14.
Table 1.14: Operations for ALU
Select (Op-code)
Operation
Instruction
Function
0000
0001
0010
0011
0100
0101
0110
0111
Y=A
Y=A+1
Y=A-1
Y=B
Y=B+1
Y=B-1
Y=A+B
Y=A+B+Cin
MOV Y, A
INC A
DEC A
MOV Y, B
INC B
DEC B
ADD A, B
ADDC A, B
1000
1001
1010
Y=A
Y=B
Y=A AND B
CPL A
CPL B
AND A, B
1011
Y=A OR B
OR A, B
1100
1101
Y=A NAND B
Y= A NOR B
NAND A, B
NOR A, B
1110
1111
Y=A XOR B
Y= A XNOR B
XOR A, B
XNOR A, B
Transfer A
Increment A
Decrement A
Transfer B
Increment B
Decrement B
Add A and B
Add A and B with
Carry
Complement A
Complement B
Logical AND with A
and B
Logical OR with A and
B
Logical NAND
Logical NOR with A
and B
Ex-OR
EX-NOR
Unit
Arithmetic
Logic Unit
The ALU has some stages, each stage consisting of three parts: a) input multiplexers b) full adder and c)
output multiplexers. The ALU performs the following four arithmetic operations, MOVE, ADD, INCREMENT
and DECREMENT. The four logical operations performed are NOT, Ex-OR, Ex-NOR, AND and OR. The input
and output sections consist of 8 to 1 and 2 to 1 multiplexers. A set of four select signals has been
incorporated in the design to determine the operation being performed and the inputs and outputs being
selected. Figure 1.17 shows the 8-bit ALU with the Cin bit cascading all the way from first stage to fourth
stage.
There are large numbers of digital circuits in a processor including ALU such as registers, counter,
multiplexer, decoder, adder etc. and every operation have a unique code, called Op-code. For example:
we want to move/copy the contents of a register (say B) to the output register (say Y). The instruction
MOV Y, B performs this operation and machine-code for this operation is 03H. The instruction-code
00112=03H enables the register Y, register B and parallel-in parallel-out register. To generate enable
signal for it, a decoder (control circuit) is used. The internal operations of the processor circuit upon
receiving instruction code shown in figure 1.18. First, the decoder is decoding the instruction code, and
generate enable signal at the output. Shift register and register Y and B enable signal connected to the
decoder enable output.
10
Decoder
4 24
0011
(Input)
(Output)
Enable signal to shift register
Register B (source)
D7
D6
D5
CLK
D4
CLK
D3
CLK
CLK
D2
CLK
D1
D0
CLK
CLK
CLK
Enable
D7
D6
D5
D4
D3
D2
Register Y (destination)
Figure 1.18: The internal circuit operation of a processor to execute MOV Y, B instruction
REVIEW QUESTIONS
1. Express decimal 167 as a binary number.
2. Represent decimal numbers 15 and 250 in binary format.
3. Convert Hex ABCD to binary.
4. Add 26H+AFH.
5. What is ALU purpose?
6. Express 101111000001 as a hexadecimal value.
7. Express decimal 100 as a hex number and then as a binary number.
8. Show that if an 8-bit register contains all logic 1s then the value stored is 255.
9. Describe the function of Mux and Demux.
10. Design a 4-bit ALU for two arithmetic and two logic operations.
11
D1
D0
CHAPTER-2
INTRODUCTION TO THE COMPUTER SYSTEM
A digital computer is a digital electronic system which is designed to store, process, and communicate
information in digital form. The computer systems are constructed of digital electronics. It means that
their electronic circuits can exist in only one of two states: On or Off. Most computer electronics use
voltage levels to indicate their present state. For example, a transistor with +5 volts would be considered
"on", while a transistor with 0 volt would be considered "off."
They are found in a wide range of applications, like process control, communication systems, digital
instruments, weather forecasting and consumer products such as PCs, handhold calculators, mobile
phones etc.
How many languages do we know? Most probably more than one, but digital computer knows only a
binary. A binary number has only two discrete values: 0 and 1. Each discrete value is represented by the
on (1) and off (0) status of an electronic switch called a transistor. These patterns of "on" and "off"
stored inside the computer, which are used to encode binary data using the binary number system. The
binary number system is a method of storing ordinary numbers as pattern of 1's and 0's i.e. the ordinary
decimal number 810 is stored in computer as 01002 in binary. Because of their digital nature, the
electronics of computer can easily manipulate numbers stored in binary by treating 1 as "on" and 0 as
"off." The digital computer has various circuits, so that it can add, subtract, multiply, divide, and can do
many other things with numbers stored in binary. All digital computers understand only binary number
patterns or binary codes. Any decimal number (base 10, with ten digits from 0 to 9) can be represented
by a binary number (base 2, with digits 0 and 1).Its Binary codes are the digital machine language. A
computer manipulates information in digital or more precisely in binary form.
Computer software consists of a collection of programs that contain instructions and data to perform a
task. All programs are written using any programming language (i.e. Assembly, C, C++, Java etc), must
be translated into binary prior to execution by a computer because the computer is a digital device.
Therefore, a translator is necessary to convert such a program into binary and this is achieved using a
translator program called a compiler.
A computer is a programmable machine. The two principle characteristics of a computer are: it responds
to a specific set of instructions in a well-defined manner and it can execute a prerecorded list of
instructions (a program). Modern computers are electronic and digital. The actual machinery wires,
transistors, and circuits are called hardware. The instructions and data are called software.
All general-purpose computers require the following hardware components:
Memory: Enables a computer to store data and programs permanent or/and temporarily.
Mass storage device: Allows a computer to permanently retain large amounts of data. Common mass
storage devices include disk drives and tape drives.
Input device: Usually a keyboard and mouse is the input device through which data and instructions
enter a computer.
Output device: A display screen, printer, or other device that lets you see what the computer has
accomplished.
Microprocessor: The brain of the computer, this is the component that actually executes instructions
(processes data according to instructions).
In addition to these components, there are many other components which make it possible for the basic
components to work together efficiently. For example, every computer requires a bus (signal lines/wires)
that transmits data from one part of the computer to another.
The basic blocks of a computer, are the central processing unit (CPU) or Microprocessor(s), the RAM and
ROM memory, and the input/output (I/O) ports or devices. The CPU or microprocessor (ALU + Reg.) of a
computer is basically the same as the brain of a human being; so computer memory is conceptually
similar to human memory.
A question asked to a human being is analogous to enter a program into a computer using an input device
such as a keyboard, touch-screen, scanner and a person answering a question is similar in concept to
outputting the program result to a computer output device such as a printer, monitor, alarm etc.
12
The main difference is that human beings can think independently, whereas computers can responds only
for those questions, which they are programmed (instructions) and designed (electronic circuit). So, one
can better understand who is more intelligent?
The computer hardware includes such components as memory, CPU, transistors, plug, socket, nuts, bolts,
and so on. These hardware components like CPU, memory are designed for software programs. The
programs can perform a specific task, such as addition, subtraction etc., if the computer has an electronic
circuit capable of adding two numbers. The programmers cannot change these electronic circuits but can
perform tasks on them using instructions.
All units (CPU, memory, and I/O devices ) of the computer work together in synchronization to perform a
task similar to human being, all parts of human body (brain as CPU and memory, Input units as eyes,
ears, nose etc. and output units as human voice, hands, lags etc) work together to perform a task.
In next paragraphs, we define some basic terms associated with microprocessor based systems.
2.1 EXPLANATION OF TERMS RELATED TO THE MICROPROCESSOR/COMPUTERS
Before we go on, it is necessary to understand some basic terms.
Signal A variable parameter by which information is conveyed through an electronic circuit or wire.
Digital Signal Operating by the use of discrete signals to represent data in the form of numbers. A
discrete-time signal having a set of discrete values is called a digital signal. Note that sampling an analog
signal produces a discrete-time signal. Then quantization of its values produces a digital signal.
An Address is a pattern of 0s and 1s that represents a specific location in memory or a particular I/O
device. Typical 8-bit microprocessors have 16 address lines, and, these 16 lines can produce 2 16 unique
16-bit patterns from 0000 0000 0000 00002 to 1111 1111 1111 11112 (0000H to FFFFH) representing
65,536 different address combinations/memory locations.
An Arithmetic-logic unit (ALU) is a digital circuit that performs arithmetic and logic operations on two or
more n-bit digital words. The value of n can be 4, 8, 16, 32, or 64 Bits. Typical computing operations
performed by an ALU are addition, subtraction, ANDing, ORing, and comparison of two n-bit digital words.
The size of the ALU defines the size of the microprocessor. For example, a 32-bit microprocessor
contains a 32-bit ALU.
The Bit is an abbreviation for the term binary digit. A binary digit can have only two values, which are 0
and 1, whereas a decimal digit can have 10 values, represented by the symbols 0 through 9.
A number of bits taken as a group are called a word. For example, a 32-bit microprocessor can process a
32-bit word or 8-bit microprocessor can process an 8-bit word.
An 8-bit word is referred to as a byte, and a 4-bit word is known as a nibble. A byte contains two nibbles.
A bit is a single binary digit of value logic 1 or logic 0. A nibble is a group of bits, e.g. 1010 2 is a nibble. A
byte is a group of 8 bits e.g. 101001112 is a byte and the byte is made up of two nibbles 1010 2 and
01112.
The Microprocessor based system consist at least a microprocessor and input/output devices and Memory.
This is the difference between the microprocessor and the microprocessor based system (microcomputer).
A bus consists of a number of conductors (wires) organized to provide a means of communication or data
transfer among different elements in a microprocessor system. The conductors in a bus can be grouped in
terms of their functions. A microprocessor normally has an address bus, a data bus, and a control bus.
Address bits are sent to memory or to an external device on the address bus. The Instructions from
memory, and data to/from memory or external devices, normally travel on the data bus. The Control
signals for the other buses and among system elements are transmitted on the control bus.
13
The Clock is analogous to `human heart beats. The microprocessor requires synchronization among its
components, and this is provided by a clock or timing circuits i.e. the microprocessor is a synchronous
electronic integrated circuit.
The instruction set of a microprocessor is a list of operations/commands that the microprocessor circuit
is designed to execute. Typical instructions are ADD, SUBTRACT, and STORE individual instructions are
coded as unique bit patterns which are recognized and executed by the microprocessor. If a
microprocessor has 3 bits allocated to the representation of instructions, the microprocessor will recognize
a maximum of 23, or eight different instructions. In other word, the microprocessor will have a maximum
of eight instructions in its instruction set. It is obvious that some instructions will be more suitable than
others to a particular application. For example, if a microprocessor is to be used in a calculating mode, the
instructions/operations such as ADD, SUBTRACT, MULTIPLY, DIVIDE and LOGICAL OPERATIONS would be
desirable. In a control application, the instructions inputting digitized signals to the processor and
outputting digital control variables to external circuits are essential. The number of instructions necessary
in an application will directly influence the amount of hardware in the chip set and the number and
organization of the interconnecting bus lines.
The Pipelining is a technique that overlaps instruction fetch (instruction read) and instruction execution.
In other word, pipelining is the fetching of current instruction and execution of the previously fetched
instruction simultaneously. This allows microprocessors processing operation to be broken down into
several steps (dictated by the number of pipeline levels or stages) so that the individual step outputs can
be handled by the microprocessor in parallel. The Pipelining is often used to fetch the microprocessors
next instruction while executing the current instruction, which speeds up the overall operation of the
microprocessor considerably.
The Random-access memory (RAM) is storage medium for group of bits or words whose contents can
be read as well as altered at specific addresses (that is why it called read/write memory). A RAM normally
provides volatile storage, which means that its contents are lost in case power is turned off. RAMs are
fabricated on chips and have typical densities of 4096 bits to 1 megabit per chip. These bits can be
organized in many ways: for example, as 4096 x 1 bit words or as 2048 x 2 bit words. RAMs are normally
used for the storage of temporary data and intermediate results as well as programs that can be reloaded
from a backup nonvolatile source. RAMs are capable of providing large storage capacity, in the megabit
range.
The Read-only memory (ROM) is storage medium for the group of bits called words, and its contents
can easily read but cannot normally be altered once programmed. A typical ROM Is fabricated on a chip
and can store, for example, 2048 eight-bit words, which can be accessed individually by presenting to it
one of 2048 addresses. This ROM is referred to as a 2K x 8-bit ROM. 1011 01112 is an example of an 8-bit
word that might be stored in one location in this memory. A ROM is a nonvolatile storage device, which
means that its contents are retained in case power is turned off. Because of this characteristic, ROMs are
used to store programs (instructions and data) that must always be available to the microprocessor.
A register can be considered as volatile storage (RAM) for a number of bits. These bits may be entered
into the register simultaneously (in parallel) or sequentially (serially) from right to left or from left to right,
1 bit at a time. An 8-bit register storing the bits or 8-bit word 111100002 are represented as follows:
1
The word micro is used in electronics and in science generally, to mean one-millionth or 1 x 106. It has
also entered general language to mean something very small circuit components fabricated by LSI or VLSI
technology for example, a very small processor or microprocessor. It has also become an abbreviation
for microprocessor, microcomputer, microprocessor-based system or a microcontroller indeed almost
anything that has micro in its name. In the scientific sense, the word micro is represented by the Greek
letter (mue). It was only a small step for microprocessor to become abbreviated to P.
14
(CPU) in a computer system or handheld device. Microprocessors made possible the advent of the
microcomputer. At the heart of all personal computers and most working stations sits a microprocessor.
The Microprocessors also control the logic of almost all digital devices, from handheld calculator to fuelinjection systems for automobiles.
Notice that a microprocessor cannot work alone and must be interfaced with peripheral support chips
(memory, input-output devices etc.) in order to perform a function. The Microprocessor receives
instruction (binary code) from memory and accepts binary data input according to the command from
memory or input device and provide the result to the output device. Actually we do not work with only
microprocessor but a microprocessor based system (described in next topic). However, we study the
microprocessor to work with microprocessor based system. Three basic characteristics that differentiate
one microprocessor to other:
Bandwidth is the number of bits processed in a single instruction. Clock speed is given in megahertz
(MHz); the clock speed determines that how many instructions per second the processor can execute.
In above both cases, the higher the value of BW and clock speed, the more powerful will be the CPU. For
example, a 16-bit microprocessor that runs at 8MHz is more powerful than an 8-bit microprocessor that
runs at 3MHz. In addition to bandwidth and clock speed, the microprocessors are classified as being either
RISC (reduced instruction set computer) or CISC (complex instruction set computer) will discuss RISC and
CISC later in this Chapter.
Microprocessor or CPU
ALU
Registers
Instruction
Decoder
Figure 2.1: Typical Microprocessor Block diagram
The microprocessor system can be divided into two categories: the microprocessor based computer for
general purpose and microprocessor based system
PC for dedicated purpose as defined in sections 2.3 and
2.4, respectively.
2.3 INTRODUCTION TO MICROPROCESSOR BASED SYSTEM
To perform a function or useful task we have to form a system by using microprocessor as a CPU and
interfacing memory, input and output devices to it. A system designed using a microprocessor as its CPU
is called a microcomputer.
The Microprocessor based system (single board microcomputer) consists of a microprocessor as CPU,
semiconductor memories like the ROM/EPROM and the RAM, input device, output device and interfacing
devices. The memories, input device, output device and interfacing devices are called peripherals. The
popular input devices are keyboard and compact disk (CD) and the output devices are printer, LED/LCD
displays, CRT monitor, etc.
Address bus
Outside
Real World
(Analog)
To/From
Input/output
Port/Device
(Peripherals)
ADC/DAC
A0-An-1
Data
Microprocessor
RAM
ROM
(CPU)
bus
D0-Dn-1
I/OW I/OR MW MR
Data bus
Control bus
Figure 2.2: A typical Architecture of the Microprocessor based Computer system
The above block diagram (figure 2.2) shows the organization of a microprocessor based system. In this
system, the microprocessor is the master and all other peripherals are slaves. The master controls all the
peripherals and initiates all operations.
The work done by the processor can be classified into the following three groups.
15
16
embedded microcontrollers, which just mean that they are part of an embedded system. Microcontrollers
are typically used for dedicated applications or smart machines such as automotive systems, home
appliances, and home entertainment systems. Examples of typical microcontrollers are the Intels 8051,
Motorolas 6811, Zilogs Z8 and PIC (peripheral interface controller) 16xx from Microchip Technology.
Microcontroller
(Single IC)
I/O Ports
ALU
Microprocessor (CPU)
Control and Timing unit
RTC
Registers
Instruction
Decoder
Figure 2.3: A typical block diagram of a microcontroller with its internal components
Microcontrollers Vs Microprocessors
1. Microprocessors
Targeted for high end of market where performance matters.
High power dissipation.
Almost all instructions are byte handling; only one or two instructions are bit handling in a
microprocessor.
Microcomputer
High cost.
Need peripheral devices to work.
Mostly used in microcomputers or General Purpose.
A microprocessor requires an external memory for program/data storage. Instruction execution requires
movement of data from the external memory to the microprocessor or vice versa. Usually,
microprocessors have good computing power and they have higher clock speed to facilitate faster
computation.
2. Microcontrollers
Targeted for low end of market where performance does not matter
Low power dissipation.
Low cost.
Bit handling instructions are in vicinity in microcontroller i.e. Microcontrollers have many bithandling instructions, while microprocessor has one or two.
Microprocessor, memory and serial/ parallel ports, all integrated into single chip, that is why its a
complete computer on a chip.
A microcontroller does not require much additional interfacing ICs for operation and it functions as a
standalone system. Mostly used in embedded systems or real time, dedicated systems. The operation of a
microcontroller is multipurpose and application specific. A microcontroller has required on-chip memory
with associated peripherals.
2.5
COMPUTER ARCHITECTURES
17
complex instruction took several clock cycles, while data flow path control words for each clock cycle were
stored in a much faster micro program memory as shown in figure 2.4. The concept of micro programming
allowed for emulation of arbitrary instruction sets and creation of specialized instructions, while speeding
up the execution. It is difficult to pipeline compared to RISC. Large instruction set helps assembly
language programmers by providing flexibility to write effective and short program. CISC processor
support many addressing modes for the memory access and data transfer instructions. The Intel
8085/80X86, Motorolas 68000 microprocessor are based on CISC.
Instruction
Pointer (PC)
PROGRAM
MEMORY
DATA
MEMORY
(Instructions)
Microinstruction
generator
(1 instruction = m
micro instruction)
Micro-program
memory
Microinstruction
decoder
Timing and
control for data
flow path
(Micro-instruction)
Figure 2.4: The CISC architecture
PROGRAM
MEMORY
DATA
MEMORY
(Instructions)
Instruction register
Instruction
decoder
Timing and
control for data
flow path
18
The Von Neumann Architecture is named after the mathematician and early computer scientist John
Von Neumann. The Von Neumann machines have shared signals and memory for code and data. Thus, the
program can be easily modified by itself since it is stored in read-write memory. There are no separate
instructions to provide separate control signals for data transfer from/to program and data memory as
shown in figure 2.6. For example, the 8085/86 microprocessors.
CPU
Figure 2.6: The von-Neumann memory architecture
In Harvard Memory Architecture (shown in figure 2.7), there are separate memories for program and
data with their distinct address and data bus. Both memory organizations have separate control signal as
separate instructions are used for data transfer from/to program and data memory. It is possible to access
program memory and data memory simultaneously. Microcontrollers are characterized by having small
amounts of program (flash memory) and data (SRAM) memory, with no cache, and take advantage of the
Harvard architecture to speed processing by concurrent instruction and data access. The separate storage
means the program and data memories can have different bit depths, for example using 16-bit wide
instructions (in program memory) and 8-bit wide data (in data memory). They also mean that instruction
pre-fetch can be performed in parallel with other activities. Examples include, the AVR by Atmel Corp,
the PIC by Microchip Technology, Inc. , Intel 8051 microcontroller series and the ARM Cortex-M3
processor (not all ARM chips have Harvard architecture).
Program
Memory
Data
Memory
Both memories use different address and data lines
CPU
Figure 2.7: Harvard memory architecture
19
When the ALU performs arithmetic and logical operations on a byte (8-bits) at an instruction, the
microcontroller is an 8-bit microcontroller. The internal bus width of 8-bit microcontroller is of 8-bit.
Examples of 8-bit microcontrollers are Intel 8051 family and Motorola MC68HC11 family.
The 16-Bit Microcontroller
When the ALU performs arithmetic and logical operations on a word (16-bits) at an instruction, the
microcontroller is an 16-bit microcontroller. The internal bus width of 16-bit microcontroller is of 16-bit.
Examples of 16-bit microcontrollers are Intel 8096 family and Motorola MC68HC12 and MC68332 families.
The performance and computing capability of 16 bit microcontrollers are enhanced with greater precision
as compared to the 8-bit microcontrollers.
The 32-Bit Microcontroller
When the ALU performs arithmetic and logical operations on a double word (32- bits) at an instruction, the
microcontroller is an 32-bit microcontroller. The internal bus width of 32-bit microcontroller is of 32-bit.
Examples of 32-bit microcontrollers are Intel 80960 family and Motorola M683xx and Intel/Atmel 251
family. The performance and computing capability of 32 bit microcontrollers are enhanced with greater
precision as compared to the 16-bit microcontrollers.
REVIEW QUESTIONS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
Why do computers use the binary number system instead of the decimal number system?
Differentiate Hardware and Software?
What are the RAM and ROM?
Why is RAM called volatile memory?
Why synchronous digital circuit needs a clock signal?
What is the function of Bus?
What do you mean by instruction and instruction set?
What is a Microprocessor?
What is the difference between a Microprocessor and a Microcomputer?
Differentiate between microprocessors and microcontroller in one line.
Define bit, byte, nibble and word.
Which type of memory architecture of the 8051 has?
What does it mean by embedded system?
What is the difference between microprocessor and CPU?
Compare RISC and CISC.
Differentiate Von-neumann and Harvard memory architecture.
Draw the typical block diagram of a microprocessor, Microcomputer and microcontroller.
What do you mean by the power of a Microprocessor? Mention the Architectural Parameters to distinguish
between Microprocessors.
19. Explain the organization of microprocessor based system with its block diagram.
20. Give at least three examples for embedded system.
21. What is the advantage of separate data and program memory (Harvard memory architecture)?
20
CHAPTER-3
INTRODUCTION TO MICROCONTROLLER, EMBEDDED PROCESSOR AND SYSTEM
Even though often nearly invisible, embedded systems are everywhere. Embedded systems are present in
many industries, including industrial automation, defense, transportation, our home and aerospace. For
example, NASAs Mars Path Finder, ISROs Mars Orbiter mission, missile guidance system, electronic
appliances, and the automobile all contain numerous embedded systems. Every day, people throughout
the world use embedded systems without even knowing it. In fact, the embedded systems invisibility is its
very beauty: users reap the advantages without having to understand the intricacies of the technology.
Remarkably adaptable and versatile, embedded systems can be found at home, at work, and even in
recreational devices. Indeed, it is difficult to find a segment of daily life that does not involve embedded
systems in some way.
INTRODUCTION TO MICROCONTROLLER
Microcontroller is a programmable digital processor with necessary peripherals. In other words, we can
say that a microcontroller is an entire computer manufactured on a single chip. Both microcontrollers and
microprocessors are complex sequential digital circuits meant to carry out job according to the program /
instructions.
Microcontrollers are usually dedicated devices embedded within an application. For example,
microcontrollers are used as engine controllers in automobiles and as exposure and focus controllers in
cameras. In order to serve these applications, they have a high concentration of on-chip facilities such as
serial ports, parallel input-output ports, timers, counters, interrupt control, analog-to-digital converters,
random access memory, read only memory, etc. The I/O, memory, and on-chip peripherals of a
microcontroller are selected depending on the specifics of the target application. Since microcontrollers are
powerful digital processors, the degree of control and programmability they provide significantly enhances
the effectiveness of the application.
Embedded control applications also distinguish the microcontroller from its relative, the general-purpose
microprocessor. Embedded systems often require real-time operation and multitasking capabilities. Realtime operation refers to the fact that the embedded controller must be able to receive and process the
signals from its environment as they are received. That is, the environment (temperature of a furnace)
must not wait for the controller to become available. Similarly, the controller must perform fast enough to
output control signals to its environment when they are needed. Again, the environment must not wait for
the controller.
EMBEDDED PROCESSOR AND APPLICATION AWARENESS
The processors found in common personal computers (PC) are general-purpose or universal processors
such as Intels x86, Power PC microprocessor, AMD processor etc. They are complex in design because
these processors provide a full scale of features and a wide spectrum of functionalities.
They are designed to be suitable for a variety of applications. The systems using these universal
processors are programmed with a multitude of applications. For example, modern processors have a
built-in memory management unit (MMU) to provide memory protection and virtual memory for
multitasking-capable, general-purpose operating systems. These universal processors have advanced
cache logic. Many of these processors have a built-in math co-processor capable of performing fast
floating-point operations. These processors provide interfaces to support a variety of external peripheral
devices. These processors result in large power consumption, heat production, and size. The complexity
means these processors are also expensive to fabricate. In the early days, embedded systems were
commonly built using general-purpose processors.
Because of the great improvement in advancements made in microprocessor technology in recent years,
embedded systems are increasingly being built using embedded processors instead of general-purpose
processors. These embedded processors are special-purpose processors designed for a specific class of
applications. The key is application awareness, i.e., knowing the nature of the applications and meeting
the requirement for those applications that it is designed to run.
One class of embedded processors focuses on size, power consumption, and price. Therefore, some
embedded processors are limited in functionality, i.e., a processor is good enough for the class of
applications for which it was designed but is likely inadequate for other classes of applications. This is one
reason why many embedded processors do not have fast CPU speeds. For example, the processor chosen
for a personal digital assistant (PDA) device does not have a floating-point co-processor because floatingpoint operations are either not needed or software emulation is sufficient. The processor might have a 16bit addressing architecture instead of 32-bit, due to its limited memory storage capacity. It might have a
21
200MHz CPU speed because the majority of the applications are interactive and display-intensive, rather
than computation-intensive. This class of embedded processors is small because the overall PDA device is
slim and fits in the palm of our hand. The limited functionality means reduced power consumption and
long-lasting battery life. The smaller size reduces the overall cost of processor fabrication.
On the other hand, another class of embedded processors focuses on performance. These embedded
processors are powerful and packed with advanced chip-design technologies, such as advanced pipeline
and parallel processing architecture. These processors are designed to satisfy those applications with
intensive computing requirements not achievable with general-purpose processors. An emerging class of
highly specialized and high-performance embedded processors includes network processors developed for
the network equipment and telecommunications industry. Overall, system and application speeds are the
main concerns.
Yet another class of embedded processors focuses on all four requirements performance, size, power
consumption, and price. Take, for example, the embedded digital signal processor (DSP) used in cell
phones. Real-time voice communication involves digital signal processing and cannot tolerate delays. A
DSP has specialized arithmetic units, optimized design in the memory, and addressing and bus
architectures with multiprocessing capability that allow the DSP to perform complex calculations extremely
fast in real time. A DSP outperforms a general-purpose processor running at the same clock speed many
times over comes to digital signal processing. These reasons are why DSPs, instead of general-purpose
processors, are chosen for cell phone designs. Even though DSPs are incredibly fast and powerful
embedded processors, they are reasonably priced, which keeps the overall prices of cell phones
competitive. The battery from which the DSP draws power lasts for hours and hours.
System-on-a-chip (SoC) processors are especially attractive for embedded systems. The SoC processor is
comprised of a CPU core with built-in peripheral modules, such as a programmable general-purpose timer,
programmable interrupt controller, DMA controller, and possibly Ethernet interfaces. Such a self-contained
design allows these embedded processors to be used to build a variety of embedded applications without
needing additional external peripheral devices, again reducing the overall cost and size of the final
product. Sometimes a gray area exists when using processor type to differentiate between embedded and
non-embedded systems. It is worth noting that, in large-scale, high-performance embedded systems; the
choice between embedded processors and universal microprocessors is a difficult one.
SELECTING THE RIGHT MICROCONTROLLER UNIT
What criteria should an engineer make a choice among microcontrollers, which are used in various
applications? When we chose a microcontroller, we must examine the delivery time, costs, development
assets and development environment, in addition to the product specifications (Figure.1). Here, the
delivery time and costs, etc. are referred to as restricting conditions and the general ways to make a
selection with regard to the product specifications and the restricting conditions will be explained.
Microcontrollers are used for a wide range of applications and there are a lot of different ways to select
one. We have to organize our opinions earlier, because the points to be considered may vary depending
on the product we are planning to develop.
22
Selecting the proper microcontroller unit (MCU) for a given application is one of the critical decisions which
control the success or failure of the task. There are numerous criteria to consider when choosing an MCU,
or in general the processor technology. The following topics present an outline of the thought guiding
during the phase of selecting the right MCU.
Technologies Involved in Design Process
We can define technology as a manner of accomplishing a task, especially using technical processes,
methods, or knowledge. Three types of technologies are central to embedded system design:
i.
Design Technologies: Design technology involves the manner in which we convert our
concept of desired system functionality into an implementation.
ii.
IC technologies: Every processor must be eventually be implemented on an integrated circuit
(IC). IC technology involves the manner in which we map a digital (gate-level) implementation
onto an IC. IC technologies differ by how customized the IC is for particular design. In other
words it differs from one another by who is responsible to connect the three groups of layers of
any IC; the bottom layers or the transistor layers, the middle layers or the logic components
layer and the top layers that connect these components with wires. Three IC technologies can
be identified.
(a) Full-custom/VLSI: All the layers are optimized for a particular embedded systems
implementation. Normally it has very high cost, but gives excellent performance with small
size and power. Such technology is usually used only in high-volume or extremely
performance critical applications.
(b) Semi-custom Application-Specific IC (ASIC): In ASIC technology, the bottom layers are fully
built, leaving us to finish the upper layers. The gate array and standard cell are examples of
this IC technology.
(c) Programmable Logic Device (PLD): In this technology, all the layers already exist. The
layers implement a programmable circuit. The programming that takes place may consist of
creating or destroying connections between wires that connect gates, either by blowing a
fuse, or setting a bit in a programmable switch. PLA, PAL and FPGA are the most popular
types of PLD technology.
The designer by using some equipment and IC technology is independent from processor technology; any
type of processor can be mapped to any type of IC technology.
iii.
Processor technologies: Processor technology relates to the architecture of the computation
engine used to implement a system's desired functionality. Three processor technologies can be
identified; use of general-purpose processor (software solution), use of single-purpose
processor (hardware solution), and use of application specific processor (e.g. use of
microcontroller).
Any of the above mentioned three processor technologies can be used to implement any task. It is the job
of the designer to select the processor that optimizes some design metrics.
The subject of the above paragraph is the selection of the right processor technology that can be used to
implement a given task. For this reason, the next three subsections are used to highlight the three
processor technologies and the design metric benefits/drawbacks of each technology. In section-2 we
discuss the design metrics that can be used to quantify the suitability of the selected processor
technology. In section-3 we discuss an outline of thought process guiding the designer to select the
optimum microcontroller unit (MCU)
PROCESSOR TECHNOLOGIES
General-Purpose Processors Software Solution
This is the case of designing a microprocessor based embedded system. The microprocessor, by definition,
is a programmable device that is suitable for a variety of applications. It has a general data path. The data
path is general enough to handle a variety of computations, so such a data path typically has a large
register file and one or more general-purpose arithmetic-logic units (ALUs). An embedded system
designer, however, need not be concerned about the design of a general-purpose processor. An embedded
system designer simply uses a general-purpose processor, by programming the processors memory to
carry out the required functionality.
Using a general-purpose processor in an embedded system may result in several design metric benefits.
Time-to-market and design costs are low because the designer must only write a program but not do any
digital design. Flexibility is high because changing functionality requires changing only the program. Unit
cost may be low. Performance may be fast for computation-intensive applications, if using a fast
23
processor, due to advanced architecture features and leading-edge IC technology. However, there are also
some design-metric drawbacks. Performance may be slow for certain applications, especially in case of
real-time systems. Size and power may be large due to unnecessary processor hardware.
Single-Purpose Processors Hardware Solution
A single-purpose processor is a digital circuit designed to execute exactly one program. An embedded
system designer may create a single-purpose processor by designing a custom digital circuit.
Alternatively, the designer may purchase a predesigned single-purpose processor. Many people refer to
this part of the implementation simply as the "hardware" portion, although even software requires a
hardware processor on which to run. Other common terms include coprocessor, accelerator, and
peripheral. The data path of the single-purpose processor contains only the essential components to fulfill
the task. Since the processor only executes this one task, it is possible to hardwire the programs
instructions directly into the control logic and use a state register to step through those instructions, so no
program memory is necessary.
The use of a single-purpose processor in an embedded system results in several design metric benefits
and drawbacks, which are essentially the inverse of those for general-purpose processors. Performance
may be fast, size and power may be small, and unit cost may be low, while design time and design costs
may be high, flexibility low, unit cost high for small quantities, and performance may not match generalpurpose processors for some applications.
Application-Specific Processors
An application-specific instruction-set processor (ASIP) can serve as a compromise between the other
processor options. An ASIP is a programmable processor optimized for a particular class of applications
having common characteristics, such as embedded control, digital-signal processing, or
telecommunications.
The data path of such a processor is optimized for the application class, perhaps adding special functional
units for common operations and eliminating other infrequently used units. Using an ASIP in an embedded
system can provide the benefit of flexibility while still achieving good performance, power, and size.
Microcontrollers (MCU) and digital signal processors (DSP) are two well-known types of ASIPs that
have been used for several decades. A microcontroller is a microprocessor that has been optimized for
embedded control applications. Such applications typically monitor and set numerous single-bit control
signals but do not perform large amounts of data computations. Thus, microcontrollers tend to have
simple data paths that excel at bit-level operations and at reading and writing external bits. Furthermore,
they tend to incorporate on the microprocessor chip several peripheral components common in control
applications, like serial communication peripherals, timers, counters, pulse-width modulators, and analog
to digital converters, all of which will be covered in a later chapter. Such incorporation of peripherals
enables single-chip implementations and hence smaller and lower cost products.
SELECTION PROCESS
The process of selecting the right MCU goes through the following steps:
Step 1: Choose the right processor technology: The goal of this step is to select one of the three
processor technologies. The selection is based on the system requirements and the strengths and
weaknesses of each technology.
Step 2: Define the System Requirements: If designer decided to use MCU, he must answer the
following question What does the MCU need to do in my system? The answer to this simple question
dictates the required MCU features for the system such as speed, packaging, power consumption, program
and data memory size, the amount of I/O pins, timer, ADC and DAC, and cost per unit.
Step 3: Prepare a List of all MCUs candidate:Conduct a search for MCUs which meet all of the system
requirements. This usually involves searching the literature and also consultations. This step considered to
be successful, if the search results in more than one MCU fulfill all the system requirements. If this is so,
the designer goes to the next step. If this step failed to find any MCU that fulfill the requirement, the
designer has to go back to step 1 and selects another processor technology.
Step 4: Finalize the Selection: Attempt to reduce the list of the acceptable MCUs to a single choice. In
the following sections we are going to discuss in details the four steps. The case if step 3 failed to find
single MCU that fulfill all the system requirements will be discussed at the last section.
CHOOSING THE RIGHT PROCESSOR TECHNOLOGY
The system analysis phase of the project will result in identifying the subsystems required to implement
the given task and also the function and the specifications of each subsystem. As a matter of fact any of
the above mentioned three processor technologies can be used to implement any of the subsystems. With
24
each processor technology has its own strength and weakness, it is important to quantify the suitability of
each technology to implement the subsystems. In most applications the following metrics can be used to
quantify the suitability of processor technology (accordingly, they are needed to be considered before
selecting the processor technology).
Cost: In the case of using off the shelf products for the implementation of the system, this metric
represents the cost of the used ICs, e.g., the cost of the selected MCU together with the supporting ICs
that may be needed to fulfill the system requirements. In the case of designing special hardware, the cost
will consist of two parts: the nonrecurring engineering cost (NRE) (the first silicon cost including the
research and development cost), and the cost of manufacturing the unit.
Performance (Speed): The execution time of the system or the processing power. It is usually taken to
mean the time required to complete a task (latency or response time), or as the number of tasks that can
be processed per unit time (throughput). Factors which influence throughput and latency include the clock
speed, the word length, the number of general purpose registers, the instruction variety, memory speed,
programming language used, and the availability of suitable peripherals.
Size: The physical space required by the system, often measured in bytes for software, and number of
gates or transistors for hardware. In case of using off the shelf products (as in case of using MCU or MPU),
the size is the physical area required to accommodate the sockets of the used ICs (the footprint).
Power: The amount of power consumed by the system, which may determine the lifetime of a battery, or
the cooling requirements of the IC, since more power means more heat.
1. Heat generation is a primary enemy in achieving increased performance. Newer processors are larger
and faster, and keeping them cool can be a major concern.
2. Reducing power usage will be the primary objective in case of designing a project that needs the
components to be crammed into small space. Such applications are very sensitive to heat problems.
3. With millions of PCs in use, and sometimes thousands located in the same company, the desire to
conserve energy has grown from a nonissue to a real issue in the last five years.
4. Power consumption has an impact on everything from cooling method selection to overall system
reliability.
Flexibility: The ability to change the functionality of the system without incurring heavy additional cost.
Software is typically considered very flexible. Generally speaking, single chip MCU are not very flexible in
use compared with single chip microprocessor. The latter, if based on a standardized bus, can be
reconfigured by swapping peripherals and altering input-output routine. The ultimate in flexibility is
probably achieved through the use of general-purpose processor.
Reliability: Reliability is an attribute of any computer-related component (software, hardware, or a
network, for example) that consistently performs according to its specifications. It has long been
considered one of three related attributes that must be considered when making, buying, or using a
computer product or component.
Reliability, availability, and serviceability -RAS, for short are considered to be important aspects to
design into any system. In theory, a reliable product is totally free of technical errors; in practice,
however, vendors frequently express a products reliability quotient as a percentage. Evolutionary
products (those that have evolved through numerous versions over a significant period of time) are
usually considered to become increasingly reliable, since it is assumed that bugs have been eliminated in
earlier releases. Software bugs, instructions sensitivity, and problems that may arise due to durability of
the EEPROM and Flash memories (The nature of the EEPROM architecture, limits the number of updates
that may be reliably performed on a single location this is called the durability of the memory. At least
10,000 updates are typically possible for EEPROM and 100 updates for flash memory), are some of the
possible reasons of the failure of embedded systems. Reliability of a system depends on the number of
devices used to build the system. As the number of units used increases, the probability of error (or
failure) increases which means lower reliability. This is why the microcontroller-based systems are,
generally, more reliable than microprocessor-based systems.
Availability - Second source suppliers: Most of the major microcontrollers and microprocessors are
now made by more than one manufacturer (Atmel, Siemens and Philips are the biggest manufacturers for
Intel 8051 family).
Serviceability - Manufacturers support: Manufacturers support covers the provision of a range of
services from the development system and its associated software through the documentation,
maintenance of the development system and providing answers to technical queries.
Maintainability: The ability to modify the system after its initial release, especially by designers who did
not originally design the system.
25
Range of complementary hardware: For some applications the existence of a good range of compatible
ICs to support the Microcontroller / microprocessor may be important.
Special environmental constraints: The existence of special requirements, such as military
specifications or minimum physical size and weight, may well be overriding factors for certain tasks. In
such cases the decision is often an easy one.
Ease of use: This will affect the time required to develop, to implement, to test it, and to start using the
system. These three factors design time, manufacturing time, and testing time- are the main factors
defining the time-to-market merit which is very important if the system is designed for commercial use. In
commercial applications, introducing an embedded system to the marketplace early can make a big
difference in the system profitability, since market windows for product are becoming quit short. This is
very important factor because the time-to-market factor defines the profitability.
Software Support: Newer, faster processors enable the use of the latest software. In addition, new
processors such as the Pentium with MMX Technology, enable the use of specialized software not usable
on earlier machines. Easier language means shorter time to learn and better maintainability
Motherboard Support: The processor we decide to use in our system will be a major determining factor
in what sort of chipset we must use, and hence what motherboard we buy. The motherboard in turn
dictates many facets of our system's capabilities and performance.
Correctness: Our confidence that we have implemented the system's functionality correctly. We can
check the functionality throughout the process of designing the system, and we can insert test circuitry to
check that manufacturing was correct.
Safety: The probability that the system will not cause harm. Metrics typically compete with one another;
Improving one often leads to worsening of another. For example, if we reduce an implementations size,
the implementations performance, power consumption may suffer. Keeping this in mind and also the fact
that each processor technology has its own metrics strength and weakness, the key embedded system
design challenge is the simultaneous optimization of competing design metrics. To optimize the system
under design, it is the job of the designer to study the rule of each subsystem within the complete frame
of the system, and from here he can identify the most critical metrics that optimize the subsystem. Based
on that, the designer can define the most suitable technology that he is going to use to implement each
subsystem. Accordingly, this phase will determine the subsystems that the designer is recommending the
use of MCU for implementation and also the requirements from each MCU. The complete list of
requirements must cover all (or the maximum possible number) the metrics mentioned above. For
example, it must cover the requirements from hardware and software resources, performance, interfacing
with other subsystems, power supply specifications, etc.
WHAT DOES THE MCU NEED TO DO IN THE SYSTEM?
In this section we present an outline of the thought process guiding the designer to prepare a complete
list of the system requirements. This represents the most important step towards finalizing the selection
process. The way of selection takes the form of questions to be answered by the designer. Some of the
questions that the designer has to ask and to find answer for them are:
Questions related to the system hardware requirements
All MCUs have on-chip resources to achieve a higher level of integration and reliability at a lower cost. An
on-chip resource is a block of circuitry built into the MCU which performs some useful function under
control of the MCU.
Built-in resources increase reliability because they do not require any external circuitry to be working for
the resource to function. They are pre-tested by the manufacturer and conserve board space by
integrating the circuitry into the MCU. The on-chip resources defer from one MCU to another. Then it is
very important in the analysis phase to define exactly the system hardware requirements to be able to
select the proper MCU. Failing to get an MCU that fulfill all the system hardware requirements means one
of two possibilities:
1. To study whether the budget and the available space constraints are going to allow you to select the
nearest suitable MCU and support it with additional ICs, to fulfill the system requirements, or not?
2. The possibility of going to another processor technology (e.g. use of microprocessor or use of
single-purpose processor). Some of the questions to be asked and answer are:
What peripheral devices are required? How many devices/bits (I/O pins) need to be controlled? Among the
many possible types of I/O devices to be controlled / monitored are RS- 232C terminals, switches, relays,
keypads, sensors (temperature, pressure, light, voltage, etc.), audible alarms, visual indicators(LCD
displays, LEDs), analog-to-digital (A/D), digital-to-analog (D/A), liquid crystal display drivers( LCD), and
vacuum fluorescent display drivers (VFD).
26
What is the expected capacity of the ROM and RAM that are required to store the programs and the data?
How many timers the application needs? Timers include both real-time clocks and periodic interrupt
timers. What is the range and resolution of the timer? Also consider if our system needs any Subfunctions, such as timer compare and/or input capture lines. Is our application needs some special
resources as internal/external bus capability, computer operating properly (COP) watchdog system, clock
operating properly detection, selectable memory configurations, and system integration module (SIM). Is
our application needs special arithmetic hardware resources such as multiply, divide, and table
lookup/interpolate? What is the word length? MCUs generally can be classified in to 8-bit, 16-bit, and 32bit groups based upon the size of their arithmetic and index register(s). The following questions must be
answered before deciding about the word length:
a. Is a lower-cost 8 -bit MCU able to handle the requirements of the system, or is a higher-cost 16bit or 32-bit MCU required?
b. Can 8-bit software simulation of features found on the 16-bit or 32-bit MCUs permit using the
lower-cost 8-bit MCU by sacrificing some code size and speed? For example, can an 8 -bit MCU be
used with software macros to implement 16-bit accumulator and indexing operations? These
questions are directly related to the choice of implementation language (high-level versus
assembler).
Questions related to the software (instruction set) requirements
Programs written for one will not run on the other manufacturers MCU. The instruction set, registers,
addressing modes, etc., of each MCU should be considered carefully, as they play critical roles in the
capability of the system. Some of the questions to be answered are: is the application to be bit
manipulating or number crunching? Remember that bit manipulation instructions (bit set, bit clear, bit
test, bit change, branch on bit set, branch on bit clear) allow easier implementation of controller
applications. Once data is received, how much manipulation is required? Is the system to be driven by
interrupt, Polled or human responses? Which implementation language are you going to use? As
mentioned before, the choice of implementation language (high-level versus assembler) can greatly affect
system throughput, which can then dictate the choice of 8-, 16-, and 32- bit architectures. System cost
restraints may override this. Do you need any special instructions to be available which could be used in
our system, such as multiply, divide, and table lookup/interpolate? Do we need the instruction set to
include instructions to handle low-power modes for battery conservation, such as stop low-power stop,
and/or wait?
How about big field instructions? In other words, do we prefer MCU with Long Instruction Word (LIW)?
Remember that the real measure of performance is how many clock cycles the system takes to complete
the task in hand, not how many instructions were executed. What are the recommended addressing
modes?
Questions related to the performance
As mentioned before, the performance can be measured by the time required to complete a task. One of
the factors which influence throughput is the clock speed. Clock speed, or more accurately bus speed,
determines how much processing can be accomplished in a given amount of time by the MCU. Some MCUs
have a narrow clock speed range, whereas others can operate down to zero. Sometimes a specific clock
frequency is chosen to generate another clock required in the system, for example, for serial baud rates.
In general, computational power, power consumption, and system cost increase with higher clock
frequencies. System costs increase with frequency because not only does the MCU cost more, but so do all
the support chips required, such as RAMs, ROMs, PLDs (programmable logic device), and bus drivers.
Concerning the performance, some of the questioned that must be answered are: is it a real-time
application, and if so, are we going to build or purchase a real-time kernel program or may be a public
domain version will suffice? What is the expected CPU core throughput? What is the CMU bus speed? Or
what is the clock speed? For serial ports, what is the data rate?
Questions related to MCU interrupts
Examining the interrupt structure is a necessity when constructing a real-time system. The designer
should look at:
How many interrupt lines or levels are there versus how many does our system require? Is there an
interrupt level mask?
Once an interrupt level is acknowledged, are there individual vectors to the interrupt handler routines or
must each possible interrupt source be polled to determine the source of the interrupt. In speed critical
applications, such as controlling a printer, the interrupt response time, for example, the time from the
27
start of the interrupt (worst case phasing relative to the MCU clock) until the first instruction in the
appropriate interrupt handler is executed, can be the selection criterion in determining the right MCU.
Questions related to power supply
Is a single or multiple voltage power supply required for the system? What is the power supply tolerance?
Is the device characterized for operation at our system supply voltage? Are the voltages to be held to a
small fixed percent variation or are they to operate over a wider range? What is the operating current? Is
the product to be a core battery operated? If battery operated, should rechargeable be used, and if so,
what is the operational time required before recharging and the required time for recharging?
Questions related to size and environment
Are there size and weight restrictions or aesthetic considerations such as shape and/or color? Is there
anything special about the operating environment such as military specifications, temperature, humidity,
atmosphere (explosive, corrosive, particulates, etc.), and pressure/altitude?
Questions related to available budget and time
Does our schedule contain enough time and personnel to develop our application? The importance of this
question will be very clear if the designer failed to find suitable MCU and the only solution is to design
single-purpose processor.
FINALIZING THE SELECTION
As a final step to help in the selection process, built a table listing each MCU under consideration on one
axis and the important attributes on the other axis. Then fill in the blanks from the manufacturers data
sheets to obtain a fair side-by-side comparison. Some manufacturers have pre made comparison sheets of
their MCU product line which makes this task much easier, but as with all data sheets, be sure they are
up-to-date with current production units.
From the discussions given at section - 2, some of the possible attributes are: Price, On-chip RAM, ROM,
EPROM, and EEPROM, Timer(s) (number of timers, range, resolution, etc.),Watchdog timer, A/D and D /A,
Serial ports and parallel ports (I/O control lines), Bus speed (minimum/maximum)? Special hardware
(multiply/divide, table lookup/interpolate, etc.) Special instructions (multiply, divide, etc.) word length.
Number of available interrupts, interrupt response time (time from start of interrupt to execution of the
first interrupt handler instruction), Package size/type (ceramic DIP (dual in-line package) or LCC, plastic
0.3-inch DIP or 0.6-inch DIP, shrink DIP (.071-inch pin spacing), PLCC (plastic-leaded chip carrier), PQFP
(plastic quad flat pack), EIAJQFP, SOIC (small outline integrated circuit), some involve surface mount
technology, Power supply requirements and any other items important to our system design.
Reference:
1. Takawira F., Dawoud D.S., Selecting The Right Microcontroller Unit Zimb. J. Sci. Technol., Vol. 4, no. 1, p 39-46.
REVIEW QUESTIONS
1. Justify the statement microcontrollers are normally less expensive than microprocessors.
2. Define the term embedded processor?
3. Why an embedded system is called dedicated system?
4. List the differences between embedded processor and general processor.
5. List the criteria to choose a microcontroller unit.
6. Can we use a general purpose processor (x86) as an embedded processor?
28
CHAPTER-4
THE 8051 MICROCONTROLLER
Intel Corporation introduced an 8-bit microcontroller called the 8051. The 8051 became widely popular
after Intel allowed other manufacturers to make the market by any upgrade version of the 8051 with the
condition that they remain instruction set-compatible. This condition means that if we write a program for
the 8051, it will run on any one of them regardless of the manufacturer.
The 8051 family of
microcontrollers is based on an architecture which is highly optimized for embedded control systems. It is
used in a wide variety of applications from military equipment to automobiles to the keyboard on our PC.
Second only to the Motorola 68HC11 in eight bit processors sales, the 8051 family of microcontrollers is
available in a wide array of variations from manufacturers such as Intel, Philips, Atmel, and Siemens.
These manufacturers have added numerous features and peripherals to the 8051 such as Flash ROM,
analog to digital converters, watchdog timers, and pulse width modulated outputs.
Variations of the 8051 with clock speeds up to 40MHz and voltage requirements down to 1.5 volts are
available. This wide range of parts on one core (single IC) makes the 8051 family an excellent choice as
the base architecture for a manufacturers entire line of products since it can perform many functions and
developers will only have to learn this one platform. Broad Classification of different microcontroller chips
could be as follows:
Embedded (Self -Contained) 8 - bit Microcontroller
16 to 32 Microcontrollers
DSP Microcontrollers
8051 Microcontroller
The 8051 is the original member of the 8051 family. The 8051 has 4KB of program/code memory
implemented as on-chip Read Only Memory (ROM). The 8051 has 128 bytes of On-chip Random Access
Memory (RAM).The 8051 can excess additional of 60 Kbyte of program memory and 64Kbyte of external
data memory. The 8051 has two timer/counters, a serial port, four general purpose parallel input/output
ports, and interrupt control logic with five sources of interrupts. Besides internal RAM, the 8051 has
various Special Function Registers (SFR), which are the control and data registers for on-chip facilities.
The SFRs also include the accumulator A, the B register, and the Program Status Word (PSW), which
contains the CPU flags. Programming the various internal hardware facilities of the 8051 is achieved by
placing the appropriate control words into the corresponding SFRs.
8052 Microcontroller
The 8052 has 256 bytes of internal RAM and 8K of internal code ROM. The 8051 and 8052 internal ROM
cannot be programmed by the user. The user must supply the program to the manufacturer, and the
Table 4.1: Comparison of the Intels 8051family members
Features
On-chip ROM
On-chip RAM
Timer
I/O pins
Serial ports
Interrupt Sources
8051
4K bytes
128 bytes
2
32
1
6
8031
0K bytes
128 bytes
2
32
1
6
29
8032
0K
256 bytes
3
32
1
8
8052
8 K bytes
256 bytes
3
32
1
8
manufacturer programs the microcontrollers during production. Due to the setup costs, the factory
masked ROM option is not economical for small quantity productions.
UV-EPROM version
The 8751 and 8752 are the On-chip Ultra Violet Erasable Programmable Read Only Memory (UV-EPROM)
versions of the 8051 and 8052, respectively. Many manufacturers offer the EPROM versions in windowed
ceramic and non-windowed plastic packages. These are user programmable. However, the non-windowed
versions cannot be erased. These are usually referred to as One-Time-Programmable (OTP)
microcontrollers, which are more suitable for experimental work or a product is designed and absolutely
finalized the OTP version is used for mass production since it is much cheaper in terms of price per unit.
Device Number
AT89C51
AT89LV51 (Low voltage version)
AT89C1051 (1/4 version)
AT89C2051(1/2 version)
AT89C52
AT89LV52
On-chip
ROM
4K
4K
1K
2K
8K
8K
On-chip
RAM
128
128
64
128
256
256
I/O
pins
32
32
15
15
32
32
Timer
Interrupt
VCC
Packaging
2
2
1
2
3
3
6
6
3
6
8
8
5V
3V
3V
3V
5V
3V
40
40
20
20
40
40
There are various speed and packaging versions of the above chips from the Atmel Corporation encoded in
chip name itself. For example, AT89C51-12PC is decoded as given below:
AT indicates manufacturer name Atmel Corporation, 8951 indicates chip number, C in between chip
number indicates CMOS technology fabrication ( LV indicates low voltage CMOS technology, 12
indicates 12 MHz clock frequency, P for plastic Dual-in- package DIP, and C is for commercial use (M
for military use).
The chips are identified by the numbering system: 8XC51 where in general, since there are exceptions,
the digit following the 8 is:
8xxx: NMOS logic
8xCxx: CMOS logic
803x: No internal program memory
805x: Factory programmed internal ROM program memory (one time programmable OTP)
87xx: Internal user programmable UV-EPROM program memory
89xx: Internal user programmable flash EPROM program memory
8xx1: 4 kilobyte internal program memory, 128 byte internal RAM
8xx2: 8 kilobyte internal program memory, 256 byte internal RAM
30
versions of the device, such as the Dallas Semiconductor 80C320, provide throughput equivalent to almost
100 MHz, compared to the original parts 12 MHz clock.
Before we look in more detail at the features of the various 8051 devices, we should note that the names
given to the various family members is always a source of confusion to new developers. For example, the
8031, 8751, 8052, 8032, 89C51, 89C52, 89C2051, C505C, C515C, C509, C868, 80C517, 83C452,
80C390, DS5000, ADC812 and MAX7651 are all members of the 8051 family. The names of the devices
provide little or no indication of the family connections.
Microcontrollers have gone through a silent evolution. The evolution can be rightly termed as silent as the
impact or application of a microcontroller is not well known to a common user, although microcontroller
technology has undergone significant change since early 1970's. Development of some popular
microcontrollers is given below:
Development tools, including assemblers, simulators and compilers are readily available as
freeware shareware and demo versions.
It is available at low cost, allowing low cost versions of in-circuit emulators, peripheral components,
and single board computers to be purchased by the student.
The 8051 is the most popular microcontroller family, with many derivatives available, and multiple
vendors manufacture it.
The 8051 architecture is available in a wide range of cost, size, and performance. For example, one
version is available in a 20-pin small outline DIP package for less than 50, and another one is
about eight to ten times the speed of the original 8051.
The 8051 CPU is also available as a building block for custom chip designs, and is the most
popular CPU for system on a chip designs. It is also the only readily available, non-proprietary
building block CPU architecture available for chip design.
Software tools for the 8051 family, such as assemblers, compilers and simulators are available at
no cost on the internet. Hardware tools, such as the combination software development kit and incircuit emulator are available for under 5000, and complete design documentation is available on
the web to allow anyone to build their own.
In addition, the 8051 has the simplest timing specifications of a device which can address external
memory, making it practical to go into the details of the design which are necessary to understand.
With less than two dozen timing specifications (compared to several times as many for most other
equivalent processors), it is possible to cover the timing specifications in detail. Once this process
is understood, it is a straightforward jump to understanding and using the larger number of
equivalent specifications characteristic of other devices.
31
If the program fits into the on-chip ROM and if the internal RAM is sufficient, the MCS- 51 family of
microcontrollers requires no additional logic to implement a complete controller system. The following
discusses the 8051 in detail.
4.3 THE 8051 MICROCONTROLLER ARCHITECTURE
The salient features of the 8051:
32
Input/output (I/O) ports: The 32 of the pins are arranged as four 8-bit I/O ports P0P3. Twenty-four
of these pins are dual purpose (26 on the 8052) with each capable of operating as a control line or part of
the data/address bus in addition to the I/O functions. A typical internal structure is shown in figure 4.3.
Port 0: This is a dual-purpose port occupying pins 32 to 39 of the device. The port is an open-drain
bidirectional I/O port with Schmitt trigger inputs. Pins that have 1s written to them float and can be used
as high-impedance inputs. This port may be used with external memory to provide a multiplexed address
and data bus. Therefore, port 0 cannot be used as I/O when external memory is connected. The port also
outputs the code bytes during EPROM programming. External pull-up resistors are necessary during
program verification.
Port 1: This is a dedicated I/O port occupying pins 1 to 8 of the device. The pins are connected via internal
pull-ups and Schmitt trigger input. Pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs; as inputs, pins that are externally pulled low will source current via the
internal pull-ups. The port also receives the low-order address byte during program memory verification.
Pins P1.0 and P1.1 could also function as external inputs for the third timer/counter-2 for 8032/8052 as
given below:
(P1.0) T2 Timer/counter 2 external count input/clock-out
(P1.1) T2EX Timer/counter 2 reload/capture/direction control
Port 2: This is a dual-purpose port occupying pins 21 to 28 of the device. The specification is similar to that
of port 1. The port may be used to provide the high-order byte of the address bus for external program
memory or external data memory that uses 16-bit addresses. When accessing external data memory that
uses 8-bit addresses, the port emits the contents of the P2 SFR. Therefore, port 2 cannot be used as I/O
33
when external memory is connected. Some port 2 pins receive the high-order address bits during EPROM
programming and verification.
Port 3: This is a dual-purpose port occupying pins 10 to 17 of the device. The specification is similar to
that of port 1. These pins, in addition to the I/O role, serve the alternate features for the 8051 family; the
alternate functions are summarized in following table:
Figure 4.4: Figure: A schematic representation of a switch connected to a port-1, 2 or 3 (with internal pull-up resistors).
The above simple switch arrangement shown only applies to Port 1, Port 2 and Port 3, since these ports all
have internal pull-up resistors. This arrangement does not apply to Port 0, which has no internal pull-ups.
To change the port setting, we need to push the pin down to 0, against the force of the spring (figure
4.5). For the Port 0, there is no pull-up resistor (no spring) to pull up the pin to changing the state of the
input pin is not possible, the pin will always read 0 as shown in figure 4.5.
Figure 4.5: A schematic representation of a switch connected to a port-0 (without internal pull up resistors).
If we need to connect a switch (or similar device) to Port 0, an external pull-up resistor must be added: a
resistance of 10 K is appropriate here (see figure 4.6). A resistance limits the current which protect
processor transistor and interface hardware transistor as well.
34
Figure 4.6: An example of a push-button (normally open) switch input. Where there is no internal pull-up, this arrangement must be used
Reset (pin 9): The 8051 is reset by holding this input high for a minimum of two machine cycles before
returning it low for normal running. An internal resistance connects to pin 20 (V SS) allowing a power-on
reset using an external capacitor connected to pin 40 (VCC). The reset input pin should be connected to an
external resistor and capacitor, so that the processor will be properly initialized (see table 4.3) upon initial
application of power. There is a capacitor between the reset pin and the power supply, and a resistor from
the reset pin to ground. When power is first applied, the capacitor has no voltage across it, forcing the
processor to reset. After resistor R1 charges the capacitor C, the reset signal goes low (inactive) and the
processor begins executing the program beginning at location 0000H in program memory. The
recommended reset circuit is shown in figure 4.7.
Table 4.3: Reset value of the SFRs
Register
PC
Accumulator
0000
00
B
PSW
SP
DPTR
00
00
0007
0000
XTAL1 and XTAL2 (pins 19 and 18 respectively): The 80C51 on-chip oscillator is driven, usually, from an
external crystal. The XTAL1 input also provides an input to the internal clock generator circuits. A crystal
connected between XTAL1 and XTAL2 provides the feedback and phase shift required for oscillation. For
stability and consistent oscillator start-up, two capacitors in the range of 20 to 47 picofarads should be
connected from the XTAL pins to ground. If XTAL1 is being driven by an external frequency source, XTAL2
should not be connected. An external clock can also be applied to XTAL1 to allow the use of a separate
clock frequency source, such as an oscillator module. Figure 4.8 shows some standard oscillator
configurations.
To drive the device with an external clock source it is usual, for the CMOS device, to drive the XTAL1 input
with the external clock and leave the input XTAL2 floating. This is shown in figure 4.8 (c). The frequency
of the crystal oscillator connected to the 8051 family may vary from 4 MHz to 30 MHz However, to make
the 8051 based system compatible with serial port of the IBM PC, we must use 11.0592 MHz crystal
oscillator.
35
PSEN (program store enable) (pin 29): This pin provides an output read strobe to external program
memory. The output is active low during the fetch stage of an instruction. The signal is not activated
during a fetch from internal memory.
ALE/PROG (address latch enable/program pulse) (pin 30): The ALE signal is an output pulse used
to latch the low byte of an address during access to external memory. The signal rate is 1/12 the oscillator
frequency and can be used as a general-purpose clock/timing pulse for the external circuitry. The pin also
provides the program pulse input (PROG) during EPROM programming. ALE will be active only during a
MOV X and MOVC instruction.
EA/VPP (external access/programming voltage) (pin 31): This pin is either tied high or low
according to circuit requirements. If tied high the device will execute programs from internal memory
provided the address is not higher than the last address in the internal ROM/OTP. When the EA pin is tied
low, thus disabling the internal ROM, program code is accessed from external ROM. For a ROM-less
device, the EA pin must be tied low permanently and the program code accessed from external ROM could
be as much as 64KB. EPROM versions of the device also use this pin for the supply voltage (Vpp)
necessary for programming the internal EPROM. If security bit 1 is programmed, the EA will be internally
latched on reset.
36
Accumulator is a register of the ALU for the one of the operand by default. Normally B is a general
purpose register but must used in multiply and divides operations by the ALU.
Program status word (PSW) keeps the current status of the Accumulator after an operation.
Stack pointer (SP) is an 8-bit register. This pointer keeps track of stack memory (Part of R/W memory)
space where the temporary data are stored during branching operation execution in a program. The stack
pointer may be placed in anywhere in the on-chip RAM. After system reset, SP is initialized at 07H and
starting storage from location 08H. The stack pointer automatically incremented or decremented by PUSH
or POP instruction and for subroutine CALL or Return instructions, respectively.
Program Counter (PC) is the 16-bit register provides address of next instruction to be executed during
program execution and it always point Program memory (ROM) space.
Data pointer (DPTR) is another 16 bit addressing register that can be used to fetch any 8-bit data from
the data memory space (RAM). When it is not being used for this purpose, it can be used as two eight bit
registers.
Instruction decoder is read and decodes the instruction fetched into the CPU.
Parallel I/O Ports: The 8051s I/O port structure is extremely versatile and flexible. The device has 32
I/O pins configured as four 8-bit parallel ports. Each pin can be used as an input or as an output under the
software control. To reduce the number of pins, the pins allotted for parallel ports are assigned some
alternative functions as well. To access external memory, port 0 is used as a multiplexed lower order
address/ 8-bit data bus. Also, any instruction that accesses external program memory will output the
higher order byte on P2 during read cycle.
Timers/counters: The 8051 has two 16-bit timers/counters and capable of working in different modes.
Each consists of a high byte and a low byte which can be accessed by the software control. There are
mode control registers and control register to configure these timers/counters in number of ways.
Serial Port: The 8051 has a high speed full duplex serial port which is programmable in four basic
modes: 8-bit UART, 8-bit UART, interprocessor communication link. The 8051 has a serial data
communication circuit that uses register SBUF to hold data. The register SCON controls data
communication, Register PCON control data rates and pins RxD and TxD connect the serial data interface.
4.5
A Small 8051 devices typically have only some 15 I/O pins, and do not support external memory. These
devices are finding their way into applications that would have involved a small number of discrete
components (transistors, diodes, resistors, capacitors) a few years ago, but which may now be
implemented more cheaply using microcontrollers. Both the Standard and Small 8051s are aimed, largely,
at low-performance application areas, where limited memory is required, and one of the most important
considerations is product cost. This forms a large segment of the embedded market but of course not
all projects take this form. To develop applications requiring additional hardware or larger amounts of
memory, we can opt to switch to a 16-bit (or 32-bit) microcontroller environment.
37
(AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port 1
out-put buffers can sink 20 mA and can drive LED displays directly. When 1s are written to Port 1 pins,
they can be used as inputs. When pins P1.2 to P1.7 are used as inputs and are externally pulled low, they
will source current (IIL) because of the internal pull-up resistor. Port 1 also receives code data during
Flash programming and verification.
Port 3: Port 3 pins P3.0 to P3.5, and P3.7 are seven bi-directional I/O pins with internal pull-up resistor.
P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a generalpurpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s are written to Port 3 pins they
89C2051
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Description
RESET - Reset
P3.0 Port 3
P3.1 - Port 3 XTAL2 - Crystal
XTAL1 - Crystal
P3.2 - Port 3
P3.3 - Port 3
P3.4 - Port 3
P3.5 - Port 3 GND - Ground
P3.7 - Port 3
P1.0 - Port 1
P1.1 - Port 1
P1.2 - Port 1
P1.3 - Port 1
P1.4 - Port 1
P1.5 - Port 1
P1.6 - Port 1
P1.7 - Port 1
Vcc - Positive
Supply
Alternate function
RXD
TXD
I NT0
I NT1
T0
T1
Figure 4.10: Pin diagram and description for the 89C2051 microcontroller
are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current because of the pull-ups. Port 3 also receives some control
signals for Flash programming and verification. The Port 3 also serves the functions of various special
features of the AT89C2051 as listed in table 4.4:
Table 4.4: Port 3 alternative function for the 89C2051
REVIEW QUESTIONS
1. List the features of the 8051.
2. What is the difference between the 8051 and 8031?
3. How many I/O ports are available in the 8051? How many ports in the 8051 are available for I/O purpose, if
external memory is connected to the 8051?
4. Why low-power version of microcontroller is important for battery operated embedded product.
5. Which I/O port of the 8051 has no alternative function?
6. What is the difference between 8051 and 8052?
7. What is the difference between 80C51 and 89C51?
8. Upon reset, what are the contents of PC and SP?
9. In the 8051, which port needs a pull-up resistor to be used as I/O?
10. List the alternate function of port-3.
38
CHAPTER-5
ASSEMBLY LANGUAGE PROGRAMMING
The microprocessor/microcontroller works only in binary as it is a digital system. A machine language
program is a set of binary code that consists of 0s and 1s is called machine language. The writing of a
program in machine language is highly prone to error and cumbersome for programmer.
One way of looking at a microcontroller/microprocessor based system is to consider the successive
translations that occur from the high level code (a programming language such as C, C++ etc) to the
electrical signals that communicate with the transistor.
A computer system can be broken down into multiple levels or layers to show the translation of a specific
instruction into a form that can be directly processed by the computer hardware. This hierarchy of
Layers of a computer system is shown below:
High Level Language
Sum: = Sum + 1
Assembly Language
ADD A, #01H
Machine Code
Register Transfer
Gate
Transistor
Language translators such as compilers and assemblers translate high level code into machine code that
can be executed by the processor. The primary focus of this book will be from the assembly and machine
language level downward.
5.1 STRUCTURE OF ASSEMBLY LANGUAGE PROGRAM
An assembly language program is the group of instructions, which is written to perform a function. An
assembly language instruction consists of an OP-code mnemonic, generally followed by one or two
operands. The operands are the data items being manipulated and mnemonics are the commands to the
microcontroller, telling it what to do with these operands. An assembly language instruction consists of
four fields:
Memory addresses
Or Labels
Mnemonic
Operand(s)
; Comment/description (optional)
2 byte instruction
2 byte instruction
1 byte instruction
1 byte instruction
In this program besides the regular Op-code mnemonics, we also see some other mnemonics such as ORG
and END. These assembler directives give the direction to the assembler. The pseudo-instructions do not
39
produce any machine code; these are related with the assembler only, not to the microcontroller. These
special instructions inform to the assembler what to do with the mnemonics such as linker and loader and
control in that manner in which a program assembles and they stand out in the program listing. They
come into play during the assembly of a program but do not generate any executable machine code. As
such these special instructions are not a part of the instruction set, called assembler directives or
pseudo-instructions/operation. For example, the ORG 2000H instructs the assembler to load the object
code of this program starting at memory location 2000H while END directives inform the assembler that
the end of this program is reached, and thus the assembly program execution terminates. In other word,
one is for the start the program and the other one for the end of the program.
Other assembler directives are EQU (equate), DB (define byte), DW (define word), DBIT (define a Bit) and
DS (define storage).
EQU: This is used to define a constant without occupying a memory location. The EQU directive does not
set aside storage for a data item but associates a constant value with a label name so that when the
label appears in the program, its constant value will be substituted for that label. For example:
TEN
EQU 10
X:
DB 05H
ORG 1000H
MOV A, #X
; Load accumulator with (X)
ADD A, #TEN
; Add 10D (AH) to Accumulator i.e A=A+10
END
; Stop further execution
In the above program, the EQU directive assigns the decimal value 10 to the label TEN.
The DB directive allows a user to define a data byte; the number can be in decimal (D optional), binary
(B), hex format (H) or ASCII formats (string or string). The assembler will convert any format number
into hex. The DB directive is the only directive that permits character strings (enclosed in single quotes)
larger than two characters. Each character in the string is converted to the corresponding ASCII code. For
example, the following statements:
ORG 040H
Data:
DB
00110111B
Data1:
DB
40H
Message:
DB
My name is Mohit
; ASCII character code
Message1:
DB
My name is Mohit, 0
; Null-terminated character string
ORG 0040H
SQUARES:
DB
0, 1, 4, 9, 16, 25
; Squares of numbers 0 to 5
ASCII:
DB
Bharat, 0
When assembled, result in the following hexadecimal memory assignment for Program memory:
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
100A
100B
100C
100D
00
01
04
09
10
19
42
68
61
72
61
74
3A
00
In a similar manner, a programmer can define a 16-bit data by employing the DW (Define a word)
directive. The purpose of the DS (define storage) directive is to reserve storage space for a variable or a
data array. The DBIT (Define a Bit) directive defines a bit constant, which is stored in the bit-addressable
section of the internal RAM. For example, the statements:
40
ORG 200h
Label: DW
11111111B, A, 1234H
The result of the above statement in the following hexadecimal memory assignments:
0200
0201
0202
0203
FF
41
12
34
Rules
1.
2.
3.
4.
5.2 ASSEMBLER
Almost every line of source coding (except assembler directives) in an assembly language source program
translates directly into a machine code (HEX code) for a particular microprocessor/ microcontroller.
Assembly languages were develop which provide mnemonics for the machine code, plus other feature
which made programming less prone to human error. The term mnemonic (pronounced as nimonik) refer
to code and abbreviations that are easy to remember than machine code, but assembly language program
must be translated to machine code by a software program, called an Assembler, as microcontroller can
understand only binary information. Assembly language is converted into executable machine code by a
software tool referred to as an assembler; the conversion process is referred to as assembly, or
assembling the code.
The advantages of the assembler are as follows:
Assembly language operation codes (mnemonic) are easily remembered (MOV for move
instructions, JMP for jump). The assembler translates mnemonic into binary code with accuracy,
thus eliminating human errors in looking up the binary/HEX codes.
The assembler generates appropriate values to the symbols and addresses to the labels. A symbol
table consists of labels with addresses assigned to them. The labels can be used for addresses
assigned to JUMP statement and no address calculation has to be done by the user.
The assembler can reserve memory locations for data by using pseudo-instruction.
The assembler checks syntax error but cannot check logic errors in a program.
It is easy to edit (insert or delete) instructions in a program.
Assembly language is referred to as low level language because it deals directly with the internal structure
of the CPU or microcontroller. In order to write programs in assembly language, the programmer must
know internal architecture of the microcontroller, programming model (microcontrollers registers),
addressing modes and its instructions as well as other details. Therefore, the assembly language
programmer must be familiar with both the assembly language and the internal architecture of the
microcontroller for which he is programming.
In the high level languages, the programmer does not deal with the internal details of the CPU, for
example: C, C++, Java etc. An assembler is a software tool- a program, which is used to translate an
assembly language (low level language) into machine code (sometimes called object code or OP-code for
41
operation code), while a software program, called compiler is used to translate a high level program into
machine code.
There are various types of assemblers available today. We define some of them in the following
paragraphs.
One-Pass Assembler: This assembler goes through the assembly language program once and translates
the assembly language program into a machine language program. This assembler has the problem of
defining forward references. This means that JUMP instruction using an address that appears later in the
program must be define by the programmer after the program is assembled.
Two-Pass Assembler: This assembler scans the assembly language program twice. In the first pass, the
first memory location is determined from the ORG statement and the location counter initialized. The
assembler also generates a symbol table. A symbol table consists of labels with addresses assigned to
them. This way labels can be used for SJMP statement addresses assigned to them and no address
calculation has to be done by the user. On the second pass, the assembler translates the mnemonics and
labels into machine code. Thus, the two-pass assembler is more desirable and easy to use. For example,
a source program is given below:
DATA EQU 55H
; Data
ORG 2000H
; Start assembling the program from location 2000H
MOV A, #DATA
; A=01010101B
infiniteloop: CPL A
; Complement A, A=10101010B
MOV P1, A
; Port 1=A
SJMP infiniteloop
; Continuously send complemented contents of A on Port 1.
END
Table 5.1: Steps to generate Hex code for two pass assembler
Pass 1
ROM Address (HEX)
2000
2002
2003
2005
Pass 2
2000
2002
2003
2005
2007
Assembled List File:
1
2
3
2000
4
2002
5
2003
6
2005
7
2007
Label Opcode
Operand
Symbol Table
MOV A
infiniteloop : CPL
MOV P1
SJMP
DATA
A
PORT 1
infiniteloop
DATA 55H
A
PORT 1
infiniteloop 2002H
74 55
F4
F5 90
80FB
74 55
F4
F5 90
80 FB
Cross Assembler: This type of assembler is typically resident on the microcontroller and assemble
programs for other for which it is written. The cross assembler program is written in a high level language
so that it can run on different types of microcontroller that understand the same high-level language.
Resident Assembler: This type of assembler assembles programs for a microcontroller in which it is
resident. The resident assembler may slow down operation of the microcontroller on which it runs.
5.3 ASSEMBLING AND RUNNING AN 8051 PROGRAM
Here we are going to discuss that how an assembly language program is created, assembled and simulate
or run?
42
The assembler program performs the task of translating symbolic code into object code which can be
executed by the 8051 microcontroller. Assembler output consists of three possible files: the object file
containing our program translated into object code; the list file can be accessed by an editor such as DOS
EDIT and displayed on monitor or take printout of our source code, the assembler generated object code,
and the symbol table; and the symbol-cross-reference file, a listing of the symbol-cross reference records.
To use the assembler, we first need a source/editor
program. The source program consists of programmerwritten assembly language instructions. These instructions
are written using mnemonic op-codes and labels as described
previously. We choose a text editor to write a source program
which is able to produce an ASCII file, such as MS-DOS EDIT,
and Notepad in windows.
We can then pass the resulting source program (.src or .asm)
file to the assembler. The assembler program converts the
instructions into machine code. The assembler will produce an
object file (.obj) and a list file (.lst).
An assembler may allow us to request object code in a
relocatable format. This makes free the programmer from
worrying
about
the
eventual
mix
of
read
only
and random access memory in the application system;
individual portions of the program can be relocated as needed
when the application design is final. Also, a large program can
be broken into a number of separately assembled modules,
such modules are both easier to code and to test.
Figure 5.1: Steps for generating a Hex file
The program list file provides a permanent record of source program and the object code, the assembler
also provides diagnostic messages for common programming syntax errors in the program listing. For
example, if we specify a 16-bit value for an instruction that can use only an 8-bit value, the assembler
tells us that the value exceeds the permissible range. After fixing all the errors indicated in the list file the
object (.obj) file is ready to be input to the linker program.
The linker program takes one or more object files and produces an absolute object file (.abs file).
The .abs file is fed into the OH (object to Hex converter) program which create a .hex file. The .hex
file is ready to burn into program memory.
5.4 PROGRAMMING MODEL FOR THE 8051
In the 8051 CPU, the internal registers are used to store data temporarily during program execution.
Since, the 8051 is 8-bit microcontroller that shows there is only 8-bits data type. Although, any data
larger than 8-bits must be divided into 8-bit pieces then it is processed. The 8051programming model
(shown in figure 5.2 and 5.3) includes a register bank at a time out of four which includes eight 8-bit
registers, one accumulator A (is a default register which is used for all arithmetic and logical operation),
register B, PSW and a stack pointer (SP). In addition, it has two 16-bit registers: the data pointer (DPTR)
and the program counter (PC).
A (8-bit)
B
R0
R1
R2
R3
R4
R5
R6
R7
SP
PSW
DPTR (16-bit)
DPH (8-bit)
DPL (8-bit)
PC (16-bit)
128
bytes
of RAM
(00-7F)
SFRs
(80-FF)
4K bytes
Of ROM
(0000H0FFFH)
43
The basic architecture is the same for all members of the 8051 family although there are differences for
devices, which may have more, or less, ports, interrupts, timers, comparators, ADC circuits, etc. Specific
features include:
8-bit CPU with registers A (accumulator) and B
16-bit program counter (PC)
16-bit data pointer register (DPTR)
8-bit program status word register (PSW)
8-bit stack pointer (SP).
It is clear from the above that the 8051 has a collection of 8-bit and 16-bit registers and 8-bit memory
locations. The internal memory of the 8051 can be shown by the programming model of Figure 5.3.
Figure 5.4: Memory organization for the 8051 microcontroller (a) Code memory (b) Data memory
44
The 8051 family devices have two data memories, internal and external. The internal data address space
has two different parts, as shown in figure 5.5. One part contains the general-purpose registers and
Note: The 128 bytes of internal RAM addresses are shown to the left, bit-addressable locations are shown inside registers.
Figure 5.5: The internal RAM organization for the 8051 microcontroller
general-purpose data storage RAM, and the other part contains all the special registers and I/O devices,
such as the parallel and serial ports, and timers. These registers are called special function registers.
There is a maximum of 256 bytes of internal RAM (128 bytes for the 8031/8051, 256 bytes for the
8032/8052) and special function registers (SFR). Four
register banks (each bank has eight registers), 128
individually addressable memory bits, and the stack all
reside in the internal data RAM. The stack depth is
limited only by the available internal data RAM. The 8-bit
stack pointer deter- mines the stacks location. The
internal data RAM provides a convenient 128 byte
scratch pad memory which includes the register banks,
bit addressable area and general purpose data storage.
For the 8051 microcontroller, the internal RAM of 128
bytes is broken down (shown in figure 5.6) into:
1. Four register banks 0 to 3, each of which
contains eight registers R0 to R7. The 32
bytes occupy addresses from 00H to 1FH.
Each register can be addressed specifically
when its bank is selected or an address can
identify a particular register regardless of the
bank, i.e. R2 of bank 2 can be specified if
bank 2 is selected or the same location can be
Figure 5.6: 128 bytes of internal RAM
specified as address 12H. The register banks not selected can be used as general-purpose RAM.
Bits 3 and 4 of the PSW register determine which bank is selected when a program is running.
Reset will cause bank 0 to be selected.
45
Sixteen bytes that are bit addressable in the address range 20H to 2FH giving 128 addressable
bits. The bits have individual addresses ranging from 00H to 07H for byte address 20H, to 78H
to 7FH for byte address 2FH.Thus a bit may be addressed directly, say bit 78H, which is bit 7 of
byte address 2F.
3. A general-purpose/ memory range from 30H to 7FH, which are bytes addressable.
2.
46
47
The above figure shows an 8-bit register format, called the flag register. However, it is not used as a
general purpose register; the six bit positions out of eight are used by the 8051. The flags are stored (by
microcontroller itself) in the 8-bit flag register, so that the programmer can examine and use these flags
(reflect data conditions of Accumulator/Result) by accessing the register through an instruction. These
flags have critical importance in the decision-making process of the microcontroller. The conditions (set or
reset) of the flags are tested through the software instructions. For example, the instruction JC (Jump on
Carry) is implemented to change the execution sequence of a program when CY flag is set.
The thorough understanding of flags is essential in writing assembly language programs. Four of the flags
in the 8051 are called conditional flags, which are indicate the status of the result in the accumulator
(arithmetic and logical condition) or other registers after execution of each instructions in ALU. Since, the
ALU includes four flip-flops, which are set (Logic 1) or reset (Logic 0) after an operation according to data
conditions of the result in the accumulator or other registers. They are called Carry (CY), Auxiliary Carry
(AC), Overflow (OV) and Parity (P) flags. The most commonly used flags are Zero, Carry, and Auxiliary
carry.
CY (Carry flag): This flag is set (high) whenever there is a carry out from the MSB in addition, or borrow
in case of subtractions. This flag bit is affected after addition, subtraction and other operations such as
shift, rotate etc. For example, after an addition of two numbers, if the sum in the accumulator is larger
than eight bits i.e. a carry out from the MSB, then a flip-flop used to indicate a carry, called the Carry flag
(CY) and CY will be set to 1 (high).
For example, add two numbers (AEH and 74H) and check the flag status.
Solution:
7654 3210 (bit position)
AEH=1010 1110
+74H=0111 0100
22H=0010 0010
An addition that causes a carry out of the high order bit sets the carry flag to 1(high), or an addition
that not causes a carry reset the flag to 0(low).
This flag bit can be modifying by an instruction such as SETB C or SETB PSW.7 (set bit carry will make
CY=1) and CLR C or CLR PSW.7(Clear carry flag will make CY=0).
AC (Auxiliary Carry flag): This flag bit is set (1) if an operation generates a carry from lower nibble to
upper nibble i.e. from D3 to D4; otherwise reset (0). This flag is only used by instruction DA A that perform
BCD (binary code decimal) arithmetic. This flag bit not available for programmer or decision making
operations because it used internally by only DA A instruction. The auxiliary carry flag and the DA A
instruction allow us to treat the value in the accumulator as two 4-bit binary coded decimal numbers.
Thus, the value 0001 1001BCD is equivalent to 19D (If this value is interpreted as a binary number, it has
the value 25D.).
48
Example 5.1: Write the instruction to store AAH into register R0 and R7 of the register bank 2.
Solution: The register bank 0 is the default register bank when the 8051 is powered up (power on reset).
In other word, the RS1 and RS0 bits of the PSW are cleared upon reset. In order to select register bank 2,
the RS1 must be set to 1 and no change in RS0.
SETB PSW.4
; Set RS1 to select register bank 2
MOV R0, #0AAH
; Save AAH into Ro of register bank 2
MOV R7, #0AAH
; Load R7 of register bank 2 with AAH
Example 5.2: Is it correct if we use direct addressing MOV 7, 0 for the 3 rd instruction in the
example5.1?
Solution: no, it is wrong because direct addressing deal with the RAM address not to the register name.
MOV 7, 0 will load the contents from the 00H RAM location into the 07H RAM location.
We can use MOV 17H, 10H in place of MOV 7, 0.
MOV R0, #AAH would give a syntax error. In common with a number of cross assemblers the software
would see AAH as a label because it starts with a hex symbol; 99H would be acceptable since it starts with
a number. The correct program line should be MOV R0, #0AAH i.e. a zero must be placed in front of the
hex symbol.
P (Parity flag): The 8051 has odd parity means this flag bit is set if number of 1s in the Accumulator is
odd, after an arithmetic or logical operation; otherwise reset. This flag is not reflecting the magnitude of
49
accumulator whether magnitude is even or odd. For example, the data byte 0000 10002 has odd parity
(P=1) even if the magnitude of the number is even.
OV (Overflow flag): This flag bit is set (high), if there is a carry out of either the D7 bit or the D6 bit of
the accumulator; otherwise reset (low). This flag is used in signed arithmetic operations and it is same as
the MSB of the result in the accumulator.
Example 5.3: What are the contents of the RAM locations after execution of the following
program?
SETB PSW.3
SETB PSW.4
; Select register bank 3
MOV R0, #20H
; Same as MOV 18H, #20H, save 20H into R0
MOV R4, #10H
; Same as MOV 1CH, #10H, Save 10H into R4
Solution: As mention above, PSW.3=0 and PSW.4=0 upon reset; therefore, instructions SETB PSW.3 and SETB PSW.4
set register bank 3 which is use RAM space from 18H to1FH. After execution of the above program the contents of the
RAM locations:
The content of RAM location 18H is 20H.
The content of RAM location 1FH is 10H.
Alternate program for the given program:
MOV 18H, #20H
MOV 1CH, #10H
F0 (General-purpose flag): This is a bit-addressable bit and user programmable. In other word, user
can use this bit to store a bit. For example:
SETB PSW.5
; F0=1
MOV PSW.5, C
; Save Carry flag into F0 bit
Example 5.4: Show the status of the Flags in PSW after the addition of 45H and 1DH in
accumulator.
Solution:
MOV A, #45H
; A=45H
ADD A, #1DH
; A= 011000102=62H
CY=0, AC=0, P=1 (odd number of 1s) and OV=0.
Example 5.5: Show that how the status of the CY, AC and P flag bits changes after addition of
8FH and 91H in the following instructions:
MOV A, #8FH
; A=8FH
MOV R0, #91H
; R0=91H
ADD A, R0
; after addition A=20H, CY =1, AC=1 and P=1.
Solution:
8F
1000 1111
+ 91
+1001 0001
120
0010 0000=20H
CY=1 since there is a carry out from the D7 bit of Accumulator
AC=1 since there a carry from theD3 to the D4 bit
P=1 since an odd number of 1s in the Accumulator
Accumulator (A): This 8-bit register, usually referred to as register A, is default register for data
operations such as addition, subtraction, etc. and for Boolean bit manipulation. This register is also used
for data transfers between the microcontroller and external memory/ports, where applicable. The
accumulator is both bit and byte addressable with the byte address at E0H and the bit addresses from E0H
to E7H.
50
B Register: This 8-bit register is used for multiplication and division operations. For other instructions it
can be considered another scratch pad register. The B register is both bit and byte addressable with byte
address at F0H and bit addresses from F0H to F7H.
Stack Pointer (SP): This 8-bit register at address 81H is incremented before data is stored during PUSH
and CALL and decremented after data is retrieved during POP and RET executions. The SP is initialized to
RAM address 07H after a reset, which causes the stack to begin at location 08H.
Data Pointer (DPTR): This 16-bit register is intended to contain the two bytes that make a 16-bit
address, with the high byte (DPH) at address 83H and the low byte (DPL) at address 82H. It may also be
used as two independent 8-bit registers. The DPTR is used for addressing locations in the external data
memory. Since the DPTR is a 16-bit quantity, a total of 64 kilobytes of data may be addressed.
Ports 0 to 3: The P0, P1, P2 and P3 are the SFR latches of Ports 0, 1, 2 and 3, respectively.
Serial Data Buffer (SBU): The Serial Data Buffer is actually two separate registers, a transmit buffer
and a receive buffer register. When data is moved to SBUF, it goes to the transmit buffer where it is held
for serial transmission (Moving a byte to SBUF is what initiates the transmission). When data is moved
from SBUF, it comes from the receive buffer.
Timer Registers: Register pairs (TH0, TL0), (TH1, TL1), and (TH2, TL2) are the 16-bit counting registers
for Timer/Counters 0, 1, and 2, respectively.
Control Registers: Special Function Registers IP, IE, TMOD, TCON, T2CON, SCON, and PCON contain
control and status bits for the interrupt system, the timer/counters, and the serial port.
For each of the interrupts the eight bytes may be sufficient to accommodate the interrupt servicing routine
but if not the programmer should provide a jump to the service routine. Whether or not an interrupt is
enabled depends on the bit settings of the IE register. If no interrupts are used the programmer could
establish the program from location 0000H; but with interrupts the programmer should enter a jump
instruction from location 0000H to the starting address of the main program.
What do the SFRs contain just after Power-on-reset or a Reset? Table 5.3 lists the contents of each SFR
after a power-on reset or a hardware reset.
51
*: Bit addressable
+: 8052, 8352 only
X: Undefined
Every CPU has an ALU and a number of registers (see figure 5.10) to store information temporarily during
execution. The information could be the values to be processed, or the address of the value needed to be
fetched or instruction from memory. Registers inside the CPU can be 8-bit, 16-bit etc. depending on the
size of processor.
The ALU circuitry of the microcontroller is responsible for performing arithmetic functions such as addition,
subtraction, and logical functions such as AND, OR etc. The ALU circuitry contains various circuits such as
MUX, Shift Register, Adder, Counter, Decoder etc.
Program Counter (PC): The function of the PC is to point the next instruction address to be executed.
As just after execution of each instruction, the PC is increment by one, to the address of the next
instruction to be executed.
52
Instruction Decoder: The function of this unit is to interpret the instruction fetched into the
microcontroller from program memory. The instruction decoder is a something sort of dictionary,
containing the meaning of each instruction in form of circuit, tells to the microcontroller, what steps
should be taken upon receiving a given instructions op-code.
5.7 INTERNAL WORKING OF THE MICROCONTROLLER
Assume that a microcontroller have some registers called A, and R0. It has an 8-bit data bus, a 16-bit
address bus for accessing data/instruction from memory and a 16-bit program counter to point a program
memory location.
We want to perform a task that adds two hexadecimal numbers 12 H and 14H. This task can be performed
by the microcontroller is to put hexadecimal value 12H into register A and then 14H is added to register A.
This task can be divided into two steps, in the first step put 12H into register A then action of the second
step add 14H to it.
The operation code for the 8051 microcontroller to move a immediate value into register A is 74H ,op-code
for add a immediate value to register A is 24H and the op-code to move A into R0 is F9H.
We have to burn the program into program memory in the form of op-codes and data (instruction). As
shown below:
Memory address Instruction
Op-code
Description
ORG 00H
0000H
MOV A, #12H
74H
; (74H) op-code for moving data into register A
0001H
12H
; (12H) data to be moved into A
0002H
ADD A, #14H
24H
; (24H) OP-code for add an immediate to register A
0003H
14H
; (14H) immediate data to be add with register A
0004H
MOV R0, A
F9H
; (F9H) Op-code to copy A into R0
0005H
END
; Stop further execution
The sequence of actions performed by a microcontroller to run or execute the above program as follows:
1. The PC can contain a value from 0000H to FFFFH. The content of PC is 0000H after reset the
microcontroller. The PC must be set to 0000H and it indicates the first instruction or OP-code to be
executed from this memory location. When the PC loaded with the first instruction address, the CPU is
ready to execute first instruction.
2. The 8051s CPU puts 0000H on the address bus and sends it out. The memory circuitry finds that
memory location while the microcontroller unit activates the MEMORY READ signal to get the contents
from location 0000H. Therefore the contents of memory location 0000H which is 74H, to be put on the
data bus and brought into the CPU and this operation known as OP-code fetching.
3. The 8051s CPU decodes the instruction 74H with the help of internal instruction decoder unit and finds
the meaning of the instruction that is the data stored in the next memory location 0001H must bring
into register A of the CPU. Therefore, it commands to its control and timing circuitry to do that. When
it brings value 12H from memory location 0001H, control and timing circuitry closed the doors of all
register except register A. Therefore when value 12H comes into the CPU from program memory and it
will go directly into register A and this operation known as memory read. After execution of the
instruction, PC points to the address of the next instruction to be executed i.e. 0002H. Address 0002H
puts on the address bus and send it out to the memory, to fetch the next instruction.
4. From memory location 0002H, it fetches the OP-code 24H. After decoding this OP-code, the CPU
knows that the data at the next address 0003H must add to the contents of register A. After data bus
brings the value 14H into the CPU, it provides the contents of register A with 14H to the ALU to
perform addition. After perform addition, it takes the result from the output of ALU and put result in
register A. After executing this instruction, PC points to the next instruction address.
5. Similarly, address 0004H puts on the address bus and op-code fetches into the CPU and executed. The
END pseudo- instruction tells to the microcontroller to stop incrementing the PC or stop further
execution.
5.8 THE 8051 MICROCONTROLLER INSTRUCTION SET SUMMARY
The following description of the instruction set is not a complete list, but serves to introduce the general
character of the standard 8051 instructions. The instruction set utilized by the 8051 microcontroller
consists of a total of 111 instructions, which may be divided up into several different categories. These
are:
1. Data transfer (28)
53
2. Logical (25)
3. Arithmetic (24)
4. Bit (Boolean) variable manipulation (17)
5. Program branching and control (17)
Each of these categories is comprised of instructions that utilize mnemonics as shown below:
Data Transfer
MOV, MOVX, MOVC, PUSH, POP, XCH, XCHD
Arithmetic
ADD, ADDC, SUBB, INC, DEC, MUL, DIV, DA
Logical
ANL, ORL, XRL, CLR, CPL, RL, RLC, RR, RRC, SWAP
Bit (Boolean) Variable Manipulation
CLR, SETB, CPL, ANL, ORL, MOV, JC, JNC, JB, JNB, JBC
Program Branching and Control
ACALL, LCALL, RET, RETI, AJMP, LJMP, SJMP, JMP, JZ, JNZ, CJNE, DJNZ, NOP.
We will discuss all instructions in detail in the forthcoming chapters.
Some important aspects of the instruction set are noted below:
In data transfer, the contents of the source are not destroyed; only the contents of the destination
are changed. The data copy instructions do not affect the flags.
Arithmetic and Logical operations are performed with the contents of the accumulator, and the
results are stored in the accumulator (with some expectations). The flags are affected according to
the results.
Any register including the memory can be used for increment and decrement operation.
A program sequence can be changed either conditionally or unconditionally, for a given data
condition.
REVIEW QUESTIONS
1. What do you mean by assembling and running of the program?
2. What is the difference between compiler and assembler?
3. What is the function of assembler directives and data types?
4. What is need of a programming model?
5. Explain the internal working of a microcontroller to run a program.
6. What are the main components of the CPU?
7. What is the purpose of the instruction decoder and program counter.
8. How can we relate address bus and program counter?
9. Explain the requirement of a program counter, stack pointer and status flags in the CPU?
10. What is PSW?
11. What are the different flags in the 8051?
12. What is flag register?
13. What is the function of accumulator?
14. Explain the memory structure of 8051.
15. Explain the internal RAM structure of the 8051.
16. Explain the Bit-addressable space of the 8051.
17. Explain the SFR space for the 8051.
18. How can we switch to a register bank?
19. What is need of bit addressing?
20. Where are the registers R0-R7 located in the 8051 microcontroller?
21. What are the SFRs associated with the 8051 ports and timers?
22. Explain the internal program memory with interrupt locations.
23. How many interrupt are available in the 8051?
54
CHAPTER-6
DATA TRANSFER INSTRUCTIONS, I/O PORT PROGRAMMING
The data transfer instructions copies the data from source operand to destination operand. Dont be confused
with the terms transfer, the data transfer instructions do not alter or destroyed the contents of the source
operand. They just copy the content of the source operand and paste into the destination operands. These
instructions just copy the data from the source operands and paste the data into the destination operands.
The data moving instructions for 8051 are given in table 6.1:
Table 6.1: Data transfer instructions
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
Mnemonics
Function
Machine Cycle/Byte
MOV A, Rn
; Move Register (any one of R0-R7) to Accumulator
1/1
MOV A, direct
; Move direct RAM data to Accumulator
1/2
MOV A, @Ri
; Move indirect RAM data to Accumulator
1/1
MOV A, #data8
; Move immediate data to Accumulator
1/2
MOV Rn, A
; Move Accumulator to register (any one of R0-R7)
1/1
MOV Rn, direct
; Move direct RAM byte to register
2/2
MOV Rn, #data8
; Move immediate data to register
1/2
MOV direct, A
; Move Accumulator to direct RAM location
1/2
MOV direct, Rn
; Move register (any one of R0-R7) to direct byte
2/2
MOV direct, direct
; Move direct RAM byte to direct RAM location
2/3
MOV direct, @Ri
; Move indirect RAM to direct RAM byte
2/2
MOV direct, #data8
; Move immediate data to direct RAM byte
2/3
MOV @Ri, A
; Move Accumulator to indirect RAM
1/1
MOV @Ri, direct
; Move direct by to indirect RAM
2/2
MOV @Ri, #data8
; Move immediate data to indirect RAM
1/2
MOV DPTR, #data16
; Load Data Pointer with a 16bit constant
2/3
MOVCA @A+DPTR
; Move Code byte relative to DPTR to Accumulator
2/1
MOVCA @A+PC
; Move Code byte relative to PC to Accumulator
2/1
MOVXA, @Ri
; Move External RAM (8-bit addr) to Accumulator
2/1
MOVXA, @DPTR
; Move External RAM (16-bit addr) to Accumulator
2/1
MOVX @Ri, A
; Move Accumulator to External RAM (8-bit addr)
2/1
MOVX@DPTR, A
; Move Accumulator to External RAM (16-bit addr)
2/1
PUSH direct
; Push direct byte only stack
2/2
POP direct
; Pop direct byte from Stack
2/2
XCH A, Rn
; Exchange register with Accumulator
1/1
XCH A, direct
; Exchange direct RAM byte with Accumulator
1/2
XCH A, @Ri
; Exchange indirect RAM byte with Accumulator
1/1
XCHD A, @Ri
; Exchange lower order nibbles indirect RAM with Accumulator
1/1
Note: A machine cycle =12 oscillator period or clock. None of the flag affected.
Rn=any one of R0-R7 register of the currently selected register bank.
Direct: 8-bit internal direct address for data. The data could be in lower 128bytes of RAM (00 7FH) or it could be in the special function
register (80 FFH).
@Ri: 8bit external or internal RAM address available in register R0 or R1. This is used for indirect addressing mode.
#data8: Immediate 8-bit data available in the instruction.
#data16: Immediate 16-bit data available in the instruction.
55
MOVX) 128 bytes of data RAM can be accessed only by indirect addressing and SFR space (80-FFH space
access by MOV) only by direct addressing. Some of these instructions are given below:
Mnemonic
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
Operand/s
Destination, Source
A, Rn
Rn, A
direct, direct
direct, A
direct, Rn
A, direct
Rn, direct
Rn, #data
direct, #data
@Ri, # data
; Comment/description (optional)
; Copy from source operand and paste into destination operand.
; Copy from source register and paste into destination register.
; Copy from A to register
; Move direct byte to direct byte within RAM
; Move A to direct byte
; Move register to RAM location direct
; Move direct byte into A
; Move direct byte into register
; Move immediate value into register
; Move immediate data into RAM location direct
; Move immediate value into RAM location indirect
Example 6.1: Write an assembly program to exchange the contents of register R0 and R4. Assume the contents of
R0=10H and R4=90H.
Solution:
(a)
Flow Chart
Start
Stop
Program
comments (optional)
ORG 0000H
MOV A, R0
MOV 0, 4
MOV R4, A
; R4=10H
END
; Stop execution
(b)
ORG 00H
MOV A, R0
MOV 1H, A
XCH A, R4
MOV R0, A
END
; A=10H
; RAM location (01H)=10H
; A= 90H and R4=10H
; R0=90H
56
Upon power-on reset the stack pointer contains a value of 07H. This means the RAM location 08 is the first
location and last location is the 1FH being used for the stack by the 8051. In the other word, register bank
1,2 and 3 are using same memory space as stack space. We can reallocate another RAM space to stack.
For example, we can allocate RAM locations 30H and higher to the stack as shown below:
MOV SP, # 2FH
; Make RAM location of 30H to first stack location (SP=2FH)
MOV 02H, #22H
; same as MOV R2, #22H
MOV R4, #11H
; Same as MOV 04H, #11H
PUSH 2
; SP=30H, RAM location (30H) contents =22H
PUSH 4
; SP =31H, (31H) =11H
POP 1
; SP=30H, (01H) =R1 =11H
POP 3
; SP=2FH, (03H) =R3 =22H
After power
on reset
After
MOV SP, #2FH
After
PUSH 2
0D
0C
0B
0A
09
08
34
33
32
31
30
34
33
32
31
30
SP=07H
SP=2FH
SP=30H
22H
After
PUSH 4
34
33
32
31
30
11H
22H
SP=31H
After
POP 1
34
33
32
31
30
22H
SP=30H
After
POP 3
34
33
32
31
30
SP=2FH
External RAM
Only indirect addressing can be used to access external memory. The choice is whether to use a one-byte
address, @Ri, where Ri can be either R0 or R1 of the selected register bank, or a two byte address, @DPTR.
The disadvantage to using 16-bit addresses if only a few Kbytes of external RAM are involved is that 16-bit
addresses use all 16 bits of the Port 0 and Port 2 as address bus. On the other hand, 8-bit addresses allow
only port 0 to address a few Kbytes of RAM. Note that in all external Data RAM accesses, the Accumulator is
always either the destination or source of the data. The read and write signals (from Port 3) to external RAM
are activated only during the execution of a MOVX instruction. Separately these signals are inactive, and in
fact if theyre not going to be used at all, Port 3 pins are available as extra I/O lines. Data Transfer
instructions that access external Data Memory space are given below:
MOVX A, @Ri
; Read external RAM location pointed by Ri (@ Ri)
MOVX @ Ri, A
; Write external RAM @ Ri (8-bit address)
MOVX A, @ DPTR
; Read external RAM @ DPTR (16-bit address)
MOVX @ DPTR, A
; Write external RAM @ DPTR
The Data Transfer instructions include a 16-bit MOV that can be used to initialize the Data Pointer (DPTR) for
look-up tables in Program Memory, or for 16-bit external Data Memory accesses. For example,
MOV DPTR, # 0300H
; Set the data pointer at the starting address of the LUT or External RAM location
MOVX @DPTR, A
; Move the contents of Accumulator into External RAM location 0300H
MOVX A, @DPTR
; Move the contents of the External RAM (0300H) into the Accumulator
The XCH A, byte instruction causes the Accumulator and addressed byte to exchange data. The source byte
can be any register or RAM location but destination must be A. For example,
XCH A, Rn
; Exchange data bytes between A and register
XCH A, direct
; Exchange data bytes between A and direct RAM location
XCH A, @Rn
; Exchange data bytes between A and indirect RAM location
The XCHD A, @Ri instruction (exchange digits) is similar, but only the lower nibbles are involved in the
exchange.
Example 6.2: W.A.P. to save the contents from external data memory location 7F00H into register R0 and the
contents of 7FFFH into register R2, after then store contents of R3 into 2500H memory location and R5 into 7F00H.
Solution:
Algorithm
1. Copy the contents of memory location 7F00H into register A.
2. Save the contents of A into R0
3. Copy the contents of memory location 7FFFH into A.
57
4.
5.
6.
7.
8.
Flow chart
Program
Description (optional)
ORG 0000H
; DPTR= 7FFFH
; A= Contents of external RAM (7FFFH)
; R2=A= (7FFFH)
; DPTR=2500H
; R3= A
; Contents of 2500H i.e.(2500H)=A=R3
MOV A, R5
MOV DPTR, # 7F00H
MOV @DPTR, A
; A=R5
; DPTR=7F00H
; Save accumulator in memory location 2500H
Start
Stop
END
MOVC A, @A + PC
RET
The table itself immediately follows the RET (return) instruction in Program Memory. This type of table can
have up to 255 entries, numbered 1 through 255. Number 0 cannot be used, because at the time the MOVC
instruction is executed, the PC contains the address of the RET instruction. An entry numbered 0 would be
the RET op-code itself.
58
Example 6.3: Write an assembly program for carry out following tasks sequentially:
a. Load Accumulator with 20H.
b. Copies A into R0-R4 registers of register bank 0.
Solution:
Flow chart
Program
Description (optional)
Start
Stop
ORG 0000
; PC=0000H
MOV A, #20H
; A=20H.
MOV R0, A
MOV R1, A
MOV R2, A
MOV R3, A
MOV R4, A
; R0=A=20H
; R1=20H
; R2=20H
END
Example 6.4: Write an assembly program for carry out following tasks sequentially:
a. Load Accumulator with 7FH.
b. Load R0 with 33H
c. Exchange the data with A and R0
d. Exchange the lower nibble with A and R0
Solution:
Flow chart
Program
Description (optional)
Start
ORG 3000H
MOV A, #7FH
; A=7FH
; R0=33H
XCH A, R0
Stop
6.2
END
The 8051 has four parallel I/O ports- Port-0, Port-1, Port-2 and Port-3. To reduce the number of pins, the
pins allotted for parallel ports are assigned some alternative functions as well. Out of the four ports, port-1 is
used exclusively for input and output functions i.e. no alternate function assigned for port-1. The Port-0,
Port-2 and Port-3 perform functions other than input and output. These alternate functions are decided by
the hardware of port and the instruction being executed. Each port of 8051 has bidirectional capability. They
can be programmed to perform input and output operation. The user can program each port using their
59
address mapped in the SFR (special function register) space. Each bit of the ports SFRs corresponds to one of
the port pins on the microcontroller. For example, bit address 80H of port 0 is pin P0.0, bit address A4H is
pin P2.4.Table 6.2 shows a list for the SFR byte address of the parallel ports and the addresses of the
individual pins.
Table 6.2: Port addressability and single pin addressability
Parallel
Port No.
SFR
address
Px.5
Px.6 Px.7
Port-0
Port-1
Port-2
Port-3
80H
90H
A0H
B0H
80H
90H
A0H
B0H
85H
95H
A5H
B5H
86H
96H
A6H
B6H
81H
91H
A1H
B1H
82H
92H
A2H
B2H
83H
93H
A3H
B3H
84H
94H
A4H
B4H
87H
97H
A7H
B7H
Figure 6.1: Internal Structure of (a) Port-0 (b) Port-1 (c) Port-2 (d) Port-3
The 8-pins of port-0 have open-drain outputs (open drain in CMOS device and open-collector in TTL device).
Each I/O line can be independently used as an input or an output. The Port-0 can be configured as output
upon reset with external pull-up resistors as shown in figure 6.2. To be used as an input, the port-0 bit latch
must contain a 1, which turns off the output driver MOSFET. While, for Ports 1, 2, and 3, the pin is pulled
60
high by the internal pull-up resistor (PMOS), but can be pulled low by an external source. Port 0 differs from
other ports as not having internal pull-up resistor (PMOS).
The pull- up MOSFET in the Port-0 output driver (see Figure 6.1 (a)) is used only when it is emitting 1
during external memory accesses. Otherwise the pull-up MOSFET is off. Consequently Port-0 lines that are
being used as output port lines are open drain. Writing a 1 to the bit latch makes both output MOSFETs off,
so the pin floats. In that condition, it can be used as a high-impedance input. Because Ports 1, 2, and 3 have
fixed internal pull-up resistor (PMOS) they are sometimes called quasi-bidirectional ports. When configured
as inputs they pull high and will source current when externally pulled low.
On the other hand, Port 0 is considered true bidirectional port, because when configured as an input it
floats.
All the port latches in the 8051 are configured as output by the reset function. If a 0 is subsequently written
to a port latch, it can be reconfigured as an input by writing a 1 to it. Ports 0 and 2 may not be used as
general purpose I/O when being used as the ADDR/DATA BUS to access external memory.
As shown in Figure 6.1 (a) and (c), the output drivers of Ports 0 and 2 are switchable (using MUX) to an
internal ADDR and ADDR/DATA bus by an internal CONTROL signal for use in external memory accesses.
Port-0 provide lower address byte and data bus
From the figure 6.1(d), the alternate functions of Port-3 can be activated only if the data 1 is written in the
port-3 bits. So that if a Port-3 bit latch contains a 1, then the output level is controlled by the signal labeled
alternate output function. The actual P3.X pin level is always available to the pins alternate input function.
Note that the internal pull-ups are field-effect transistors, not linear resistors.
I/O PROGRAMMING OF THE PORTS
Port-0 can be configured as a normal bidirectional I/O port or it can be used for address/data interfacing for
accessing external memory. When Control =1, the port is used for address/data interfacing. When the
Control =0, the port can be used as a normal bidirectional I/O port.
For example, assume that Control =0. When the port is used as an input port, 1' must be written to the
latch. In this situation both the output MOSFETs are off'. Hence the output pin floats. This high impedance
pin can be pulled up or pulled down by an external source. When the port is used as an output port, a 0'
must be written to the latch, the
pin is pulled down by the lower
NMOS. Hence the output
becomes zero. But when 1'
written to the latch by the
internal bus during send data on
it, again both the output
MOSFETs turn off' and causes
the output pin to float. An
external pull-up resistor is
required to pull-up output to 1'.
When the control =1,
address/data bus controls the
output driver MOSFETs. If the
address/data bus (internal) =0,
the upper MOS is off' and the
lower MOS is on' in turn output
becomes 0'.
Figure 6.2: A pin of port-0 with external pull up resistor when use as O/P
If the address/data bus =1, the upper MOS is on' and the lower MOS is off'. Hence the output is 1.
For the Port-1, 2 and 3, when used as output port, the pin is high or low through internal pull-up (PMOS) and
pull down (NMOS). To use any port as input port, 1' has to be written to the latch. In this input mode when
1' is written to the ports pin by the external device then it read without any trouble. But when 0' is written
to the pin by the external device then the external source must sink current due to internal pull-up. If the
external device is not able to sink the current the pin voltage may raise due to PMOS has limited current
driving capability and it is leading to a possible wrong reading. To use ports as output, 0 has to be written to
the latch. A 0 will turn on the lower MOS, grounding the pin.
61
Note that the Port 1, 2, and 3 each can drive up to three LS family TTL inputs (fan out or load). These port
pins can be driven by open-collector and open-drain outputs, but low to high transition will not be fast.
While, Port-0 can drive up to eight LS-TTL inputs in address /data mode to access external memory and to
use port 0 as output it needs external pull-up resistors.
Example 6.5: Write instructions to perform following tasks:
1. Make port-0 as input port
2. Read the data from the port-0
3. Send it to the port 2
Solution:
MOV P0, #0FFH
; Configured port-0 as input port by writing 1s to the latches
MOV A, P0
; Read port-0
MOV P1, A
; Send it to the output port-1
END
Example 6.6: Write instructions to read the port-0 and send to the Port-1 continuously.
Solution:
MOV P0, #0FFH
; Configured port-0 as input port by writing 1s to the latches
DREAD: MOV A, P0
; Read port-0
MOV P1, A
; Send it to the output port-1
SJMP DREAD
; Go back to read and send continuously
Example 6.7: W.A.A.P. to read port-2. Save its content into R4 and display at port-0.
Solution:
Flow chart
Program
Start
ORG 0000H
MOV A, #0FFH
MOV P2, A
MOV A, P2
MOV R4, A
MOV P0, A
Stop
; Description (optional)
; Save it into R4
; Send it to port-0
END
Read-Modify-Write Feature
Such instructions that read a port, some of them read the latch and others read the pin. There is a difference
between read the latch and read the pin is given below:
Reading a latch: Usually the instructions that read the latch, read a value, possibly modified (by arithmetic
or logical operation) it, and then rewrite it to the latch. These are called read-modify-write instructions.
Examples of a few instructions are:
ANL P2, A
; Read P2 latch, logical AND with P2 and A (modified) and finally result write into P2
62
DJNZ (Decrement and jump if not zero, e.g., DJNZ P3, address)
MOV PX.Y, C (Move the C bit into Port bit e.g. MOV P1.3, C)
CLR PX.Y (Clear port bit e.g. CLR P0.7)
SETB PX.Y (Set the port bit e.g. SETB P1.3)
Reading a port Pins: Some instructions are reading of the port pins values. For example,
MOV A, P2
; Move port-2 pin values to A
MOV A, P0
; Read Port-0
The read-modify-write feature save many lines of code as three
operations; read-modify and write performed by a single instruction.
Other advantage of read-modify-write instruction is that, it is
possible a misinterpretation of the voltage level at the pin reading
but reading a latch is give a correct result then reading a pin. For
example, a port bit P1.2 might be used to drive the base of a
transistor.
When a 1 (5V) is written to the bit P1.2, the transistor is turned on
(figure 6.3). If the CPU then reads the same port bit at the pin
rather than the latch, it will read the base VBE voltage (0.6V) of the
transistor and interpret it as a 0 (0V-1.4V treated as 0). Reading the
latch rather than the pin will return the correct value of 1 (5V).
Figure 6.3: P1.2 to derive BJT
given below:
; Set bit-0 of port-1, i.e. P1.0=1, configure P1.0 as input bit.
; Save P1.0 into bit location 07H of RAM
; Save bit into RAM bit location 07H
; Clear bit-0 of port-1, i.e. P1.0=0, Configure as output bit
; Send Carry bit value to the P1.0
; Complement bit-0 of port-1, i.e. P1.0=1
From the above example, we can see that each of port bit can be configured as I/O bit, manipulation, and
store. This feature is very useful for the user when we access only 1 or 2 bits of the port instead of entire
port pins.
Example 6.8: Write a program for figure 6.4 to perform the following task:
1. Read the status of a switch which is connected to the P2.1 bit.
2. Whenever switch is pressed, it is indicated by turn on a LED
connected to the P2.2 bit.
Solution: Upon reset all ports are configured as output port.
SETB P2.1
; Configure P2.1 as input bit
CHECK: JNB P2.1, CHECK
; Monitoring for switch is pressed or not
; if switch is pressed, get out from the loop
SETB C
; C=1
MOV P2.2, C
; Send a high to P2.2 to turn on the LED
ACALL DELAY
; Wait
SJMP CHECK
; back to check the status of switch
VDD
63
MOVC A, @A+DPTR
MOV P1, A
INC DPTR
DJNZ R3, L1
SJMP AGAIN
ORG 0300H
SINETABLE DB 128, 192, 238, 255, 238, 192, 128, 64, 17, 0, 17, 64, 128
END
Note: to get a better wave regenerate the values of the table per 2 degree.
REVIEW QUESTIONS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
64
CHAPTER-7
ADDRESSING MODES
The instruction format is given below for copy operation:
MOV destination, source
For example, MOV R0, A or MOV A, #82H is to copy data from a source into a destination. In these instructions the
source can be an 8051s register, an input port, memory location or an 8-bit constant number (00H to FFH). Similarly, a
destination can be an 8051s register, memory location or an output port. The sources and destination are operands. The
various formats for specifying operands or these various ways of accessing data are called the ADDRESSING
MODES. For the 8051, they are:
1. Immediate/constant addressing
2. Register addressing
3. Direct addressing
4. Register indirect addressing
5. Indexed addressing
6. Implied addressing mode
1. IMMEDIATE/CONSTANT ADDRESSING
The constant /immediate data is available in the instruction itself. When the instruction is assembled or written, the
operand comes immediately after the OP- code. In other words, the value of a constant can follow the op-code in
Program Memory. Notice that the immediate data must follow the pound sign (#). For example,
MOV A, # 100
Above instruction loads the Accumulator with the decimal number 100. The same number could be specified in hex
digits as 64H.
Some more examples given below:
MOV R0, #33H
MOV B, #01011111B
MOV P2, #10H
ADD A, #56H
MOV SP, # 30H
The 16-bit DPTR can be accessed as two 8-bit register, DPH (higher byte) and DPL (lower byte). For example,
The assembler directives (data types) are used immediate addressing mode to access data as describe below:
TEN: EQU 10
X: DB 05H
ORG 1000H
MOV A, #X
ADD A, #TEN
END
cross assemblers the software would consider FAH as a label because it starts with a hex symbol.
65
MOV P1, A
MOV B, R0
The register bank, containing registers R0 through R7 can be accessed by certain instructions which carry a 3-bit register
specification address within the op-code of the instruction. Instructions that access the registers this way are code
efficient, since this mode eliminates an immediate/address byte. When the instruction is executed, one of the eight
registers in the selected bank is accessed. One of four banks is selected at execution time by the two bank select bits in
the PSW.
Some common syntax errors
MOV R2, R4
MOV A, DPTR
; Invalid, data transfer between register banks registers by their name is not allowed.
; Invalid, the source and destination registers size must match.
1.
2.
3.
4.
In direct addressing, the memory address that contains the data to be operand is specified by an 8-bit address field in the
instruction. The entire internal data RAM and SFRs space can be directly accessed using direct addressing mode. Notice
that # sign is absent here.
Direct addressing mode for R0 R7 and 30H-7FH
Ram locations 00H-1FH are assigned to the register banks and 08H -1FH to the stack. The register R0 R7 can be
accessed by either using their names (Rn) or their addresses. For examples, some statements are given below:
MOV R1, 50H
MOV A, 0
MOV 30H, A
MOV 2, 4
; Move the immediate data F3H into RAM location 40H: (40H) = F3H
; A = (40H) = F3H
; (35H) = A = F3H
; (56H) = (35H) = F3H
; Invalid, Immediate value cannot be a destination.
For example,
PUSH A
PUSH 0E0H
PUSH 5
PUSH 6
PUSH 0E0H
POP 0F0H
POP 2
POP 15
66
Address (Hex)
A
B
P0
P1
P2
P3
E0
F0
80
90
A0
B0
If an address is used by the above bit instructions, then it is a bit address. On the other hand, Address used by all other
instructions is byte address. For example,
CLR 86H
; Clear bit P0.6
SETB E5H
; Set bit ACC.5
67
Example 7.2: Save the status of bit P1.7 to bit address 05H.
Solution:
SETB P1.7
; Configure P1.7 bit as input
MOV C, P1.7
; Read P1.7 bit and save into bit C
MOV 05, C
; Save Carry bit into bit-address 05H (bit 5 of byte address 20H)
If the data is stored in the external RAM location and address of external RAM (128 bytes external RAM) location is 8-bit
ranging from 80-FFH. Recall that the same address range also allotted to the SFRs. These ranges of address are identified
by the external access instruction. For example;
MOVX A, @R0
MOVX @R1, A
The data pointer (DPTR) is used to store a 16-bit address for indirect addressing or accessing of external 64KB RAM. For
example,
MOVX A, @DPTR
MOVX @DPTR, A
; Move the contents of external RAM location which is held by DPTR into A.
; Move the contents of A into external RAM location which is pointed by DPTR
The XCHD instruction exchanges only the lower nibble of A with the lower nibble of the internal RAM location pointed
to by either R0 or R1 while upper nibbles in both remain unchanged. For example,
MOV 30H, #13H
; Save 13H into RAM location 30H
MOV A, # 78H
; Load A with 78H
MOV R0, #30H
; Set R0 as pointer to point RAM location 30H
XCHD A, @R0
; Exchange the lower nibbles A and data held by RAM location 30H
After execution of the XCHD instruction, A=73H and RAM location 30H has (30H)=18H.
Example 7.3: Find the content in RAM locations and registers after each step?
Solution:
MOV 32H, #10H
MOV R0, 32H
MOV R1, #45H
MOV @R1, R0
MOV A, R1
MOV A, @R1
MOV @R0, A
; (32H) =10H
; R0 =10H
; R1 =45H
; (45H) = R0=10H
; A =45H
; A = 10H
; (R0) = 10H
68
Example 7.4: Write a program to copy a block of 5 bytes of data from RAM locations starting at 30H into
RAM locations starting at 65H.
Solution:
COUNT EQU 5
MOV R0, #30H
MOV R1, #65H
MOV R3, #COUNT
BACK: MOV A, @R0
MOV @R1, A
INC R0
INC R1
DJNZ R3, BACK
ORG 300H
DBBHARAT,0
END
; Label MYDATA=300H, Define bytes from 300H for six ASCII character
; Notice that a null character is present at the end of string!
; End of program
MOVC A, @A+DPTR
MOV 61H, A
INC DPTR
MOVC A, @A+DPTR
MOV 62H, A
INC DPTR
CLR A
MOVC A, @A+DPTR
MOV 63H, A
INC DPTR
CLR A
MOVC A, @A+DPTR
MOV 64H, A
INC DPTR
CLR A
MOVC A, @A+DPTR
MOV 65H, A
AGAIN: SJMP AGAIN
; Stay here
All of us have seen a multiplication table in school. Our math teacher is taught us how to memorize the whole thing; it was
easy up to 10 but difficulties arise when we go greater than 10. Its easy to remember 2 x 2 = 4, but try 196 x 314 or
457432 x 938483. What if we had a table that would let we find the answer instead of calculating it ourselves? In many
ways, this is a look-up table, because if we want to find the answer to something, we just have to look it up.
Before the advent of computers, lookup tables of values were used by people to speed up hand calculations of complex
functions, such as in trigonometry, and logarithms. In ancient India, Aryabhata created one of the first sine tables, which
he encoded in a Sanskrit-letter-based number system.
In computer science, a lookup table is a set of data or an array that replaces runtime computation with a simpler indexing
operation. The savings in terms of processing time can be significant, since retrieving a value from memory is often faster
than undergoing an 'expensive and long' computation or input/output operation with co-processor. In data analysis
applications, such as image processing, a lookup table (LUT) is used to transform the input data into a more desirable
output format. For example, a grayscale picture of the planet Saturn will be transformed into a color image to emphasize
the differences in its rings.
A classic example of reducing run-time computations using lookup tables is to obtain the result of a trigonometry
calculation, such as the sine of a value. Calculating trigonometric functions can substantially slow a computing application.
Example 7.6: Write a program to get x from P1, calculate x3 using look-up table and send it to the P2,
continuously. Assume x in the range of 0 to 6.
Solution: It is computationally expensive in terms of time to calculate in real time.
Look-Up-Table (LUT)
ORG 0000H
MOV DPTR, #TABLE
MOV P1, #0FFH
BACK: MOV A, P1
MOVC A, @A+DPTR
MOV P2, A
SJMP BACK
ORG 200H
TABLE: DB 0, 1, 8, 27, 64, 125, 216.
END
ROM
location
200H
201H
202H
203H
204H
205H
206H
0
1
2
3
4
5
6
x3
(Decimal)
0
1
8
27
64
125
216
Assume that P1 get a value of 4 and so A=4H. The instruction MOVC A, @A+DPTR (A+DPTR=4H+0200H=204H) find the
3
value of x in the look-up table and get the data from ROM location 204H into A. In the statement A+DPTR, A contains the
offset address and DPTR has base address (first address of the LUT) of the look-up table, constitutes the physical
3
address of the data record that corresponds to the actual value of x .
71
analyzing, designing, documenting or managing a process or program in various fields. Every flowchart symbols
have a unique purpose, are used in making of flowcharts are shown in following figures:
Oval Indicates the beginning or stop of a task (program/subroutine execution start
or stop)
Parallelogram Indicates inputs or outputs
Arrow Indicates the direction of data/process flow (flow of program execution)
Diamond Indicates decision making and branching (decision based flow of program
execution)
Circle with an arrow Joining of two parts of program or continuation of flow chart to
other page (off-page connector).
4. Implement algorithm in assembly program: The small and simple steps describe in algorithm/flowchart are
translate in sequence into instructions (assembly program).
5. Translate assembly language to machine language: If the 8051 based single board microcomputer (8051
trainer kit ) have assembler then no need of performing this step, feed assembly program in microcomputer and
execute the program, otherwise, find the Hexadecimal machine code for each instruction of our assembly
program in the 8051 instruction set. Write each machine code in same sequence as instruction. Check out
specification of trainer kit/ single board microcomputer, suppose microcomputer has program memory, starting at
the address 0000H, feed machine codes sequentially in the consecutive memory location from 0000H to onwards
and execute the program. To execute the program, we need to specify the starting and ending address location to
the microcontroller and push the execution key to start program execution.
REVIEW QUESTION
1. List the addressing modes of 8051?
2. What do you mean by addressing mode?
3. What type of addressing mode is used to move data from the external (RAM and ROM) memory to the
accumulator?
4. Which register bank shares the same space with the stack?
5. What type of addressing is used to access stack?
2
6. Write a program to find y where y=x - 3, and range of x is from 0 to 9.
7. Write a program to clear RAM locations 30H to 35H.
8. Write a program to exchange the content of R6 with R7.
9. Find out which byte for each of the bits in the following instruction belongs?
SETB 42H
CLR 0FH
CPL 12H
72
CHAPTER-8
BRANCHING INSTRUCTIONS, LOOPS AND PROGRAMS
This group of instructions used to transfer program control or program execution to a different location either conditionally or
unconditionally. The program control instructions for the 8051 family given in table 8.1:
Table 8.1: Program branching instructions
Mnemonics
Function
1.
2.
3.
4.
5.
6.
7.
8.
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
9.
JC
Flags
2/2
2/3
2/1
2/1
2/2
2/3
2/2
2/1
none
none
none
none
none
none
none
none
2/2
none
10. JNC
Jump (PC + Rel) if C bit=0
2/2
11. JZ rel
Jump (PC+Rel) if Accumulator =0
2/2
12. JNZ rel
Jump (PC+Rel) if Accumulator is Not Zero
2/2
13. JB bit, rel
Jump (PC+Rel) if bit=1
2/3
14. JNB bit, rel
Jump (PC + Rel) if bit=1
2/3
15. JBC bit, rel
Jump (PC+Rel) if bit=0
2/3
16. CJNE A, direct, rel
Compare direct byte to Acc and Jump if Not Equal
2/ 3
17. CJNE A, #data8, rel
Compare immediate to Acc and Jump if Not Equal
2/3
18. CJNE Rn, #data8, rel
Compare immediate to register and Jump if Not Equal
2/3
19. CJNE @Ri, #data8, rel
Compare immediate to indirect and Jump if Not Equal
2/3
20. DJNZ Rn, rel
Decrement register and Jump if Not Zero
2/2
21. DJNZ direct, rel
Decrement direct byte and Jump if Not Zero
2/3
22. NOP
No Operation
1/1
Note: - #data8: Immediate 8-bit data available in the instruction.
addr11: 11-bit target address for short absolute jump.
addr16: 16-bit target address for long call or long jump.
rel: Relative address to the PC used for short jump (SJMP) and all conditional jumps.
bit: Bit address (Directly addressable bit of internal RAM or SFR)
direct: 8-bit internal RAM direct address for data (Directly addressable byte of internal RAM or SFR)
none
none
none
none
none
none
CY
CY
CY
CY
none
none
none
; Program counter (PC) load with the address of 3456H (program execution start from memory location 3456H)
73
+126
Downward jump (down to 127 bytes of memory)
+127
Hex
(80)
(81)
(FE)
(FF)
(00)
(01)
(02)
(7E)
(7F)
The advantages of the relative jump are only 1 byte of jump address is needed, i.e. for jumping forward, the
range is 0 to 127 and for jumping backward, the range is -1 to -128. Specifying only one byte address
instead of two byte address, save the program memory space since the 8051 has only 4K byte on-chip ROM
and speeds up program execution.
Example 8.1: Calculate the target address of the short jump instruction in the following list file.
S.No.
1
2
3
4
5
6
7
PC
Op-code
2000
2002
2003
2005
2007
74 55
F4
F5 90
80 FB
Mnemonic
DATA EQU 55H
ORG 2000H
MOV
UPWARD: CPL
MOV
SJMP UPWARD
END
Operand
A, #DATA
A
P1, A
Solution: Notice that the SJMP is upward jump in the above program list. In line 6, the instruction SJMP UPWARD has opcode 80H and relative address is FBH=(2s complement value of -5). Add the relative address (-5) to the current PC contents
(2007H) to get target address (2002H).
Example 8.2: Calculate the target addresses of the short jump instruction in the following list file
S.No. PC
Op-code
Mnemonic
Operand
1
ORG 2000H
2
2000
74 22
MOV
A, #22H
3
2002
24 FF
ADD
A, # FFH
4
2004
40 01
JC
DOWNWARD
5
2006
F9
MOV
R1, A
6
2007
F8
DOWNWARD: MOV
R0, A
7
2008
END
Solution: Notice that the JC is downward jump in the above program list. In line 6, the instruction JC DOWNWARD has opcode 40H and relative address is 01H. Add the relative address (01H) to the current PC contents (2006H) to get target
address (2007H).
74
Example 8.3: W.A.P. to create a square wave to all bits of port 1 continuously or infinitely.
Solution:
Start
ORG 0000H
Load A
MOV A, #00H
; A=00H
Complement A
Send A to port 1
CPL A
; Complement A
MOV P1, A
SJMP BACK
In this program, the microcontroller is executing an infinite loop. To terminate this loop, apply RESET or interrupt to the microcontroller.
A7
A6
A5
A4
A3
A2
Lower eight address bits
Second Byte
A1
A0
AJMP transfers program execution to the target address, which is formed during execution by concatenating
the high-order five bits of the PC (after incrementing the PC twice), bits 7 through 5 of first byte (upper
address bits), and the second byte of the instruction. The target address must therefore be within the same 2
K byte block of program memory as the first byte of the instruction following AJMP. In the simple words, 64 K
byte of program memory space is divided into 32 blocks of 2 K byte. Each the upper 5 bits of the program
counter (PC+2) hold the page number and the lower 11bits of the PC hold the address within that page. For
example, assume the AJMP command is at code memory location 650H, it can only do a jump to addresses
0000H through 07FFH (0 through 2047, decimal).Thus, an absolute address is formed by taking page
numbers of the instruction (From PC) following AJMP and attaching the specified 11bits to it to form the 16bit address as shown in table.
PC=0347H
0
Addr11=0113H
After AJMP
0
PC=0113H
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
75
ORG 0000H
A=(40H)
MOV A, 40H
JZ L1
Is
A=0?
YES
No
P1=00H
SJMP OUT
Jump out
OUT: .
76
J1:
J2:
J3:
ORG 0H
MOV R0, #40H
MOV A,#00H
MOV R4, A
ADD A, @R0
JNC J1
INC R4
INC R0
ADD A,@R0
JNC J2
INC R4
INC R0
ADD A,@R0
JNC J3
INC R4
MOV R5, A
END
; R2=8H
; Toggle pin 7 of port 2
; Repeat until R2=0 (8 times)
Above instructions toggles P2.7 eight times, causing four output pulses to appear at bit 7 of output Port 2. Each pulse
lasts three machine cycles; two for DJNZ and one to complement the pin value.
77
Example 8.9: Find the sum of the data bytes which are stored in five RAM locations from 40H to 44H. Save the upper
byte of the sum into R4 and lower byte into R5.
Solution:
ORG 0H
MOV R0, #40H
; R0=40H
MOV R4, #00H
; R4=00H
MOV R3, #05H
; R2=05H
BACK: ADD A,@R0
; Add A with RAM contents
INC R0
; Increment R0
JNC L1
; Jump to label L1, if not carry
INC R4
; Increment R4 by one
L1: DJNZ R3, BACK
; Repeat until R3=0 (5 times)
MOV R5, A
END
Example 8.10: W.A.P. to multiply 07H with the 05H without using MUL instruction.
Solution:
ORG 0000H
MOV A, #00H
; Clear A
MOV R2, #05H
; Load count in B i.e. B=05H
loop: ADD A, #07H
; 7,14,21,28,35
DJNZ R2, loop
; 4, 3, 2, 1, 0
these instructions form a finite loop, which is add 07H to A for 5 times.
END
Flow Chart
Start
A=00H
R2=05H
A=A+07H
R2=R2-1
No
Is
R2=0?
Finite loop
Yes
Stop
What we do, if we want to repeat a loop more than 256 times? We can use a technique as explain below.
Nested Loop (loop within a loop)
As in example 8.8, the DJNZ can repeat a sequence of instructions (loop) a maximum of 256 times. But what
we do if count value greater than 256? To do that, we use a nested loop or a loop inside a loop. In nested
loop two or more counter register we can use to hold the count value.
78
R3=F0H
A= A
No
R3=R3-1,
Is R3=0?
Yes
R2=R2-1,
Is R2=0?
No
Yes
Stop
79
It is a 3-byte instruction. CJNE compares the magnitudes of the first two operands
Table 8.2: CJNE and Carry flag status
Compare
Carry Flag
and if their values are not equal, program control transfer to the target address.
The carry flag is set if the unsigned integer value of first operand byte (destination
Destination > Source
CY=0
byte) is less than the unsigned integer value of second operand byte (source
Destination < Source
CY=1
byte) ; otherwise, the carry is cleared (see table). The comparison of two
operands is performed by subtracting the content of the source operand from the content of the destination operand, without
change in operands value. This jump replaces the PC (program counter) content with a new target address, which is
computed by adding the relative value (within -128 to +127) in the third byte to the PC+3 (or next instruction address), recall
that the CJNE is a 3-byte instruction.
The first two operands allow four addressing mode combinations: the Accumulator may be compared with any directly
addressed byte or immediate data, and any indirect RAM location or working register can be compared with an immediate
constant. It has following formats.
CJNE destination byte, source byte, relative address
CJNE A, direct, relative address
CJNE A, #data, relative address
CJNE Rn, #data, relative address
CJNE @Ri, #data, relative address
Example 8.13: Write a program to determine that R0 contains the value 20H. If it has, make R1=00H if not R1=FFH.
Solution:
CJNE R0, #20H, N1
MOV R1, #00H
SJMP N2
N1: MOV R1, #0FFH
N2: END
Alternate program
MOV R1, #0FFH
CJNE R0, #20H, N1
MOV R1, #00H
N1: END
Example 8.14: The port-2 is configured as an input port which is connected to an air pressure sensor to check tyre pressure.
Three pins of Port-1 is an output, one pin is connected to a buzzer, second pin to a Red LED and third to a Green LED. Write a
program to read the air pressure of a tyre and perform the following tasks:
If air pressure of the tyre = 45, send a high signal to buzzer,
If air pressure of the tyre < 45, turn on green LED, and
If air pressure of the tyre > 45, turn on red LED.
Solution: The required hardware for given specification shown in figure and software program given below.
ORG 0H
8051
MOV P2, #0FFH
Air Pressure
MOV A, P2
; Read Port-2
Sensor and
PORT-2
ADC
CJNE A, #45, N1
; Compare A with 45?
P1.0
SETB P1.2
; If A=45, turn on buzzer
SJMP N3
; Exit
P1.1
N1: JNC N2
; Check carry?
CLR P1.1
; If CY=1 i.e. A< 45, turn on green LED
P1.2
SJMP N3
; Exit
N2: CLR P1.0
; If CY=0 i.e. A>45, turn on red LED
N3: END
Figure 8.1: H/w for example 8.14
Example 8.15: Assume internal RAM location 40H-49H contains daily transaction of an ATM for ten days. Search to
see if any of the values is 68.
Solution: To indicate any stored value in RAM locations is equal to 68, if 68 exist in RAM we save its location into R3
otherwise save 00.
ORG 0H
MOV R1, #40H
; Initialize RAM pointer
MOV R2, #10
; Set counter=10
80
MOV A, R1
MOV R3, A
SJMP FOUND
NF: INC R1
DJNZ R2, CHECK
MOV R3, #00H
FOUND: END
(b) Alternate program
ORG 0H
MOV R1, #40H
MOV R2, #10
MOV A, #68
CHECK: CJNE A, @R1, NF
MOV 3, 1
SJMP FOUND
NF: INC R1
DJNZ R2, CHECK
MOV R3, #00H
FOUND: END
Example 8.16: W.A.P. to find the largest number in a block of data. The length of the block is in memory location 40H
and the block itself starts from memory location 41H. Store the maximum number in memory location 50H. Assume
that the numbers in the block are all 8 bit unsigned binary numbers.
Sample problem
(40H) = 04
(41H) = 34H, (42H) = A9H, (43H) = 78H, (44H) =56H.
Result = (42H) = A9H
Solution:
Start
Yes
Is A>M?
Check
CY flag
No
No
R2=R2-1
Is R2=0?
Yes
Stop
81
Source program
MOV A, 40H
MOV R2, A
MOV A, #00H
MOV R0, #41H
BACK: CJNE A, @R0, L1
L1: JNC SKIP
MOV A, @R0
SKIP: INC R0
DJNZ R2, BACK
MOV 50H, A
END
LCALL
This is a 3-byte instruction; the first byte is the op-code for CALL and remaining two byte are used to hold 16-bit address of
the target subroutine location (0000H to FFFFH). The target location may therefore be anywhere in the full 64K program
memory address space. Its format given below:
LCALL 16-bit address
Long Call is transferred the program control to the target location (followed by LCALL) by loading the high-order and loworder bytes of the PC (respectively) with the second and third bytes of the instruction. When the 8051 executes a LCALL
instruction, it adds three to the program counter to generate the address of the next instruction and then pushes the PC
contents onto the stack (low order byte first), incrementing the Stack Pointer by two. The high-order and low-order bytes of
the PC are then loaded, respectively, with the second and third bytes of the LCALL instruction. Program execution continues
with the instruction at this target address.
Example 8.17: After Reset, the Stack Pointer points at 07H. After executing the instruction,
DELAY EQU 0100H
; The label DELAY is assigned to program memory location 0100H.
000AH LCALL DELAY
; The Stack Pointer will contain 09H, internal RAM locations 08H and 09H will contain 0DH
and 00H, and the PC will contains 0100H.
000DH NOP
After
CALL 0100H
0D
0C
0B
0A
09
00
08
0D
SP=09H, PC=0100H
After
RET
0D
0C
0B
0A
09
08
SP=07H, PC=000DH
A subroutine which is called by a CALL instruction must have at least a RET instruction, Why?
82
Example 8.19: W.A.P. to generate a square wave of 66% duty cycle on the port-1 continuously.
Solution:
Program execution flow
ORG 0000H
MOV A, #0FFH
Main program
BACK: CPL A
Delay program (subroutine)
MOV P1, A
CALL delay program
LCALL DELAY ; Call delay subroutine
back to the main program
CPL A
MOV P1, A
CALL delay program
LCALL DELAY ; Call delay subroutine back to the main program
LCALL DELAY ; Call delay subroutine
CALL delay program
RET (back to main program)
SJMP BACK
back to the main program
8051
DELAY
O/P
PORT-1
A=~A
Send A to Port-1
Initialize R2=00H
Call DELAY
Complement A and
Send A to the port-1
NO
R2=R2-1
Is R2 =0?
2/3
1/3
Call DELAY
YES
Call DELAY
RET
83
Whenever RET instruction is executed in a subroutine program, the memory address stored in the stack is retrieved
or popped automatically (as using POP instruction) onto program counter and main program execution begin from
where it was suspended.
0
0
Op-code
A7
A6
First Byte
A5
A4
A3
A2
Lower eight address bits
Second Byte
A1
A0
The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto
the stack (low-order byte first) and increments the stack pointer twice. AJMP is similar to ACALL (but not use stack) transfers
program execution to the target address, which is formed during execution by concatenating the high-order five bits of the PC
(after incrementing the PC twice), op-code bits 7 through 5, and the second byte of the instruction. The target address must
therefore be within the same 2 K byte block of program memory as the first byte of the instruction following ACALL. In the
simple words, 64 K byte of program memory space is divided into 32 blocks of 2 K byte. Each the upper 5 bits of the program
counter (PC+2) hold the page number and the lower 11bits of the PC hold the address within that page. The subroutine
called must therefore start within the same 2K block of program memory as the first byte of the instruction following ACALL.
The advantage of ACALL over LCALL is that it is used only 2 byte of program memory. Therefore, ACALL saves memory
space. For instance, after reset SP holds 07H. The labelSUBRTN is at program memory location 0354H.
After executing the instruction
ACALL SUBRTN
at location 0103H, SP will contain 09H, internal RAM location 08H and 09H will contain 05H and 01H, respectively, and the
PC will contain 0354H.
Machine cycle-1
1T
2T
3T
..
machine cycle-2
Machine cycle-4
12T
Time Delay
Time delay is very important in microcontroller applications. Typically, in sequential process control, the microcontroller is
required to provide time delay for on-off devices such as pumps or motor-operated machine or valves, traffic signal,
microwave oven, to synchronize with slow responding peripherals etc. The delay subroutines are used to provide such time
delays. The time delay subroutine program is written by programmer in program memory, to provide specific time delay for
application.
84
Example 8.20: An 8051 microcontroller has a clock frequency of 11.0592 MHz. What is the time for each clock cycle
and machine cycle?
Solution:
Clock period (T) =
-6
(=10 )
Example 8.21: Calculate the period of machine cycle if crystal frequency is (a) 20MHz (b) 8MHz.
Solution:
-6
(a) 12/ (20 10 ) =0.6 s
-6
(b) 12/ (8 10 ) =1.5 s
If the 8051 has a clock frequency of 11.0592MHz, we can calculate the time required for an instruction as given below:
Instruction
Numbers of Machine cycles/ clock cycles
Time to execute
ACALL
2/24
2 1.085 s=2.17 s
MOV R2, #04H
1/12
1 1.085 s=1.085 s
MOV A, R2
1/12
1 1.085 s=1.085 s
SJMP
2/24
2 1.085 s=2.17 s
NOP
1/12
1 1.085 s=1.085 s
DJNZ
2/24
2 1.085 s=2.17 s
RET
2/24
2 1.085 s=2.17 s
MUL AB
4/48
4 1.085 s=4.34 s
Time Delay Calculation Methods
The NOP instruction can be used for smallest time delay but apart from this there are two methods of creating time delays:
Register decrement (Software method)
Onboard timers (Hardware method, see chapter 12)
Register decrement method:
A typically program for delay subroutine is given below (assume crystal frequency is 11.0592 MHz):
DELAY: MOV R2, #number
; for simplicity we may use decimal number instead of Hex number
L1: DJNZ R2, L1
; Decrement R2, if it is not zero jumps to L1.
RET
MOV takes 1 machine cycle, DJNZ and RET each take 2 machine cycles. The delay is called up from the main program
using ACALL, which takes 2 machine cycles.
The total delay time is (2+1+ (number 2) +2) machine cycles or in terms of clock cycles,
the total delay time is (24+12+ (number 24) + 24).
Delay time = (5+ (number 2)) machine cycles 1.085 s.
Delay time= (60+ (number 24)) clock cycles 90.423 ns.
We can use Clock cycles for time delay calculation, but it increases calculation complexity.
Example 8.22: Find the delay time for the following program, if the crystal frequency is 11.0592 MHz.
ORG 0
PULSE: SETB P1.7
ACALL DELAY
CLR P1.7
ACALL DELAY
AJMP PULSE
Time delay subroutine
DELAY: MOV R0, #100
L1: DJNZ R0, L1
RET
Solution:
DELAY: MOV R0, #100
L1: DJNZ R0, L1
RET
The delay is called up from the main program using ACALL, which takes 2 machine cycles. MOV takes 1 machine cycle,
DJNZ and RET each take 2 machine cycles. Therefore, we have time delay of [2 + 1+ (100 2) + 2] 1.085 s = 222.425 s.
85
From the above delay subroutine, the largest delay we can by loading 00 into R2. If we load R2 with 00, then DJNZ will
execute 256 times. For instance,
Machine cycles/ Clock cycles
DELAY: MOV R2, #00
1/12
L1: DJNZ R2, L1
2/24
RET
2/24
Therefore, this subroutine generates a time delay of [1 + (256 2) + 2] machine cycles 1.085 s = 558.775 s.
To increase the delay we can use NOP instruction one or more times in the loop. Another way to increase delay time is to
use a nested loop. For example,
Machine cycles/ Clock cycles
Times of execution
DELAY: MOV R2, #00
1/12
1
L1: NOP
1/12
256
DJNZ R2, L1
2/24
256
RET
2/24
1
This subroutine generates a delay time of [1 + (2561) + (256 2) + 2 ] machine cycles 1.085 s = 836.535 s.
Example 8.23: Find the time delay for the following subroutine for 11.0592 MHz of crystal frequency.
DELAY: MOV R2, # 100
L2: MOV R3, #50
L1: NOP
NOP
NOP
DJNZ R3, L1
DJNZ R2, L2
RET
Machine Cycles
1
1
1
1
1
2
2
2
Times of execution
1
100
50 100
50 100
50 100
50 100
100
1
Solution:
The total machine cycles are 25303 [1 + (1 100) + (3 50 100) + (2 50 100) + (2 100) + 2].
-3
The total delay time is calculated as 25303 1.085 s =27.454 ms.
(m=10 )
TRIPLE LOOP DELAY
DELAY: MOV R2, #number1
OUTER: MOV R1, #number2
INNER1: MOV R0, #number3
INNER: DJNZ R0, INNER
DJNZ R1, INNER1
DJNZ R2, OUTER
RET
Approximately the time delay = (number 1) (number 2) (number 3) 21.085 s. Suppose number-1=30, number-2= 200,
and number-3=250, then time delay = (30 200250) 2 1.085 =3.255s, this is long enough to see a LED going on and off.
Example 8.24: An 8051 microcontroller has an 11.0592MHz crystal-controlled clock oscillator. Write an assembly
language program that will generate a 5 kHz square wave signal on pin 7 of port 1 when a switch causes pin 0 on the
same port to go to logic 1.
Solution:
Clock frequency = 11.0592MHz
Thus period of clock cycle = (1/11.0592MHz) = 90.423 ns
Signal frequency = 5 kHz
Therefore period of signal cycle = (1/5 kHz) = 200 s
The delay required is half of this value since the square wave has an equal
logic 1/logic 0 time.
Delay =100 s= (5+ (number 2)) machine cycles 1.085 s
Hence number= [(100 s/1.085 s) 5]/2 44 decimal (to the nearest whole
number).
ORG 0
SJMP START
ORG 0040H
START: JB P1.0, PULSE
CLR P1.7
SJMP START
86
Example 8.25: An 8051 microcontroller clocked at 12 MHz, is connected to a loudspeaker. Write a program to
generate a sound at a frequency of 500Hz.
Solution:
Figure 8.3 shows the hardware interface where the loudspeaker is connected to Port 1 at pin P1.0. A simple transistor is used as an
amplifier as the 8051 output port does not have enough current drive capability to drive the loudspeaker directly.
Figure 8.3 also shows a simple timing diagram to explain how the 500Hz generate. Square wave is generated by the program. The 1 ms
subroutine is used to provide the basic time delay for each half cycle.
ORG 0000H
LOOP: SETB P1.0
LCALL DELAY
CLR P1.0
LCALL DELAY
SJMP LOOP
DELAY: MOV R2, #250
L1: NOP
NOP
DJNZ R7, L1
RET
REVIEW QUESTIONS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
87
CHAPTER-9
ARITHMETIC INSTRUCTIONS AND PROGRAMS
These instructions for the 8051 performs arithmetic operations such as addition, subtraction, BCD addition, increment by one,
decrement by one etc, all arithmetic operation are performed in accumulator A and the result is also stored in A that means,
in arithmetic operation instruction must have accumulator as default destination operand except increment and decrement
instructions. These instructions are as given in table 9.1.
Table 9.1: Arithmetic instructions
Mnemonics
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
ADD A, Rn
ADD A, direct
ADD A, @Ri
ADD A, #data 8
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data8
SUBB A, Rn
SUBB A, direct
SUBB A, @Ri
SUBB A, #data8
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
Function
Add register to A
Add direct byte to A
Add indirect RAM to A
Add immediate data to A
Add register to A with Carry
Add direct byte to A with Carry
Add indirect RAM to A with Carry
Add immediate data to A with Carry
Subtract Register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A with borrow
Subtract immediate data from A with borrow
Increment Accumulator
Increment register
Increment direct byte
Increment indirect RAM
Decrement Accumulator
Decrement Register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A and B
Divide A by B
Decimal Adjust Accumulator
Machine Cycle/Byte
Flags affected
1/1
1/2
1/1
1/2
1/1
1/2
1/1
1/2
1/1
1/2
1/1
1/2
1/1
1/1
1/2
1/1
1/1
1/1
1/2
1/1
2/1
4/1
4/1
1/1
ADDITION
The formats for addition instructions are given below:
Mnemonic
Operands
; Description (optional)
ADD
ADDC
ADD
ADDC
ADD
ADDC
ADD
ADDC
A, #data8
A, #data8
A, Rn
A, Rn
A, @Ri
A, @Ri
A, direct
A, direct
88
MOV A, # 78H
MOV R0, #30H
ADD A, @R0
ADD A, 40H
ADDC A, @R0
ADDC A, 40H
Accumulator A is an SFR and its RAM address is 00E0H. A large number of instructions use accumulator A, but not all.
ADD instruction adds the source byte to the Accumulator, leaving the result in the Accumulator. The carry and auxiliary-carry
flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned number,
the carry flag indicates an overflow occurred. OV is set there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7
but not bit 6 ; otherwise OV is cleared. When adding signed numbers, OV indicates a negative number produced as the sum
of two positive operands, or a positive sum from two negative operands. Four source operand addressing modes are
allowed: register, direct, register-indirect, or immediate. For example,
The Accumulator holds 0C4H (11000100B) and register 0 holds 0A9H (10101001B). The instruction,
ADD A, R0
will give 6DH (01101101B) in the Accumulator with the AC flag cleared and both the carry flag and OV set to 1.
Example 9.1: Write an assembly program to add two 8- bit numbers and store result in register R5. Assume two
numbers are 37H and 47H.
Solution:
Start
Stop
ORG 0000H
MOV A, #47H
; A=47H
ADD A, #37H
; A= 47H + 37H=7EH
MOV R5, A
END
Example 9.2: W.A.P. to add two 8-bit numbers 37H and 47H which are stored in 50H and 51H respectively. Store the
result in register R4 and then in 52H memory location.
Solution:
Start
ORG 000H
; PC=0000H
MOV A, 50H
ADD A, 51H
MOV R4, A
MOV 52H, A
; R5= A
;
; Save A into RAM location (52H)
Stop
END
89
Example 9.3: W.A.P. to add two 16-bit numbers and store higher byte of result in reg. R3 and lower byte in reg. R4.
Assume two numbers are 1284H and 2385H.
Solution:
Algorithm
1. Add the lower bytes of the given numbers , i.e. 84H+85H=09H and carry flag CY=1.
2. Store the accumulator in register R4 , i.e. store the lower byte result in R4=09H
3. Add the higher bytes of the given numbers with carry , i.e. 12H+23H+1=36H
4. Store the accumulator in register R3 , i.e. store the higher byte of result in R3=36H
Start
ORG 0000H
MOV A, #84H
ADD A, #85H
MOV R4, A
MOV A, #12H
ADDC A, #23H
; A=12H
; A=12H+23H+1(CY) =36H and CY=0.
MOV R3, A
; R3= 36H
Stop
END
SUBTRACTION
In processor, there is no additional circuit for subtraction. Here, adder circuit is used for subtraction. Therefore subtraction is
performed by using 2's compliment addition technique, and the result if negative, is expressed in 2's complement.
For example, to perform 10H-05H (minuend (10H) subtrahend (05H) = difference (0BH))
10H in binary
00010000
2s complement of - 5H
11111011
CY=1 00001011 = 0BH.
After addition, Complement the carry (in this case CY=0). Now check carry/borrow, If carry/borrow flag=0, result is positive
and if Carry/borrow=1, result is negative.
The syntax for SUBB instructions given below:
SUBB A, Rn
; Subtract Register from A with borrow
SUBB A, direct
; Subtract direct byte from A with borrow
SUBB A, @Ri
; Subtract indirect RAM from A with borrow
SUBB A, #data8
; Subtract a constant value from A with borrow
See the following sequence of instructions:
MOV A, #10H
; A=10H and CY/Borrow=0
SUBB A, #05H
; A= A-5H-CY (0) = 0BH and borrow/carry flag CY=0.
MOV A, #30H
MOV R5, #40H
SUBB A, R5
; A=30H
; R5=40H
; A=A-R5-CY= 10H and carry/borrow =1 (it indicates that the result is negative)
90
30H in binary
= 00110000
2s complement of 40H
= 11000000
CY=0 11110000 =F0H
After addition, complement the carry (in this case CY=1). Now check borrow/carry; if CY=1 then result is negative and takes
the 2s complement of the result in accumulator. The 2s complement of F0H is 10H, will be in the Accumulator.
we continue the above program as the borrow/carry flag is set in the execution of last instruction.
MOV A, #40H
; A=40H
MOV R0, #25H
; R0=25H
SUBB A, R0
; A=A-R0-CY , i.e. A=40H-25H-1=1AH
SUBB subtracts the source byte and the carry flag together from the accumulator, leaving the result in the accumulator.
SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and clears CY otherwise. (If CY was set before executing a
SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple precision subtraction, so the
carry is subtracted from the accumulator along with the source operand). If the state of the carry is not known before starting
a single or multiple-precision subtraction, it should be explicitly cleared by a CLR C instruction.
AC is set if a borrow is needed for bit 3, and cleared otherwise.
OV is set if a borrow is needed into bit 6 but not into bit 7, or into bit 7 but not bit 6. When subtracting signed numbers, OV
indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a
positive number is subtracted from a negative number.
The source operand allows four addressing modes: register, direct, register indirect, or immediate.
Example 9.4: W.A.P. to subtract two 8-bit numbers (Assuming 85H-72H). The minuend is stored in 50H and
subtrahend is in 51H of RAM memory locations. Store the result in 53H memory location.
Solution:
Start
ORG 00H
MOV A, 50H
SUBB A, 51H
MOV 53H, A
Stop
; A=85H
END
Example 9.5: W.A.P. to subtract two 16-bit numbers and store higher difference byte in R4 and lower difference byte
in R5. Assume numbers are 2375H (minuend) and 1284H (subtrahend).
Solution:
Algorithm
1. Subtract the lower bytes of the given numbers , i.e. 75H-84H=F1H and borrow/carry flag is 1(set).
2. Store the accumulator in 2090H memory location , i.e. stores the lower byte of result in R5.
3. Subtract the higher bytes of the given numbers with borrow , i.e. 23H-12H-1=10H
4. Store the accumulator in 2091H memory location , i.e. stores the higher byte of result into R4.
91
Start
Stop
ORG 0000H
MOV A, #75H
SUBB A, #84H
MOV R5, A
MOV A, #23H
SUBB A, #12H
MOV R4, A
; R4=10H
END
Example 9.6: Register R0 has 65H and the accumulator has 97H. Subtract the contents of register R0 from the
contents of the accumulator. Display the result on PORT 1.
Solution:
SUBB A, R0
; A=97H-65H= 32H
MOV P1, A
; display contents of A (result) at port 1 (address of port 1 is 01H)
used is wasted). The extra storage requirements are usually offset by the need for the
accuracy and compatibility with calculator or hand calculation that fixed-point decimal arithmetic provides.
92
The difference between Packed BCD number and two-digit BCD number is that both digits are individual represent two
separate BCD number for packed BCD while in two-digit BCD, we consider the both digits together are represent the
magnitude of data. However, here we use both packed BCD and two-digit BCD interchangeably.
If we are dealing with BCD numbers, there is a problem with adding two or more BCD numbers, which must be corrected.
The problem is that after adding packed or unpacked BCD numbers, the result is no longer in BCD format. Since, digital
processors have binary hardware. It needs to be clearly defined that BCD operands can never have any digit greater than 9 ,
i.e. digits A-F are not allowed for BCD addition.
For example: MOV A, #14H
ADD A, # 29H
Adding these two numbers gives 0011 11012 (3DH), which is not a BCD number because each digit of BCD number can
have from 0000 to 1001 (0 to 9). The correct result should have been 14+29=43 (0100 0011). In order to correct this problem,
the programmer must add 6 (0110) to the low digit: 14H +29H+6H=43H, in other words we can say that 3DH (0011 11012) in
hexadecimal is equal to the 43H (0100 00112) in BCD format. The same problem could have happened in the upper digit (for
example 72H+82H=F4H). Again to solve this problem 6 must be added to the upper digit (F4H+60H=154H) Hence, after
addition of BCD numbers, we must check the lower and upper 4-bit or nibble of the result, if lower 4-bit greater than 1001 add
6 (0110) in it and a carry (auxiliary carry) generated from lower nibble (D3), add it with upper nibble (D4) of the result than
check upper nibble, if greater than 1001(9) add 6, if a carry generated from D7, collect it in other 4/8-bit format to represent
upper BCD digit and result must be 12/16-bit otherwise result must be an 8-bit BCD number. The addition result for 8-bit BCD
number from 00 to 99. If addition result greater than 99, 12-bits or 16 bits are used to represent addition result.
Stop
ORG 000H
MOV A, #47H
ADD A, #25H
DA A
END
93
Example 9.8: Write a program to subtract the BCD number stored in R5 register from the number stored in the R6
register.
Solution:
The subtraction of BCD number is carried out 10's complement (for single digit) or 100's complement (for 2 digit number).
The 100's complement of a decimal number is equal to the 99's complement plus 1. The 99's complement of a number can
be found by subtracting the number from 99.
The steps for finding 100's complement BCD subtraction are:
Find the 100's complement of subtrahend
Add two numbers using BCD addition
In this way, when two BCD numbers are subtracted, we can use DA A instruction for adjusting the result to get BCD:
Source Program:
MOV A, #99
; Load 99 into A
SUBB A, R5
; Find the 99's complement of subtrahend
INC A
; Find 100's complement of subtrahend
ADD A, R6
; Add minuend to 100's complement of subtrahend
DA A
; Adjust for BCD
END
; Terminate program execution
Example 9.9: Write a program to add two 4-digits BCD numbers. Assume two 4-digit numbers are 3629 and 4738.
Solution:
MOV A, #29H
; Get lower 2 digits of no. 1
ADD A, #38H
; Add two lower digits
DA A
; Adjust result to valid BCD
MOV R3, A
; Store partial result (lower byte of result)
MOV A, #36H
; Get most significant 2 digits of number
ADDC A, #47H
; Add two most significant digits
DA A
; Adjust result to valid BCD
MOV R4, A
; Store partial result (upper byte of result)
END
; Terminate program execution.
Multiplication
The instruction format is as follows:
MUL AB
It multiplies the unsigned eight-bit data in the accumulator and register B. The low-order byte of the sixteen-bit product is left
in the accumulator, and the high-order byte in B. If the product is greater than 255 (0FFH) the overflow flag is set; otherwise it
is cleared. The carry flag is always cleared. In the following example, we are multiplying 80 (50H) by 160 (0A0H).
MOV A, #50H
MOV B, #0A0H
MUL AB
will give the product 12,800 (3200H), so B is changed to high byte of result 32H (00110010B) and the accumulator is
changed with low byte of result 00H. The overflow flag is set, carry is cleared.
Example 9.10: A = 135 decimal, B = 36 decimal. What would be the value in each register after executing the
instruction MUL AB?
Solution:
Multiplication operation AB gives 4860 =12FCH. The lower byte of the result 0001 0010 or 12H would be placed in A and
upper byte is 1111 1100 or FCH in register B.
Division
The instruction syntax is as follows:
DIV AB
It divides the unsigned 1-byte data in the accumulator (numerator) by the unsigned 1-byte data in register B (denominator).
The accumulator receives the integer part of the quotient; register B receives the integer remainder. The CY and OV flags will
94
be cleared if the denominator (B) is not 0. A real time application of this instruction is that to convert Hex data from an ADC to
decimal to display on 7-segment display by dividing Hex data by 10 repeatedly.
Note: If the denominator B is 00H, the values returned in the accumulator and B register will be undefined and the overflow
flag will be set to indicate a invalid result of infinity. The carry flag is cleared in any case. The following example shows a
division:
MOV A, # 251
; Load A with numerator 0FBH
MOV B, # 18
; Load B with denominator 12H
DIV AB
will leave quotient 13(0DH or 00001101 B) in A and the reminder value 17 (11H or 00010001B) in B,
Since 251 = (13x18) + 17. Carry and OV flags will both be cleared.
Example 9.11: Assume A = 135, B = 36. What would be the value in each register after execution of the instruction
DIV AB?
Solution: A/B = 3; remainder 27 (1BH): Hence 03H in A, 1BH in B
INCREMENT/DECREMENT
The 8-bit contents of an operand can be incremented or decrement by one. Note that when INC/DEC instruction is used to
modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.
The instructions for increment and decrement operation are described in the following sections:
Increment
INC increments the operand value by 1. An original value of 0FFH will overflow to 00H. No flags are affected. Three
addressing modes are allowed: register, direct, or register-indirect. The syntax is given below:
INC
A
; A=A+1
INC
Rn
; register = register +1
INC
direct
; Direct = direct+ 1
INC
@Ri
; @Ri= @Ri + 1
INC
DPTR
; DPTR = DPTR +1
See the following sequence of instructions performing Increment operations:
MOV A, #0FEH
; A=FEH
INC A
; A=A+1 = FEH + 1= FFH
INC 0E0H
; A= FFH + 1= 00H and CY is not set , i.e. CY=0.
Assume R0 =7EH. Internal RAM locations 7EH and 7FH contain 0FFH and 40H, respectively. The instruction sequence:
INC @R0
; RAM location 7EH contains 00H
INC R0
; R0=7FH
INC @R0
; RAM location 7FH contains 41H
Assume registers DPH and DPL contain 12H and 0FEH, respectively. The instruction sequence:
INC DPTR
; DPH= 12H and DPL= FFH.
INC DPTR
; DPH=13H and DPL=00H
INC DPTR
; DPH= 13H and DPL=01H
Decrement
DEC decrements the operand value by 1. An original value of 00H will be underflow to 0FFH. No flags are affected. Three
operand addressing modes are allowed: register, direct, or register-indirect. The syntax is given below:
DEC
A
; A=A-1
DEC
Rn
; register = register -1
DEC
direct
; Direct = direct- 1
DEC
@Ri
; @Ri= @Ri 1
See the following sequence of instructions performing Increment operations:
MOV A, #0FEH
; A=00H
DEC A
; A=A-1 = FFH and CY=0
DEC 0E0H
; A= FFH - 1= FEH
Assume R0 =7EH. Internal RAM locations 7EH and 7FH contain 00H and 40H, respectively. The instruction sequence:
DEC @R0
; RAM location 7EH contains FFH
DEC R0
; R0=7FH
DEC @R0
; RAM location 7FH contains 3FH
95
Example 9.12: Write an assembly language program to generate Fibonacci number of N given term and display
it to the port 1.
Solution: Fibonacci numbers are 0, 1,1,2,3,5,8,13,21 and so on.
We should choose Count Value (N) not more than 12 (0CH) to get the last number of Fibonacci series within 8-bit range.
Algorithm
0 1 1
Source Program
2 3
5 and so on..
MOV R2, #COUNT
MOV R3, #00
MOV A, R3
MOV R0, #01
BACK: ADD A, R3
MOV P1, A
MOV 3, 0
MOV R0, A
DJNZ R2, BACK
END
Start
Initialize R2 =COUNT
Clear A and R3
Initialize R0=01H
; Initialize counter
; R3=0 initialize variable to store previous number
; Initialize variable to store current number
; Add two numbers
; Send it out at port 1
; Current number is now previous number
; Save result as a new current number
; Decrement counter, if not zero, go to back
; Stop.
No
R3
R0
R2=R2-1
Is counter
R2=0?
Yes
Stop
96
Iteration table
st
nd
Iteration 1
2
A
R3
R0
1
1
1
2
1
2
3
2
3
5
3
5
8
5
8
13
8
13
0
1
0
1
0
1
rd
th
th
th
th
th
So
on
..
...
Start
A=A+@R0
Convert Hex addition result
into BCD equivalent
No
Is CY=0?
Check flag
JNC NEXT
INC R4
Yes
Save upper byte in R4;
R4=R4+1
NEXT: INC R0
R0=R0+1
Yes
Is R2=0?
R0=R0+1
Save lower byte of the result
R0=R0+1
Save Upper byte of the result
Stop
INC R0
MOV @R0, A ; Save LSDs of BCD result in memory
INC R0
MOV @R0, R4 ; Save MSD of BCD result in memory
END
REVIEW QUESTIONS
1. Explain the following instructions:
a) DA A
b) INC
c) SUBB
2. Write a program to add two numbers of 8-bit each.
3. Is there any difference between the following two instructions?
a) DEC A
b) SUBB A, #1
4. Is there any difference between the following two instructions?
a) INC A
b) ADD A, #1
5. DEC register can be used to decrement the contents of ----------------.
6. Write instruction to increment the contents of memory location 40H by 1.
7. Write instruction(s) to decrement the contents of the register R0 by 2.
8. Write a program to move the contents of memory location 20H to accumulator. Increment these contents by two and
place them in location 21H.
97
98
CHAPTER-10
LOGIC INSTRUCTIONS AND PROGRAMS
In this chapter, we will discuss those instructions which perform various logical operations with the contents of the
Accumulator and store the result in Accumulator itself except direct addressing instructions. These instructions are given in
table 10.1.
Table 10.1: Logic Instructions
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
Mnemonics
Function
ANL A, Rn
ANL A, direct
ANL A, @Ri
ANL A, #data
ANL direct, A
ANL direct, #data
ORL A, Rn
ORL A, direct
ORL A, @Ri
ORL A, #data
ORL direct, A
ORL direct, #data
XRL A, Rn
XRL A, direct
XRL A, @Ri
XRL A, #data
XRL direct, A
XRL direct, #data
CLR A
CPL A
RL A
RLC A
RR A
RRC A
SWAP A
Machine Cycle/Byte
1/1
1/2
1/1
1/2
1/2
2/3
1/1
1/2
1/1
1/ 2
1/ 2
2/3
1/1
1/2
1/1
1/2
1/2
2/3
1/1
1/1
1/1
1/1
1/1
1/1
1/1
Flags affected
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
CY
none
CY
none
LOGICAL INSTRUCTIONS
These instructions perform Boolean logic operations. The two operands allow six addressing mode
combinations. When the destination is the accumulator, the source can use register, direct, register-indirect,
or immediate addressing; when the destination is a direct address, the source can be the accumulator or
immediate data. No flags are affected. When this instruction is used to modify an output port, the value used
as the original port data will be read from the output data latch, not the input pins. Each is explained below:
Logical AND
The formats for AND instructions are given below:
ANL destination, source
; destination= destination AND source
ANL A, Rn
; A= A AND Rn
ANL A, direct
; A =A AND (direct)
ANL A, @Ri
; A= A AND @Ri
ANL A, #data
; A= A AND data
ANL direct, A
; (direct) = (direct) AND A
ANL direct, #data
; (direct) = (direct) AND data
The ANL performs the bitwise logical-AND operation between the source and destination bytes and stores the results in the destination.
See the following example:
MOV A, #12H
; A=12H
MOV R3, #23H
; R3=23H
ANL A, R3
; A=02H
12H in binary
00010010
23H in binary
00100011
12H AND 23H 00000010=02H will placed in Accumulator.
99
When the destination is a directly addressed byte, this instruction will clear combinations of bits in any RAM location or
hardware register. The mask (set to 0) byte determining the pattern of bits to be cleared would either be a constant contained
in the instruction or a value computed in the accumulator at run-time.
The instruction
ANL P1, #01110011B
will clear bits 7, 3, and 2 of output port 1.
Example 10.1: Write a program to mask upper nibble of the Accumulator. Assume accumulator contains 78H.
Solution:
MOV A, #78H
; A=78H
ANL A, #0FH
; A= 78H AND 0FH= 08H
ORL performs the bitwise logical OR operation between the indicated variables, storing the results in the
destination byte. See the following example,
MOV A, #55H
; A=55H
ORL A, #AAH
; A= 55H OR AAH=FFH
MOV R0, A
; R0=FFH
MOV A, #00H
; A=00H
ORL A, R0
; A= 00H OR FFH =FFH
Explanation
55H in binary
01010101
AAH in binary
10101010
55H OR AAH
11111111=FFH
00H OR FFH
11111111=FFH will stored in accumulator.
Another aspect of masking is to use the ORL instruction to force a particular bit to logic 1, at the same time, not altering other
bits. The instruction
ORL P1, #00110010B
100
CLR (CLEAR)
This instruction is used to clear (all bits set to zero) destination operand. The destination may be 8-bit Accumulator, any
directly addressable bit or carry flag. No flags are affected.
CLR A
; The accumulator is cleared (all bits set to zero).
Assume the accumulator contains 5CH (01011100B). The instruction CLR A will set the accumulator to 00H.
CLR bit
CLR C
; Clear bit
; Clear carry flag
For example: Port 1 has previously been written with 5DH (01011101B). The instruction CLR P1.2 will leave the
port set to 59H (01011001B).
CPL A (COMPLEMENT ACCUMULATOR)
Each bit of the accumulator is logically complemented (ones complement). Bits which previously contained a one
are changed to zero and vice versa i.e. All 0s are replaced by 1s and all 1s are replaced by 0s. No flags are affected.
For instance, assume the accumulator contains 5CH (01011100B). The instruction CPL A will leave the
accumulator set to 0A3H (10100011 B).
Example 10.3: Write a program to take 2s complement of a number.
Solution:
MOV A, #55H
; A= 01010101B
CPL A
; After execution A=AAH=10101010B i.e. 1s complement of 55H.
INC A
; After execution A=10101011B=ABH which is 2s complement of 55H, stored in A.
ROTATE ACCUMULATOR
Each bit in the accumulator can be shifted either left or right to the next position with carry bit or without carry bit.
RLC A
(Rotate accumulator left through the carry)
The eight bits in the accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the
carry flag; the original state of the carry flag moves into the bit 0 position.
CY
MSB
LSB
For example:
MOV A, #0C5H
RLC A
CY
MSB
LSB
For example:
MOV A, #0C5H
RRC A
RL A
101
The eight bits in the accumulator are rotated one bit to the left. The bit 7 is rotated into the bit 0 position.
MSB
LSB
For example:
MOV A, #0C5H
RL A
; A= 0C5H (11000101B)
; A=8BH (10001011B)
MSB
LSB
For example:
MOV A, #0C5H
RR A
; A= 0C5H (11000101B)
; A= 0E2H (11100010B)
For example:
MOV A, #45H
SWAP A
; A=45H
; A= 54H
Example 10.4: Write a program to exchange the nibbles without using SWAP instruction.
Solution:
MOV A, #45H
; A=45H
RL A
; Rotate left
RL A
; Rotate left
RL A
; Rotate left
RL A
; Rotate left (A=54H)
Example 10.5: Write a program to send a data byte (stored in RAM location 50H) serially (LSB first) on a port pin.
Solution:
MOV A, 50H
; Load A with data byte
MOV R2, #08H
; Initialize counter to 8 times
L1: RRC A
; LSB to Carry bit
MOV P1.2, C
; Output data bit
DJNZ R2, L1
; Repeat 8 times
END
102
Example10.6: Write a program to break a packed BCD number into two unpacked BCD numbers.
Assume a packed BCD number is 85H.
Solution:
Algorithm: To convert packed BCD to unpacked BCD:
Packed BCD
Unpacked BCD
85H
08H and 05H
1000 0101
0000 1000 and 0000 0101
MOV A, #85H
MOV R0, A
ANL A, #0FH
MOV R1, A
MOV A, R0
ANL A, #0F0H
SWAP A
MOV R2, A
; A=85H
; R0=85H
; Mask the upper nibble (A= 05H)
; Save a unpacked BCD into R1 (R1=05H)
; Get original packed BCD back
; Mask the lower nibble (A=80H)
; A=08H
; Save other unpacked BCD into R2 (R2=08H)
Example 10.7: W.A.P. to mask (make 0) upper nibble and store the result in register R0, and then mask lower nibble
of the original number and store the result in register R1. The original number is stored in 30H RAM location.
Solution:
Start
Stop
ORG 0000H
; PC=0000H
MOV A, 30H
MOV R4, A
ANL A, # 0FH
MOV R1, A
MOV A, R4
ANL A,#0F0H
MOV R0, A
END
103
use ASCII standard. In order to make BCD standard compatible with ASCII, a conversion program is used between ASCII
and BCD. Some microcontroller has real time clock (RTC), they provide the time (h-m-s) and date (y-m-d) in BCD.
Therefore, to display BCD data they must be converted into ASCII representation. See the table 10.2:
Table 10.2: ASCII and BCD representation for decimal digits (0-9)
Decimal Digit
0
1
2
3
4
5
6
7
8
9
Binary value
0011 0000
0011 0001
0011 0010
0011 0011
0011 0100
0011 0101
0011 0110
0011 0111
0011 1000
0011 1001
Stop
ORG 0000H
MOVA, #67H
MOV R3, A
ANL A, # 0FH
ORL A, #30H
MOV R6, A
MOV A, R3
ANL A, #0F0H
RL A
RL A
RL A
RL A
ORL A, #30H
MOV R7, A
END
104
Example10.12: Write a program to convert ASCII code to packed BCD. Assume ASCII characters are 6 and 7.
Solution:
ASCII
Unpacked BCD
Packed BCD
6=36H
0000 0110
7=37H
0000 0111
0110 0111 (67H)
Algorithm:
2. Separate into nibbles (unpacked)
3. Convert each nibble into ASCII code
4. Store the ASCII codes in memory location 2051H and 2052H.
ORG 00H
MOV A, # 36H
MOV R0, # 7
ANL A, #0FH
ANL R0, #0FH
SWAP A
ORL A, R0
END
REVIEW QUESTIONS
1. If A = 2D, what would be the accumulator contents after execution of the instruction ANL A, #3BH?
2. If the contents of register 0 (R0) = 38H, what would the contents of that register be after execution of the
ORL R0, #9AH instruction?
3. Write a program to count the number of 1s in a 16-bit number.
4. Rotate the contents of the accumulator by one bit to the left through carry. And comments on carry flag status.
5. Show the contents of register A, R0 and the status of flags after executing each of following instruction:
MOV A, #77H
MOV R0, A
INC R0
ADD A, R0
ORL A, R0
XRL A, R0
Also comment on operation performed by each instruction.
6. Write a program to set zero flag, if the input port reading is zero without affecting the contents of the accumulator.
7. XRL can be used to .Accumulator.
8. Write a program to performing following functions:
a) Load the data byte 5AH in register R7.
b) Mask lower nibble
c) Display the result at output port.
9. Explain the operation performed by the following program:
MOV A,# D2H
ANL A, #0FH
RR A
RR A
RR A
RR A
(ANSWER: mask upper nibble (02H) and then swap nibbles (20H).
10. Write a program to mask lower nibble
11. The contents of A register is 0000 0001B. Specify the contents of A register after rotating left 4 times.
12. After executing XRL A, A the zero flag will be set. State true or false.
13. Write programs for following operations:
a) Load the A with A1H, and mask all bits except D0 of A.
b) Multiply by 2 without using MUL
c) Divide by 2 without using DIV
14. In an 8-bit operand, bit D7 is used for sign bit. State true or false.
15. Write a program to convert -16H to its 2s complement representation.
16. Explain the difference between a carry and an overflow.
17. For the following decimal numbers, give the packed BCD and unpacked BCD representation.
a) 16
b) 99
105
CHAPTER-11
SINGLE BIT HANDLING INSTRUCTIONS
A special and powerful feature of the microcontrollers is that they can handle single bit data. In the 8051,
single bit handling instruction in vicinity and allow the user to manipulate individual bit of port, RAM bit
addressable area and some Special function register that have 0 or 8 as the last digit in their hex address.
See the table 11.1:
Table 11.1: Boolean Variable Manipulation
Mnemonics
Function
Machine Cycle/Byte
1. CLR C
Clear Carry
2. CLR bit
Clear direct bit
3. SETB C
Set Carry
4. SETB bit
Set direct bit
5. CPL C
Complement Carry
6. CPL bit
Complement direct bit
7. ANL C, bit
AND direct bit to Carry
8. ANL C, /bit
AND complement of direct bit to Carry
9. ORL C, bit
OR direct bit to Carry
10. ORL C, /bit
OR complement of direct bit to Carry
11. MOV C, bit
Move direct bit to Carry
12. MOV bit, C
Move Carry to direct bit
13. JC rel *
Jump if Carry is set
14. JNC rel*
Jump if Carry not set
15. JB bit, rel *
Jump if direct Bit is set
16. JNB bit, rel*
Jump if direct Bit is Not set
17. JBC bit, rel*
Jump if direct Bit is set and clear bit
Note: - *These instructions are already discussed in chapter-9.
C: Carry bit
rel: Relative address to the PC used for short jump (SJMP) and all conditional jumps.
bit: Directly addressed bit in internal RAM or SFR
1/ 1
1/ 2
1/ 1
1/2
1/1
1/ 2
2/ 2
2/2
2/ 2
2/2
1/2
2/2
2/2
2/2
2/3
2/3
2/ 3
Flags affected
CY
none
CY
none
CY
none
CY
CY
OV
OV
OV
none
none
none
none
none
none
Example 11.1: In the following instruction sequence, find the carry flag. What are the contents of the
accumulator?
SETB C
; CY=1
MOV A, #01H
; A=0000 0001B
RRC A
; Rotate Accumulator right through Carry
CPL C
; Complement CY
END
Solution: The SETB instruction sets the carry flag to 1. The MOV instruction loads 01H into the accumulator. The RRC
instruction rotates the accumulator 1 bit to the right. The contents of the accumulator are 1000 0000 (80H) and Carry flag
loaded by D0 i.e. carry flag is set i.e. CY=1. The CPL instruction reset the carry flag i.e. CY=0.
Example 11.2: Write a program to monitor the status of the smoke sensor continuously in an office (See figure
11.1). The smoke sensor is connected to bit-2 of port-1 and buzzer to bit-3 of port-1. If there is smoke, sensor
gives a high pulse to P1.2 and put the buzzer on.
Solution:
SETB P1.2
; Configure P1.2 as input pin
L1: MOV C, P1.2
; Read pin P1.2
JNC N1
; If not carry jump to N1
MOV P1.3, C
; If carry, send a high to buzzer
ACALL DELAY
; Wait
N1: SJMP L1
; keep monitoring
Figure 11.1: Sensor and buzzer arrangement
Example 11.7: Write a program to find data is even or odd in a given byte. If given data is even store it in R0. If
odd, save it in R7.
Number Binary Status
Solution:
1
0001
odd
Check
(a)
MOV A, # DATA
JB ACC.0, N1
MOV R0, A
SJMP EXIT
N1: MOV R7, A
SJMP EXIT
EXIT: .
0010
even
0011
odd
0100
even
0101
odd
0110
even
0111
odd
And so on.
last bit
of each
number?
If D0=0,
no. is
even.
If D0=1,
no. is
odd
Figure 11.3: Arrangement to allow a port pin to source and sink current
The inverter gate (buffer) in the above circuit (figure 11.4) provides a good current buffer protecting to the microcontroller
port pin from unnecessary current loading. In the above circuit the current flow is between the inverter gate and the 5V
DC supply.
Example 11.8: Interface a port pin with a LED.
Solution: Assume that pin 2 of port 1 is connected to a LED as shown in figure 11.4. The instruction SETB P1.2 puts logic 1 (5 V) onto
the inverter input and therefore its output connected to the LED cathode, is at 0V causing current to flow through the LED. The LED has
a particular forward voltage VF (refer LED data specification sheet). For a typical LED, VF=2V and forward current IF=12 mA so that:
-3
R= (5V-VF) / IF = (5-2) / (12 10 ) = 250
CLR P1.2 ; clears bit-2 on port 1 to zero and puts logic 0 on the buffer input and therefore its output, the LED cathode,
becomes logic 1 which is 5 V. This gives a voltage difference (5V DC cathode voltage) of 0V and the LED turns off.
109
MOV B, #0AH
MUL AB
ADD A, R0
MOV 51H, A
END
Example 11.10: W.A.P. to convert the BCD numbers from 0 to 30 which are stored in data memory location from 30H
to 4EH into its binary equivalent numbers and store the binary equivalent result in a data memory location from 50H
to 6EH.
Solution:
ORG 00H
; Start program execution from program memory location 2000H
MOV R0, 30H
; Initialize data memory pointer to bring packed BCD number from data memory, i.e. source pointer
MOV R1, 50H
; Initialize another data memory pointer to save binary equivalent number to data memory, i.e. destination pointer
MOV R2, 1FH
; Set counter at 31 i.e. R2=1FH
L1: MOV A, @R0
; Get the packed BCD number from data memory location indicated by @R0
LCALL BCD2BIN
; Call the Packed BCD to binary conversion subroutine.
MOV @R1, A
; Store the A (binary equivalent) into data memory pointed by @R1 destination pointer
INC R0
; Increment R0 (source pointer) to get next packed BCD number.
INC R1
; Increment R1 (destination pointer) to store next binary equivalent number.
DJNZ R2, L1
; Repeat until R2=0
END
BCD2BIN: MOV R3, A
; Save a copy of the contents of accumulator, i.e. R3=A=XX10
ANL A, #0FH
; Mask upper nibble of Accumulator, i.e. A=0X10
MOV R4, A
; Save unpacked BCDL in R4 register, i.e. R4=0X10
MOV A, R3
; Get BCD again to unpacked BCDU, i.e. A=XX10
ANL A, #F0H
; Mask lower nibble of Accumulator after execution this instruction A=X010
SWAP A
MOV B, #0AH
; Set B register as multiplier of 0AH, B=0AH
MUL AB
; Multiplication BCDU by 0AH
ADD A, R4
; Add BCDL
RET
; Return to main program
Here X represent decimal digit from 0 to 9.
110
ORG 100H
MOV A, 50H
MOV B, #100
DIV AB
MOV 51H, A
MOV A, B
MOV B, #10
DIV AB
SWAP A
ADD A, B
MOV 52H, A
END
g
e
d
DP
LEDs
to display 0; LEDs
a,b,c,d,e,f are ON and g is OFF
to display 3; LEDs
a,b,c,d,g are ON and f,e are OFF
Common Anode seven segment LED arrangement: A common anode seven-segment display is sometimes used in applications were the
driving IC cannot supply all of the required current but it can pull it to ground.
+Vcc
OFF 1 (+Vcc)
+Vcc
ON
+Vcc
0 (ground)
a
B
c
d
e
f
g
DP (not consider so left it unconnected)
1 (+Vcc)
ON
ground
Ground
DP
dp (not consider so left it unconnected)
111
The wiring for a common anode and common cathode are shown below:
Hex
code
for CC
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
3F
06
5B
4F
66
6D
7D
07
7F
6F
77
7C
39
5E
79
71
1
0
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
1
1
1
0
0
1
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
1
1
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
1
0
1
0
0
1
0
0
0
0
0
0
1
0
1
0
0
Hex
code
for CA
40
79
24
30
19
12
02
78
00
10
08
03
56
21
06
0E
From the above table, we can see that there is no direct relationship between seven-segment code (both type) and binary/Hex
numbers. This is because of hardware consideration in between seven-segment code and binary numbers. Therefore, in the
order to display a BCD digit on seven-segment display (LED), we use Look-up-table technique.
In Look-up-table techniques, the codes of the digits to be displayed on seven-segment LED are stored sequentially in data
memory. The conversion program for a BCD digit to be display brings that particular code from data memory to the
microcontroller and it sends it out to the output port (seven-segment LED display). For example: suppose common cathode
based seven-segment LED is display unit.
112
Decimal digit
0
1
2
3
4
5
6
7
8
9
MOV DPTR, #370H
MOV A, #02H
MOVC A, @A+DPTR
MOV P1, A
CALL DELAY
END
Look-up-table
(ROM location)
370
371
372
373
374
375
376
377
378
379
REVIEW QUESTIONS
1. Discuss about various Bit handling instructions in detail
2. Create a Square wave of 50% duty cycle over Port 0.0.
3. WAP perform a) keep monitoring the P0.1 until it becomes high b) When P0.1 become high, read data
from Port 1 and c) send a low to high pulse on P0.2 indicate that data has been read.
4. WAP to toggle P1.3, P1.7, P.15 continuously without disturbing other pins of port.
5. Sate the Bit address of various ports and SFRS. (See the chapter 5, figure 5.7)
6. WAP to find the number of zeros in register R2 of bank-0.
7. Write a program to set all the bits of RAM locations 20H to 28H using byte addresses and bit addresses.
8. Write a program to determine the number of zeros in the A.
9. Write a program to generate a square wave with 90% duty cycle.
10. Which register bank is used if we alter RS0 and RS1 of the PSW by the following 2 instruction?
SETB PSW.3
SETB PSW.4
11. Write a program to convert a binary number into packed BCD.
12. Write a program to display a packed BCD at seven-segment display with following configuration:
a) Common cathode
b) common anode
13. Design a BCD counter to count from 00 to 99 with 1 ms delay between each count. Display the lower
nibble count at port 0 and upper nibble at port-1.
14. Write a program to convert a set of binary numbers into equivalent ASCII codes.
15. Write a program to convert a set of ASCII code into binary equivalent.
16. W.A.P. to display a block of data (packed BCD no.). The length of the block is in memory location 30H
and the block itself begins from the memory location 31H.
17. Design Temperature controlled system using 8051 where system is sensed temperature of furnace at a
regular interval. If it exceeds the desired level (assume) then Heater control should be turn off
otherwise it remains on?
113
CHAPTER-12
TIMER/COUNTER IN THE 8051
Many applications require the counting of external events, calculate the frequency of an external pulse train, or generate a
precise delay. There are two techniques to count external event or generate a precise delay: software and hardware
techniques. In the software technique, the microcontroller remains busy all the time in generating delay or counting
outside event. We have discussed software technique in previews chapters; we can see that this technique keeps the
microcontroller occupied. Hence, no other task can be performed.
In the hardware technique, the microcontroller can perform other useful task with generating delay and counting outside
events, simultaneously. Therefore, better to use hardware techniques, i.e. timers (internal clocks counting) and counters
(outside event counting).
TIMERS PROGRAMMING
In the 8051, there are two 16-bit timers/counters. Both can either be programmed to:
1. Count internal clock (as a timer)
2. Count external event or clock (as a counter)
Both can be independently configured to operate in a variety of modes as a timer or as an event counter. When operating
as a timer, the timer/counter runs for a programmed length of time, and then issues an interrupt request. When operating
as a counter, the timer/counter counts negative transitions on an external pin. After a preset number of counts, then
counter issues an interrupt request.
In the timer mode, the counter is incremented in every machine cycle. Thus, one can think of it as counting machine
th
cycles. Hence the clock rate is 1/12 of the oscillator frequency.
Example 12.1: Find the timer clock frequency and period for the following crystal frequencies:
1. 12 MHz
2. 11.0592 MHz
Solution:
1. 1/12 12 MHz= 1MHz and period= 1/1MHz= 1 s
2. 1/12 11.0592 MHz= 921.6 KHz and period = 1/921.6 KHz = 1.085 s
In the counter mode, the register is incremented in response to a high (1) to low (0) transition at its corresponding external
th
input pin (T0 or T1). It requires 2 machine cycles to detect a high to low transition. Hence maximum count rate is 1/24 of
oscillator frequency.
All timer/ counter action is controlled by the TMOD (timer mode register) and the TCON (timer/counter control register).
TIMER/COUNTER REGISTERS
The original 8051 has two 16-bit timer/counter registers known as timer 0 and timer 1. Timers 0 and 1 are up-counters
and may be programmed to count internal clock pulses (timer) or count external pulses (counter). Each 16-bit timer is
divided into two separate 8-bit registers of timer low and timer high bytes i.e. TL0, TH0 and TL1, TH1 (these registers is
byte addressable not bit addressable). The operation of the timer/counter is controlled by the TMOD and TCON registers
of the SFRs. The 8-bit TMOD is the timer SFR in which two identical 4-bit registers, one each for the two timers. The 8-bit
TCON consists of control bits and flags.
Timers 0 and 1 are fundamentally the same and both have two 8-bit registers, timer high (TH) byte and timer low (TL)
byte. Both share the timer control (TCON) register and the timer mode (TMOD) register. The programming model for the
timer/counter registers is shown in figure 12.1. All registers in the programming model are accessible using direct
addressing and register addressing.
114
These registers are allocated in SFR space with the following addresses:
SFR name
TL0
TH0
TL1
TH1
TCON
TMOD
Description
Timer 0 lower order byte
Timer 0 higher order byte
Timer 1 lower order byte
Timer 1 higher order byte
Timer control
Timer mode control
SFR address
8AH
8CH
8BH
8DH
88H
89H
GATE (Gating Hardware/software control): In the 8051, The start and stop of the timer is controlled by hardware
control or software control. In softaware control, GATE bit must be cleared (GATE=0) and then TR0 bit for timer 0 and
TR1 for timer 1 bits (TR bits in TCON register) are programmed to start (SETB TR0 for timer 0 start) or stop (CLR TR0 for
timer 0 stop).
In hardware control, GATE bit must be set (GATE=1) and then external source controls which is connected to the INTx
pin (P3.x) the timers start and stop operation. The table briefs the operation.
GATE
Input at INTx (P3.x) Timer status
1
high
Start counting
1
low
Stop counting
0
x
To start counting use SETB TR (TR0 or TR1)
0
x
To stop counting use CLR TR (TR0 or TR1)
Whare INTx (P3.x) represent INT0 (P3.2 pin) for timer 0 and INT1 (P3.3) for timer 1.
C/T (Counter/ Timer selection bit): This bit is used to select whether the timer is used to generate a delay or an event
counter. If this bit is clear (C/T=0), it is used for timer operation to generate delay (input from crystal frequncy of the
8051) and count every machine cycle (12 clocks). If this bit is set (C/T=1), it is used for counter operation to count an
external event pulses (input from Tx input pin). See the table below:
C/T
Operation
1
0
Where Tx (P3.Y) represent T0 (P3.4 pin) for timer 0 and T1 (3.5 pin) for timer 1.
M1 and M0 (Mode select): The M1 and M0 bit functions depend on the bit assignment as shown in following table.
M1
M2
Mode
Operation
0
0
1
0
1
0
0
1
2
Where THx and TLx denotes TH0 or TH1 and TL0 or TL1.
115
Bit Name
TF1
TR1
TF0
TR0
Function
Timer 1 overflow: The hardware sets this bit when timer1 overflows.
Timer 1 run control bit set/cleared by software to turn Timer/counter on/off.
Timer 0 overflow: The hardware sets this bit when timer1 overflows.
Timer 0 run control bit set/cleared by software to turn Timer/counter on/off.
Figure 12.2: Circuit for timer 0/1 operating as a 16-bit up-counter in mode 1
116
00H, so C/T=0 and the peripheral defaults to being a timer rather than a pulse counter. The default value of GATE is 0
and this is inverted, so the OR output defaults to logic 1. The timer is turned on or off by TR1/0 (in TCON register), putting
TR0=1 would turn timer 0 on.
In mode 1, the TH and TL registers in timer 0 or timer 1 join to form a 16-bit up counter. The counter can be loaded with a
base number from which the timer can increment upwards towards the 16-bit maximum of 65535 (FFFFH). The time
taken to count from the base number to the maximum count value is the required delay. For instance, assume that the
timer is loaded with the base count of FFF0H, timer starts counting from FFF0H to FFFFH. When it rolls over from FFFFH
to 0000H, it sets timers flag bit TF=1. Figure 12.3 shows the method of achieving the required delay.
Example 12.3: Write a program to generate a 1 kHz square-wave signal from pin 2 on port 1. Assume that the
crystal frequency is 11.0592 MHz and timer 1 is used to generate delay.
Solution: The steps are given below should be following:
(a) Determine the required delay time.
(b) Determine the base numbers.
(c) Write the program
The required waveform is shown in Figure 12.4.
(a) One cycle time T of the required square-wave signal equals
1/frequency
Time period (T) = 1/ 1 kHz = 1 ms
Delay time= T/2=0.5 ms
(b) Timer clock = crystal frequency/ 12= 11.0592 MHz /12= 921.6
kHz
(c) The timer clock increments in timer clock cycles from the base number up to the maximum value of the 16-bit
register, which is FFFFH. One more increment would cause the register to rollover to 0000H and set the timer flag
(TF) to 1. The TF is a bit in the TCON SFR:
On power-up the default values of all the TCON bits are zero and so the timer flags TF1 and TF0 are 0. Timer 1 is
117
turned on by making TR1=1 and it is turned off by making TR1=0; the control action of timer 0 is the same using
TR0. As soon as TR0=1, the timer 0 mode1 TH0, TL0 registers start incrementing upwards from their base count.
Upon rollover the TF0 flag sets to 1 and this indicates that the delay has been completed.
Steps to program in mode-1:
1. Load the TMOD register with the appropriate word to select timer/control 0 or/and timer/control 1and timer
mode.
2. Load TH and TL with base count value.
3. Start the timer.
4. Keep check Timer flag. If high stop the timer and clear TF.
5. Go back to step-2.
MOV TMOD, #10H
L2: MOV TH1, #0FEH
MOV TH0, #33H
CPL P1.2
SETB TR1
L1: JNB TF1, L1
CLR TR1
CLR TF1
SJMP L2
; Timer 1, mode-1
; Load timer TH1 with upper order base count byte of FEH
; Load timer TL1 with lower order base count byte of FEH
; Toggle P1.2
; Start the timer 1
; Check TF1? If TF1=0, Keep check
; If TF1=1, Stop the timer 1
; Clear TF1, for the next counting
; Keep generating
For the scientific calculator, the following steps give the base count in Hex:
1. Enter the value of delay count i.e. 461
2. Press hex to convert it to Hex i.e. 01CDH
3. Press +/- button, which give FE33H (as our count value is 16 bit wide, so take last four digits and ignore all the
Fs)
Example 12.4: Calculate the frequency of the square wave generated by the program in the example 12.3.
Solution:
Machine Cycles
MOV TMOD, #10H
(outside from the loop)
L2: MOV TH1, #0FEH
2
MOV TL1, #33H
2
CPL P1.2
1
SETB TR1
1
L1: JNB TF1, L1
461 + 1 (roll over)
CLR TR1
1
CLR TF1
1
SJMP L2
2
Total= 472
Time period= 2 472 1.085 s =1024.24 s
6
Frequency of the square wave = 10 /1024.24 = 976.33 kHz.
118
We can see there is much difference in between actual frequency and given frequency generation. In the base count calculation for
time delay generation, we did not include the extra machine cycles due to instructions in the loop. In order to get correct frequency
generation, we need to subtract extra clock cycles from delay count (472- 461= 11) due to instruction in delay count value, i.e. 46111=450. Therefore new base count value is given by:
New base count = 65535 (FFFFH) - 450 (01C2H) =65085 (FE3DH) and loaded as given below:
FE hex to go into TH1
3D hex to go into TL1
Example 12.6: Repeat example 12.3, to produce a 2 kHz square wave at port 1, pin 2. Assume the clock frequency
remains at the same value and timer 0 is used to generate waveform.
Solution:
(a) One cycle time T of the required square-wave signal equals 1/frequency
Time period (T) = 1/ 2 kHz = 0.5 ms
Delay time= T/2=0.25 ms
(b) Timer clock = crystal frequency/ 12= 11.0592 MHz /12= 921.6 kHz
; Timer 0, mode 1
; toggle port bit
; Call DELAY subroutine
; Keep generating
; Load lower base count byte, TL0=0EH
; Load upper base count byte, TH0=FFH
; Start the timer-0
; Jump to L2 if TF0 is not 1
; Turn off the timer-0
; TF=0
; Go back to main program
Example 12.7: Find out the frequency of the generated square wave in the following program. Assume that
crystal frequency is 11.0592MHz.
ORG 40H
; Program start address at 0040H
MOV TMOD, #01H
; Put Timer 0 into mode 1
AGAIN: SETB P1.3
; Pin 3 port 1 to logic 1 (5 volts)
ACALL DELAY
; Go to subroutine delay
CLR P1.3
; Pin 3 port 1 to logic 0 (0 volts)
ACALL DELAY
; Go to subroutine delay
SJMP AGAIN
; Repeat
DELAY: MOV TH0, #00H
119
120
Example 12.8: The 8051 microcontroller having an 11.0592MHz clock is to be used to generate a 5 kHz squarewave signal from pin 2 of port 1. Write a suitable program to achieve this.
Solution: One cycle time T of the required square-wave signal equals 1/frequency
Time period (T) = 1/ 5 kHz = 0.2 ms
Delay time= T/2=0.1 ms
Timer clock = crystal frequency/ 12= 11.0592 MHz /12= 921.6 kHz
; Turn Timer 0 on
; Repeat until rollover when TF0=1
; Turn Timer 0 off
; Clear TF0 back to 0
; Return to main program from delay subroutine
Example 12.9: Find out the frequency of the generated square wave in the following program. Assume that
crystal frequency is 11.0592MHz.
ORG 40H
; Program start address at 0040H
MOV TMOD, #20H
; Initialize timer 1 into mode 2
MOV TH0, #0H
; Load base count into TH0
AGAIN: SETB P1.3
; Pin 3 port 1 to logic 1 (5 volts)
ACALL DELAY
; Go to subroutine delay
CLR P1.3
; Pin 3 port 1 to logic 0 (0 volts)
ACALL DELAY
; Go to subroutine delay
SJMP AGAIN
; Repeat
DELAY: SETB TR0
; Turn Timer 0 on
L1: JNB TF0, L1
; Repeat until rollover when TF0 = 1
CLR TR0
; Turn Timer 0 off
CLR TF0
; Clear TF0 back to 0
RET
; Return from delay subroutine
Solution: TH is loaded with zero i.e. timer counts from 00 to FFH.
FFH - 00(base count) +1=256 machine cycles.
Time delay generated by the delay subroutine is 256 1.085 s= 277.76 s (this is the largest time delay we can get
using mode-2) and time period of the square wave is 555.52 s. Therefore, frequency of the generated square waveform
is 1/555.52 s 1.8 kHz (this is the smallest frequency we can generate in mode-2).
LARGE TIME DELAY GENERATION (MIXED APPROACH)
The example 12.7 for 16-bit register and example 12.9 for 8 bit register shows that the largest time delay generation. The
size of time delay also depends on crystal oscillator frequency. In order to generate larger time delay, we can use timer in
a loop by using DZNZ instruction. See the following examples:
Example 12.10: Write a program to generate 10 s time delay.
Solution:
The largest delay generated in mode-1 is 71 ms, and this is achieved by loading 00H in the TH and TL. The count value
for the counter register is calculated as given below:
121
Count value =10 s/ 71 ms=141 (8CH) should be loaded into counter register.
MOV TMOD, #01H
; Initialize timer 0 in mode 1
MOV R2, #8CH
; Initialize counter
L2: MOV TL0, #00
; TL0=00H
MOV TH0, #00
; TH0=00H
SETB TR0
; Turn on timer 0
L1: JNB TF1, L1
; Repeat until rollover when TF0 = 1
CLR TR0
; Stop timer 0
CLR TF0
; Clear timer 0 flag
DJNZ R2, L2
; Reload timer if R2 not zero
Example 12.11: Find the value loaded into the timer registers for each of the following:
1. MOV TH0, # -2
2. MOV TH1, # -20
3. MOV TH1, # -220
Solution: These values can be find out easily by using a scientific calculator; select decimal and enter -2 using
+/- key. Then select hex, use right two digit which is loaded in timer register and we get:
1. The 2s complement of -2 is FEH, TH0=FEH.
2. The 2s complement of -20 is ECH, TH1= ECH.
3. The 2s complement of -220 is 24H, TH1=24H.
Mode 3 (Split mode)
This occurs when TMOD register mode bits M1 = 1, M0 = 1. Under these conditions timer 1 is off and simply hold their
count value. When timer 0 is operated in this mode, it essentially becomes two separate 8-bit timers, i.e. timer 0 is TL0
and Timer 1 is TH0. The control bit TR1 and timer flag TF1 are then used by timer 0 with the arrangement shown in figure
12.7.
TL0 sets timer flag TF0 whenever overflow occurs while TH0 is controlled by TR1 and sets the timer flag TF1 whenever it
overflows. Mode 3 is provided for applications that require an extra 8-bit timer on the counter.
122
The pulse from the sensor can be given as an external input to a counter. The counter can be programmed to produce an
interrupt after a predefined count value. The 8051 timers when operated as counters can count pulses applied at the P3.4
for timer/counter 0, and P3.5 for timer/counter 1 as shown in figure 12.9.
The counters will scan the voltage levels on these pins after every machine cycle (12 clock cycles). It takes two machine
cycles (24 clock cycles) to recognize a 1-to-0 transition on these pins as a pulse input; the maximum count rate is 1/24 of
the oscillator frequency. For the 11.0592 MHz clock, the maximum external input frequency that can be counted is
4, 60,800 pulses/ second.
When the timer/counter is performing the counter function the register is incremented in response to a falling edge
transition at its external input pin (T0 or T1). The TMOD bit C/T must be set to 1 to enable the pulses from the Tx pin to
reach the control circuit. To count a certain number of internal or external pulses a number is put into one of the counters;
the number inserted represents the maximum count, less the desired count, plus one. The following table shows the pin
description for timers:
Port Pin
Function
Operation
P3.4
T0
External input to Timer/counter 0
P3.5
T1
External input to Timer/counter 1
There are no restrictions on the duty cycle of an external input cycle but to ensure a given level is sampled at least once
before it changes it should be held for at least one full cycle. The counter will increment from the initial number to the
maximum and then resets to zero on the last pulse, setting the timer flag. Testing the flag state allows confirmation of the
completion of the count or, alternatively, the flag may be used to interrupt the program.
The counters have four operating modes (modes 0, 1, 2 and 3), which are determined by the status of the bits M0 and M1
in the TMOD register. Modes 0, 1 and 2 are the same for both timers/counters but this is not the case for mode 3. In
general, mode-1 is preferred for counting external events as shown in figure 12.10.
123
Figure 12.10: Timers/counters with external input (at P3.4 or P3.5) configured in mode-1
Example 12.12: An object sensor is connected to T1 pin, write a program for counter 0 in mode 1 to count the
input pulses from the sensor and display the count value on the port 1 (lower byte) and port 2 (upper byte) .
Assuming that, a sensor gives a pulse for every object moving on the conveyor belt.
Solution:
MOV TMOD, #05H
; Initialize counter 0 in mode 1
MOV TH0, #00H
; Clear TH0
MOV TL0, #00H
; Clear TL0
SETB P3.5
; Configure P3.5 as input pin
L2: SETB TR0
; Start the counter
L1: MOV A, TL0
; Read TL0
MOV P1, A
; Display TL0 on port 1
MOV A, TH0
; Read TH0
MOV P2, A
; Display TH0 on port 2
JNB TF0, L1
; Repeat L1 until rollover when TF0 = 1
CLR TR0
; Stop the counter
CLR TF0
; Clear TF0
SJMP L2
; Repeat
8051
External input fed intoT1
P3.5
Port-1
Port-2
Display
124
timer will measure the time (in micro sec) for which the amplitude of pulse remains high that gives T on
value and same for Toff value. At last duty cycle is calculated using equation
125
REVIEW QUESTIONS
1. Write an assembly language program to generate a square wave of 1 KHz at port pin 1.5 using auto reload mode
of timer 0.
2. Draw the format of TMOD register and write the function of each bit.
3. Describe mode-0 of timer of the 8051 microcontroller.
4. Describe the difference between the timer and counter operation of the 8051 microcontroller.
5. Draw the hardware circuit diagram for timer / counter control logic and explain it.
6. Describe the TCON, TMOD SFR?
7. Assume XTAL=22 MHz, WAP to generate the pulse train of 2 seconds period on P2.4, Use time-1 in mode-1?
8. W.A.P to generate a Square wave of 50 % duty cycle on P1.5. Time-0 is used to generate the delay?
9. How do you program timer-0 in Mode-2?
10. How you will generate a pulse after every 2 ms using 12 MHz Crystal oscillator?
126
CHAPTER-13
8051 SERIAL COMMUNICATION, SPI, I2C AND USB INTERFACE
In digital data communication, ASCII (7-bits wide) or extend ASCII (8-bits wide) codes of characters (alpha-numeric
and special characters) are used for data transfer. The Computer controlled (programmed) data a transfer is primarily
divided into two ways: Parallel and serial data transmission. In parallel data transfer, the binary data transmits and
receives in group of n-bits simultaneously. A parallel port of the processor unit (MPU/DTE) sends and receives n- bits
of data at a time through n number of separate wires. This allows data to be transferred very quickly. Parallel ports
for parallel data transfers are used to connect a MPU/PC to a printer, memory, or peripheral devices like 8255. Parallel
ports of the MPU are easy to program and almost n-times faster compared to the serial ports. But main disadvantage
over long distance for n-bits parallel data transmission is it needs n number of transmission wires, n separate
amplifiers, related hardware and error handling mechanism. This result in complex circuitry and high wiring and other
hardware cost. Because of economical reason parallel ports are not used in long distance communications. Thus, serial
data transfer method is preferred for communication between long distance located Data terminal equipments (DTE)
or computers.
In serial data transfer, the binary data packet transmits and receives in bit by bit i.e., one bit at a time over single
wire with each bit having a specified length of time interval. A serial port of the processor unit (MPU/DTE) sends and
receives single bit of data at a time through a pair of wires (one wire for data and other for signal ground/reference).
The main advantage over parallel communication is that it is much economical although data transferring is n (bits)
times slower than parallel transfer, only a few wires are required. In fact, two-way (full duplex) communications is
possible with only three separate wires - one to send, one to receive, and a common signal ground wire. The
advantage of serial data transfer is to reduce number of pins in a package when speed is not important as ICs are
more expensive when they have more pins. Figure 13.1 shows the basic difference between working of parallel
transfer and serial transfer of data.
DTE
D0
(Data Terminal
Equipment/MPU)
D7
D0
DTE
(Data Terminal
Equipment/MPU)
DTE
DTE
(Data Terminal
Equipment/MPU)
(Data Terminal
Equipment/MPU)
D7
Parallel data transfer
Serial communication between two device can be simplex, half-duplex or full duplex. In simplex data
transmission, flow of data transfer only in one direction for example USB device, keyboard, mouse, radio, television
etc. In half-duplex transmission, the flow of data can be in both direction i.e., each DTE can transmit and receive, but
not at the same time. In other words, Data transfer can take place in either direction between two DTEs but only in
one direction at a time for example, walkie-talkies etc. In full duplex transmission, both DTEs can transmit and receive
data simultaneously for example telephone networks etc.
Within a processor unit data is transferred in parallel, it is converted to serial form (by using parallel to serial
converter/shift register/DCE) and then transmitted. On receiving end, serial data converted back in parallel form
(serial to parallel converter/shift register/DCE) and then transmitted to other microprocessor unit as shown in figure
13.2.
DTE
DCE
DCE
DTE
(Data Terminal
Equipment/
Processor unit)
(Data
communication
Equipment/
Modem)
(Data
communication
Equipment
/Modem)
(Data Terminal
Equipment/
Processor unit)
Telephone line
Figure 13.2: Binary data serial transmission between two Microcontroller based system
continuously send data packets/blocks to stay in synchronize. The start and end of data packet/block are identified
with specific bit patterns or bytes.
The synchronous transmitted character consists 5 to 8-bit, and a parity bit (optionally) like asynchronous transmitted
character, but unlike asynchronous format. The synchronous format consists Synch character and tail character
instead of start and stop bits. In the synchronous communication, a receiver and transmitter are synchronized by the
same clock control (as shown in figure 13.3)
In general, synchronous transmission is used where high data transmission is required (more than 20Kbits/second).
Transmitter
Tail
Character
D0-D7
Data N
..
.
D0-D7
Data 4
D0-D7
Data 3
D0-D7
Data 2
D0-D7
Data 1
Sync
Character
Sync
Character
Receiver
Clock
Figure 13.3: An arrangement for synchronous transmission
In Asynchronous transmission, each data character has a bit to identify its start, one or two bits to identify its end.
Since each character is individually identified. The character can be sent at any time. Here, Asynchronous means no
synchronization between transmitter and receiver, and thus does not require sending and receiving additional specific
Synch character or bits patterns. The start bit indicate when the data byte is about to begin and the stop bit(s)
indicate when it ends. The requirement to send these additional bits cause asynchronous communications to be
slightly slower than synchronous, however, it has the advantage that the processor does not have to deal with the
additional specific Synch bytes or bits patterns). In an asynchronous transmission, there is no problem in starting up
because the transmitter put a mark (high) on the communication channel until the transmission is ready to begin (as
shown in figure 13.4).
Mark (1)
D0
D1
D2
D3
D4
LSB
D5
D6
D7
MSB
Space (0)
.
Start bit
5 to 8 bit character
Parity bit
(Optional)
1, 11 2, or 2 Dead
stop bits
space
characters packet. For example, to frame the ASCII character A (7-bit binary 1000001) with no parity bit and one
stop bit for asynchronous serial data transfer (see figure 13.5). The framed sequence for ASCII character A is
010000011 (LSB is sent out first). The ASCII characters are 7-bits wide and extended ASCII characters 8-bits wide.
Start bit
LSB
MSB
Stop Bit
Dead Space
Besides the synchronization provided by the use of start and stop bits, an additional bit called a parity bit may
optionally be transmitted along with the data. A parity bit affords a small amount of error checking, to help detect
data corruption that might occur during transmission. In order to maintain data integrity in some secure applications,
a parity bit of the character (data bits) is included in the data frame i.e., a single bit is transmitted following the data
bits to indicate whether the number of 1s in the data is even or odd. However, the parity bit can be odd or even
depending on design of system. For odd parity bit system, the number of data bits, including the parity bit, has an
odd number of 1s. Similarly, in an even-parity bit system, the number of data bits, including the parity bit, has an
even number of 1s. For example, when the ASCII character for 8 (0111000 in binary) is transmitted in an even
parity system, the parity bit is set to 1, While in an odd parity system, the parity bit is set to 0.
Once the start bit has been sent, the transmitter sends the actual data bits. There may either be 5, 6, 7, or 8 data
bits, depending on the number you have selected. Both receiver and the transmitter must agree on the number of
data bits, as well as the baud rate. Almost all devices transmit data using either 7 or 8 (ASCII or Extended ASCII)
data bits.
Notice that when only 7 data bits are employed, you cannot send ASCII values greater than 127. Likewise, using 5
bits limits the highest possible value to 31. After the data has been transmitted, a stop bit is sent. A stop bit has a
value of or a mark state and it can be detected correctly even if the previous data bit also had a value of 1. This is
accomplished by the stop bit's duration.
The number of information bits, parity bits (present or not), the type of parity (even or odd), and the number of stop
bits may be changed from one sequence of characters to next, these parameters for sender and receiver remains
unchanged within a transmission. These parameters are programmable and can change by the program of control
register of the peripheral chips and MODEMs.
Table 13.1: Synchronous versus Asynchronous Transmission
PARAMETER
ASYNCHRONOUS
SYNCHRONOUS
Data Size
Data Transfer Speed
Framing information
Synchronization
Group of characters
Used
for
high
data
transfer
rates20Kbits/sec.
Sync character(s) is transmitted along with
each group of characters.
Sender and receiver must be synchronized
i.e. same clock for both
Smaller and can be reduce if number of
characters increases in a group of
characters.
Bit Overhead
Transmission type
Data Transfer Efficiency
NRZ, RZ, Walsh code, Manchester, 4B3T or HDB3 etc.). The bit rate is concern with one change of
one bit, while baud slightly more or less than one bit. As baud rate depends on the modulation
channel coding used. Since, there are many problems encountered in transmission of digital data
wires such as power dissipation, noise, and bandwidth. However, the bit rate (bps) and baud rate
can relate as given below:
Example 13.1: Draw the block diagram and describe to establish the telecommunication between two
microprocessor systems using RS232C through telephone line.
Solution: Digital data is delivered at the DTE (may be 8251 UART) in parallel form, which is then converted into serial
form and sent to DCE via RS-232 cable. The DCE (a modem) output is an audio signal carried through a telephone line.
At the receiving end side, the opposite process is carried out to retrieve the original data.
In a communication environment, two modems are usedone at the transmitting end side and one at the receiving end
side. Modems are generally called DCE (Data Communication Equipment). High frequency digital signals require a very
wide transmission channel bandwidth which makes the system very costly. However, existing telephone line facilities
(which carry analog signals in the range of 40 Hz to 4 KHz) can be used to transmit such high frequency digital signals. A
modem converts a digital signal into audio tone frequencies (at the transmitting end side) and reconverts this audio
frequencies into high frequency digital signals (at the receiving end side)and it utilizes Frequency Shift Keying (FSK) for
this purpose. Thus a modem converts a logical 1 to 1200 Hz and 0 to 2200 Hz audio frequency. These signals are then
transmitted over a telephone line over a carrier. The inverse operation is done at the receiving end side.
Since there would be voltage mismatch between RS-232 and microprocessor /microcontroller voltage
levels, we must use a voltage converter such as MAX 232 (other line driver like MC 1488 and 1489) to
convert the TTL/CMOS logic levels to the RS-232 voltage levels and vice versa. The RS-232 interfacing
with MAX-232 is discussed in next section.
The RS-232 standard does not define such elements as the character encoding or the framing of
characters, or error detection protocols. The standard does not define bit rates for transmission, except
that it says it is intended for bit rates lower than 20,000 bits per second. Many modern devices support
speeds of 115,200 bit/s and above. RS-232 makes no provision for power to peripheral devices.
Details of character format and transmission bit rate are controlled by the serial port hardware, often a
single integrated circuit called a UART that converts data from parallel to asynchronous start-stop serial
form. Details of voltage levels, slew rate, and short-circuit behavior are typically controlled by a line driver
(MAX-232) that converts from the UART's logic levels to RS-232 compatible signal levels, and a receiver
that converts from RS-232 compatible signal levels to the UART's logic levels.
based system or personal computer is a DTE device, while DCE devices are serial to parallel or parallel to
serial converter and/or modem. The function of DCE is to convert parallel data into serial data and convert
a binary signal into an analog signal to transmit over long distance wire. Since the normal wires have a
limited bandwidth, digital signal requires larger bandwidth cannot be transmitted directly. The RS-232
standard states that DTE devices use a 25/9-pin male connector, and DCE devices use a 25/9-pin female
connector. Therefore, we can connect a DTE device to a DCE using a straight pin-for-pin connection.
D-sub Connectors
D-Subminiature connectors are a family of plugs and sockets widely used in communications and
computer devices. For example, the common analog VGA (Video Graphics Array) interface for monitors
uses a D-sub 15-pin plug and socket.
The D-sub defines the physical structure (Alphabet D like shape) of the connector which indeed protect
from false plug-in connection, followed by a letter denoting the shell size (A=15 pins, B=25 pins, C=37
pins, D=50 pins, E=9 pins), followed by the actual number of pins, followed by the gender (M=male,
F=female). For example, DB-25M denotes a D-sub with a 25-pin shell size and M for male
connector. Possibly because the original PC used DB-25 connectors for the serial and parallel ports, it
seems that many people, not knowing the significance of the letter B as the shell size, began to call all
D-sub connectors DB connectors instead of specifying DA, DC or DE. When the PC serial port began
to use 9 pin connectors, they were often called DB-9 instead of DE. It is now common to see DE or DA
connectors sold as DB-9 or DB-15 connectors. Although, today the common designation for D-sub
connectors are "DB connectors," the international DIN 41625 standard defines them using the letter D
followed by A through E, with DB-25 being the only actual "DB" connector. The DIN designations are in
parentheses in the illustration below:
DB-9 (DE-9)
The male DB-9 connector (officially the DE-9) was typically used for the first serial port on earlier PCs
(COM1) as well as other communications devices. It is widely used for various RS-232 communication
systems.
DB-15 (DA-15 and DE-15)
Two DB-15 connectors are widely used. The larger, two-row female DA-15 is the game port on a PC, and
the smaller, three-row, female high-density DE-15 is the VGA port.
DB-25
The female DB-25 connector was widely used in the past for the printer port on a PC. The male DB-25 was
also the second serial port (COM2) on the PC when serial ports were popular. It is still widely used for
various RS-232 communications system.
Function
Group
Data
Control
Control
Control
7
8
9
10
11
12
13
14
15
Secondary
Timing
16
17
Secondary
Timing
18
19
20
21
22
Unassigned
Secondary Request to send
Data Terminal Ready (DTR) Outgoing handshaking signal
controlled by DTE
Signal quality detector
Ring Indicator (RI) Incoming signal from a modem
23
24
25
Unassigned
1
2
3
4
5
6
Control
Control
Data
Control
Secondary
Secondary
Secondary
Control
Control
Control
Control
Timing
Pin Number
1
2
3
4
5
6
7
8
9
25 Pin Connector
Pin 8 DCD
Pin 3 RD
Pin 2 TD
Pin 20 DTR
Pin 7 GND
Pin 6 DSR
Pin 4 RTS
Pin 5 CTS
Pin 22 RI
The data lines carry the most important signals. The received data and transmitted data lines permit fullduplex communication between the DTE and DCE. To make sure that there is no confusion on the
direction of data flow on the received data and transmitted data lines, the RS-232 standard specifies data
flow directions from the perspective of the DTE, outgoing data from the DTE to the DCE on the transmit
data line, and incoming data from the DCE to the DTE on the received data line.
Table 13.3: This is a standard 9 to 25 pin cable layouts for asynchronous data on a PC AT serial cable
Description
Carrier Detect
DCD
9-pin
DTE
1
Receive Data
RD
from Modem
Transmit Data
TD
from Terminal/Computer
DTR
20
SG
from Modem
DSR
from Modem
Request to Send
Clear to Send
RTS
CTS
7
8
4
5
from Terminal/Computer
from Modem
RI
22
Ring Indicator
Signal
25-pin
DCE
8
from
Terminal/Computer
from Modem
The control lines are used for handshaking, i.e. DTE /DCE can signal to the other DCE/DTE that there is
data to be transmitted .Six control lines are used most frequently to handshake between DTE and DCE:
1. Data Terminal Ready () from the DTE is another indication that the DTE is ready. If there is
something wrong with the terminal, this signal will not be activated. This signal can be used to
inform the DCE/modem that the DTE is alive and kicking. Its intended function is very similar to
the RTS line. DSR (Data Set Ready) is the companion to DTR in the same way that CTS is to RTS.
Some serial devices use DTR and DSR as signals to simply confirm that a device is connected and
is turned on. The DTR and DSR lines were originally designed to provide an alternate method of
hardware handshaking. It would be pointless to use both RTS/CTS and DTR/DSR for flow control
signals at the same time. Because of this, DTR and DSR are rarely used for flow control.
2. Data Set Ready () from DCE/modem to tell the DTE that DCE is ready to communicate and can
accept new data.
3. Request to Send () from the DTE (computer) signal to the DCE (modem) that the DTE has a
new data byte it would like to transfer. It is an active-low output from the DTE and an input to the
DCE. The DTE device puts this line in a mark condition to tell the remote device that it is ready and
able to receive data. If the DTE device is not able to receive data (typically because its receive
buffer is almost full), it will put this line in the space condition as a signal to the DCE to stop
sending data. When the DTE device is ready to receive more data (i.e. after data has been
removed from its receiver buffer), it will place this line back in the mark condition. The complement
of the RTS wire is CTS, which stands for Clear to Send. The DCE device puts this line in a mark
condition to tell the DTE device that it is ready to receive the data. Likewise, if the DCE device is
unable to receive data, it will place this line in the space condition. Together, these two lines make
up what is called RTS/CTS or "hardware" flow control. This line and the CTS line are used when
"hardware flow control" is enabled in both the DTE and DCE devices.
4. Clear to Send () from the DCE in response to , indicates to the DTE that the DCE can accept
new data. This input signal to the DTE is used by DTE to start the communication.
5. Data Carrier Detect () from DCE to inform the DTE that a valid carrier has been detected and
the contact is established a connection with another DCE/modem.
6. Ring Indicator (RI) from DCE (modem) to the DTE indicates that telephone is ringing. This signal
goes toggle
(repeatedly high and low) in synchronization to form ringing sound. This is the
least often used of the six control signals.
Using these handshake lines, the complete data transmission sequence is a series of repeated requests to
send new data byte, a handshake showing that the request can be honored, sending the data, a
handshake indication that new data cannot be accepted because either the DCE or the DTE is not ready or
the transmission link is unavailable, then waiting for the ready to accept or send signal and so on. The
other control lines let the DCE indicates to the DTE that DCE has detected a ringing signal, or that the
transmission line signal quality is acceptable, among other functions.
Cables and Null Modems
In a perfect world, all serial ports on every computer would be DTE devices with 25-pin male "D"
connectors. All other devices to would be DCE devices with 25-pin female connectors. This would allow
you to use a cable in which each pin on one end of the cable is connected to the same pin on the other
end. Unfortunately, we don't live in a perfect world. Serial ports use both 9 and 25 pins, many devices can
be configured as either DTE or DCE, and as in the case of many data collection devices - may use
completely non standard or proprietary pin-outs. Because of this lack of standardization, special cables
called null modem cables, gender changers and custom made cables are often required.
Cables Lengths
The RS-232C standard imposes a cable length limit of 50 feet. You can usually ignore this "standard",
since a cable can be as long as 10000 feet at baud rates up to 19200 if you use a high quality, well
shielded cable. The external environment has a large effect on lengths for unshielded cables. In electrically
noisy environments, even very short cables can pick up stray signals. The following chart offers some
reasonable guidelines for 24 gauge wire under typical conditions. You can greatly extend the cable length
by using additional devices like optical isolators and signal boosters. Optical isolators use LEDs and Photo
Diodes to isolate each line in a serial cable including the signal ground. Any electrical noise affects all lines
in the optically isolated cable equally - including the signal ground line. This causes the voltages on the
signal lines relative to the signal ground line to reflect the true voltage of the signal and thus canceling out
the effect of any noise signals. The rule of thumb for the length a data cable depends on speed of the
data, quality of the cable.
PC Baud Rate
110
300
1200
2400
4800
9600
19200
5000
4000
3000
2000
500
250
100
1000
1000
500
500
250
100
25
If you connect two DTE devices (or two DCE devices) using a straight RS232 cable, then the transmit line
on each device will be connected to the transmit line on the other device and the receive lines will likewise
be connected to each other. A Null Modem cable or Null Modem adapter simply crosses receive and
transmit lines so that transmitter on one end is connected to receiver on the other end and vice versa. In
addition to transmit and receive lines, handshaking lines such as DTR and DSR, and RTS and CTS are also
cross linked in a Null modem connection (see figure 13.9)
As shown in null MODEM wiring diagram 13.10, it requires only 3 wires (TD, RD and SG) to be wired
straight through thus is more cost effective to use with long cable runs. The theory of operation is
reasonably easy. The aim is to make to computer think it is talking to a modem rather than another
computer. Any data transmitted from the first computer must be received by the second thus TD is
connected to RD. The second computer must have the same set-up thus RD is connected to TD. Signal
Ground (SG) must also be connected so both grounds are common to each computer.
The original application of a null modem was to connect two teleprinter terminals directly without using
modems. As the RS-232 standard was adopted by other types of equipment, designers needed to decide
whether their devices would have DTE-like or DCE-like interfaces. When an application required that two
DTE's (or two DCE's) needed to communicate with each other, then a null modem was necessary. A Null
Modem is used to connect two DTE's together. This is commonly used as a cheap way to network games
or to transfer files between computers using Zmodem Protocol, Xmodem Protocol etc.
Loop Back Plug
This loopback plug can come in extremely useful when writing Serial / RS232 Communications Programs.
It has the receive and transmit lines connected together, so that anything transmitted out of the Serial
Port is immediately received by the same port. If we connect this to a Serial Port and write a Terminal
Program, anything we type will be immediately displayed on the screen.
The Data Terminal Ready is looped back to Data Set Ready and Carrier Detect on both computers. When
the Data Terminal Ready is asserted active, then the Data Set Ready and Carrier Detect immediately
become active. At this point the computer thinks the Virtual Modem to which
it is connected is ready and has detected the carrier of the other modem.
All left to worry about now is the Request to send and Clear to Send. As both
computers communicate together at the same speed, flow control is not
needed thus these two lines are also linked together on each computer.
When the computer wishes to send data, it asserts the Request to send high
and as it's hooked together with the Clear to Send, It immediately gets a
reply that it is ok to send and does so.
Notice that the ring indicator is not connected to anything of each end. This
line is only used to tell the computer that there is a ringing signal on the
phone line. As we don't have a modem connected to the phone line this is left
disconnected.
Figure 13.11: Loopback Plug Wiring Diagram
Voltage Converters
The types of driver ICs used in serial ports can be divided into three general categories:
Drivers which require plus (+) and minus (-) voltage power supplies such as the MC1488 series of
interface integrated circuits. (Most desktop and Power PCs use this type of driver.)
Low power drivers which require a +5 volt power supply. This type of driver has an internal charge
pump for voltage conversion such as MAX 232 interface. (Many industrial microprocessor controls
use this type of driver)
Low voltage (3.3 V) and low power drivers which meet the EIA-562 Standard. (Used on notebooks
and laptops)
1. MC1488 series
There are two types of voltage converters which are used to make compatible TTL/CMOS logic level with
RS-232 logic level. These are:
Figure 13.12: (a) MAX 232 pin diagram and (b) Inside MAX 232
The advantage of the MAX232 is that it powered by a +5V power source which is same as the power
supply for the processor. In other words, a single +5V power supply can power both processor and
MAX232, with no need for dual power supplies.
MAX232 voltage levels helpful to understand what occurs to the voltage levels. When a MAX232 IC
receives a TTL/CMOS level to convert, it changes TTL/CMOS logic 0 to between +3 and +15 V, and
changes TTL/CMOS logic 1 to between -3 to -15 V, and vice versa for converting from RS232 signals to
TTL/CMOS signals. This can be confusing when you realize that the RS232 data transmission voltages at a
certain logic state are opposite from the RS232 Control Line voltages at the same logic state. To clarify the
matter, see the table below:
+3 V to +15 V
0 V to +0.8V
-3 V to -15 V
2V to 5 V
-3 V to -15 V
2V to 5 V
+3 V to +15 V
0V
Bit
Bit address
Function
SM0
SM1
SM2
REN
TB8
RB8
TI
SCON.7 (9FH)
SCON.6 (9EH)
SCON.5 (9DH)
SCON.4 (9CH)
SCON.3 (9BH)
SCON.2 (9AH)
SCON.1 (99H)
RI
SCON.0 (98H)
Transmit interrupt flag, set when byte transmission is completed. Must be cleared by
software to send next data byte.
Receive interrupt flag, set when a byte in the serial buffer (SBUF) is completely
received. Must be cleared by software to receive next data byte.
The SM0 and SM1 bits of the SCON register are used to define the operating modes of the serial port as
describe in following table:
Table 13.4: Serial port (UART port) modes of operation
Description
Baud rate
Only 8 bits (LSB first) are transmitted/received: 8 data bits (LSB first).
Variable
1/32 (SMOD=1) or
1/64 (SMOD=0) the
oscillator frequency
Variable.
Serial port modes 0 and 2 have fixed baud rates while modes 1 and 3 the baud rate can be selected, a typical range is:
150; 300; 600; 1200; 2400; 4800; 9600; 19200; 38400.
Serial port modes 0 and 1 are used for connection between two devices, while modes 2 and 3 are used for master-slave
multiprocessor systems, in principle there could be one master microcontroller and up to 255 slave microcontrollers. In
mode 1 ten bits are used to specify an RS232 frame consisting of 1 start bit (logic 0), 8 data bits and 1 stop bit (logic 1).
For example the ASCII bit pattern 0100 0001 (hex 41) represents the character A and is transmitted as shown in figure
13.14; least significant bit (LSB) first.
In this book we will work on serial port mode-1 because of the mode-1 framing format is widely used and compatible with
the IBM PC then other three serial modes. Upon reset the SCON hold a value of 00H.
OR
Where SMOD bit is in PCON SFR. The SMOD bit is used to double the baud rate.
SMOD= 0 for serial mode 0.
SMOD= 0 for serial mode 1 and 3, will divide the machine cycle frequency by 32.
SMOD=1 for serial mode 1 and 3, will divide the machine cycle frequency by 16. Hence, doubles the baud rate.
SMOD=0 for serial mode 2, will divide the crystal frequency by 64.
SMOD=1 for serial mode 2, will divide the crystal frequency by 32. Hence, doubles the baud rate.
For mode 0 the baud rate is fixed at oscillator frequency/12. In the 8051 the baud rates in modes 1 and 3 are determined
by the timer 1 overflow rate and the value of SMOD as follows:
Using the above equations we can easily find the value of baud rate or the values to be loaded into TH1, and assuming an
oscillator frequency of 11.0592 MHz and UART mode 1 and SMOD=0, the TH1 values for baud rates of 19200, 9600,
2400, 1200, would be:
19200 TH1 = 254.5 or -2 (FEH)
9600 TH1 = 253 or -3 (FDH)
2400 TH1= 244 or -12 (F4H)
1200 TH1 = 232 or -24 (E8H)
The machine cycle frequency for the crystal frequency of 11.0952 MHz is 921.6 kHz. In serial mode 1, the UART is
divided it by 32 and gives 28,800 Hz before it is used by timer 1. The oscillator frequency and value in TH1 are decided to
generate the required range of baud rates. The following table show variously commonly used baud rates and how they
can be obtained from timer 1:
; Timer 1 mode 2
; Same as MOV TH1, # -3, Baud rate 9600
; Turn timer 1 on
; ASCII value of letter A into SBUF
; Stay here till TI set, wait until last bit of the data is transferred (polled operation)
; Clear TI to send next data byte
; Repeat
Example 13.3: Write a program to transfer serially a block of data bytes which is stored in internal RAM
addresses from 30H to 3FH continuously at baud rate 2400. Use polled operation.
Solution:
MOV TMOD, #20H
; Initialize timer 1 in mode 2 (8-bit autoreload timer)
MOV TH1, # -12
; Same as MOV TH1, #0FAH, initialize timer 1 for 2400 baud
MOV SCON, #50H
; Initialize serial port in mode 1
MOV R0, #30H
; Initialize RAM pointer
MOV R2, # 16
; Counter register load with 16
NEXT: MOV SBUF, @R0
; Load SBUF register with RAM data byte which is pointed by @R0
L1: JNB TI, L1
; Check TI to test whether data has been sent. (Polled operation)
CLR TI
; Clear TI for next byte
INC R0
; Increment RAM pointer
DJNZ R2, NEXT
; If R2 not zero send next data byte
END
Example 13.4: Write an assembly language program that repeatedly sends the line of text XUV serially at 9600
baud rate in mode 1 of serial port. Use polled operation.
Solution:
MOV SCON, #50H
; Serial mode 2, REN enable, TI and RI bits are disable
MOV TMOD, #20H
; Timer 1 mode 2
MOV TH1, #0FDH
; Baud rate 9600
SETB TR1
; start timer 1
L1: MOV A, # X
; Transfer first ASCII character X
ACALL SEND
; Call data send subroutine
MOV A, # U
; Transfer second ASCII character U
ACALL SEND
MOV A, # V
; Transfer third ASCII character V
ACALL SEND
SJMP L1
Serial port data transfer subroutine
SEND: MOV SBUF, A
L2: JNB TI, L2
CLR TI
RET
Example 13.5: Write a program to transmit a message REAL WORLD IS ANALOG which is stored in internal
ROM at the baud rate of 9600 for crystal frequency of 11.0592MHz.
Solution:
ORG 00H
MOV SCON, #40H
; Serial mode 2, REN, TI and RI bits are cleared
MOV TMOD, #20H
; Timer 1 mode 2
MOV TH1, #0FDH
; Baud rate 9600
SETB TR1
; Turn timer 1 on
MOV DPTR, #MSG17
; Initialize Data Pointer to message address
NEXTCH: MOV A, #0
; Clear A
MOVC A,@A + DPTR
; Get character into A from ROM
JZ L1
; Checking null character of message
ACALL SEND
; Send text character
INC DPTR
; Increment data pointer
SJMP NEXTCH
; Prepare to send next character
L1: END
SEND: MOV SBUF, A
; Send contents of A
; Text message
Example 13.6: Write an assembly program that receives an ASCII character into the serial buffer (SBUF) of the
UART and save this character in R7 and send on port 1. The serial port should be configured as mode 1. Used
polled operation.
Solution:
MOV SCON, #50H
; Mode 1, REN enabled
MOV TH1, #0FDH
; 9600 baud
MOV TMOD, #20H
; Timer 1 mode 2
SETB TR1
; Turn timer 1 on
L1: JNB RI, L1
; Check for received byte (polled operation)
CLR RI
; Clear RI
MOV A, SBUF
; Move character from buffer to A
MOV P1, A
; hex value onto port 1
MOV R7, A
; Save it in R7
END
Example 13.7: Draw an arrangement and write programs for appropriate baud rate to read the
temperature of a furnace at Delhi and monitor it at Mumbai. Use polled method.
Solution:
8051
Transmit
TxD
MAX-232
DB-9
Port 1
3
RS-232
Cable
RS
232
Port
2
MODEM
Telephone
Lines
Delhi
MODEM
RS
232
Port
2
RS-232
Cable
3
DB-9
2
8051/ PC
MAX-232
RxD/COM
Receive
Port 2
Display
Mumbai
Program for transmitter
MOV SCON, #40H
MOV TMOD, #20H
MOV TH1, #0FDH
SETB TR1
MOV A, #0FFH
MOV P1, A
L2: MOV A, P1
MOV SBUF, A
; Stay here till TI set, wait until data is transferred (polled operation)
; Clear TI to send next data byte
; Repeat
SMOD bit is used when setting the baud rate of the serial port. We use higher frequency crystal oscillator
or SMOD bit to increase the baud rate of data transfer. To double the baud rate without changing crystal
frequency, set SMOD bit to 1 as given below:
MOV A, PCON
SETB ACC.7
; Set D7 bit of A to 1
MOV PCON, A
#01H
PD is the Power Down bit, which also preserved the on-chip RAM and SFR values but saves the most
power by stopping the oscillator clock. However, the program is not dead. Port values are not changed/
overwritten in power down mode. The Power down Mode can be terminated (PCON.1 is cleared to 0) by
Hardware Reset only. The CPU starts from the next instruction where the Power down Mode was invoked.
The Power down Mode is enabled by setting the PD bit to 1 as given below:
ORL PCON,#02H
; Enables Power Down
Either mode can be terminated by an external reset signal as discussed below:
1. Activation of any enabled interrupt will clear PCON.0 bit and hence the Idle Mode is terminated. The
program goes to the Interrupt Service Routine (ISR). After RETI is executed at the end of the ISR, the
next instruction will start from the one following the instruction that enabled Idle Mode.
2. A hardware reset or power on reset terminates the Idle and Power Down modes.
Example 13.8: Repeat the example 13.2, to transfer ASCII character A at baud rate of 19200. Use polled operation.
Solution:
ORL PCON, # 80H
; Double baud rate by setting SMOD to 1
MOV SCON, #40H
; Serial mode 2; REN, TI and RI bits are disabled
MOV TMOD, #20H
; Timer 1 mode 2
MOV TH1, #0FDH
; Baud rate 9600
SETB TR1
; Turn timer 1 on
L2: MOV SBUF, #A
; ASCII value of letter A (A=41H) into SBUF
L1: JNB TI, L1
; Stay here till TI set, wait until data is transferred
CLR TI
; Clear TI to send next data byte
SJMP L2
; Repeat
A new form of inter-device communication becoming popular is the I2C (inter-integrated circuit) interface
created and popularized by Phillips. I2C is a serial format data link which uses two wires (one for data and
one for clock) and can have many drops to varying devices. Each device has its own ID address on the
link to which it will respond, data transfers are bi-directional, and the bus can have more than one master.
Phillips has been a leader in adding I2C capability to the 8051 microcontroller. Hardware wise, two I/O
pins are taken from port 1 for the I2C interface and a set of SFRs are added to control the I2C and aid in
implementing the protocol of this interface.
A wide assortment of ICs and processors are available with an IC interface used to transfer data serially to
other ICs. Like SPI, a serial interface has a hardware advantage in that it requires fewer pins and traces
on a PCB as long as the bandwidth is sufficient. An I2C bus has only two signal wires, SCL and SDA. SCL
functions as a clock line and SDA can function as a 1-bit serial data line or as a 1-bit serial address line. A
common ground is of course also required. The IC signal lines are open drain. One again, this means they
are only driven low and a single external pull up resistor pulls the line high (when no device is pulling it
low). With additional logic gates a tri-state output can simulate an open drain output by tri-stating its
output whenever the bit should go high. I2C devices are either masters or slaves. Slaves respond to
requests from the master. An I2C slave device is assigned a unique 7-bit I2C bus address. Since I2C has
address information, the bus protocol is more complex than SPI. Recall that SPI used chip select lines and
no addresses.
When a processor (master) needs to communicate with and I2C device (slave) it sends out a start
sequence. To stop an I2C sequence, the microprocessor sends out a start sequence. In figure 13.15, note
that a start sequence is the only time SDA goes high to low while SLC is high. Also note that a stop
sequence is the only time SDA goes low to high while SLC is high. This allows a special logic circuit to
detect start and stop. The processor drives the SCL clock lines to transfer each SDA serial bit. I2C devices
can drive SCL low to force a wait state. Typical clock rates range from 100 kHz to 400 kHz.
5. The processor serially clocks out the 7-bit I2C address of the slave with the R/W bit set High (i.e. read
operation).
6. The processor serially clocks in the 8-bit data value(s).
7. The processor sends a stop sequence.
It is possible to have multiple bus masters with collision detection in one of the I2C standards. Bus
arbitration is required. A collision occurs when two masters drive the bus at the same time. The bus
arbitration scheme determines which device can drive the bus.
Some I2C devices support a higher 3.4 MHz clock rate, expanded 10-bit addresses, programmable
addresses, and lower supply voltages. Many PC motherboards use the System Management Bus (SMB)
bus to measure temperature, fan speed, and voltage. SMB was developed by Intel in 1995 and is based
on I2C. I2C devices can also be found in new TVs, automobiles and many other consumer electronics.
The SPI and I2C standards both provide excellent support for communication with low-speed devices on
the same PCB. SPI is perhaps a better choice for applications that need to transfer higher bandwidth data
streams that do not require address information. Analog-to-digital (A/D) and digital-to-analog (D/A)
converters used to continuously sample or output analog signals are perhaps the most widely used SPI
devices. I2C requires addressing, so the hardware is more complicated but with current VLSI chip
technology these additional hardware costs are minimal.
This patented Philips method of serial data transmission uses two lines, one for a serial clock (SCL) and
the other for serial data (SDA). There are various microcontrollers in the Philips Semiconductors family
having I2C capability; the programs in this text are based on the P80C554 (a 8051 version from Philips).
The P89C66x pin 7 on port 1 is the SDA line and that pin 6 is the SCL line. When used for I2C these two
pins configure as open drain and it is necessary to have a pull-up resistor from each pin to 5 V, the
P89C664 board used 3.3 k resistors.
There are other microcontrollers belonging to the 8051 family that have I 2C SFRs, for example the
P87LPC764. The P87LPC764 microcontroller is designed to send and receive I 2C data as bits and requires
extra programming to group them into bytes. The class of microcontrollers to which the P89C664 belongs
sends and receives the data as bytes.
All I2C slave ICs have the ability to return Acknowledge (A) signals (active low) back to the Master IC
sending to them.
I2C has three modes; all 8-bit bidirectional, dependent on devices and clock speeds:
1. standard mode (up to 100 kbps (k bits per second))
2. fast mode (up to 400 kbps)
3. High-speed mode (up to 3.4Mbps).
There are four modes of operation:
1. master transmitter
2. master receiver
3. slave receiver
4. Slave transmitter.
Software support for SPI and I2C devices
Some general purpose microcontrollers and many USB microcontrollers include I2C and SPI interfaces.
Two or three bits on a GPIO port can be also used with the appropriate software driver to implement an
SPI or I2C interface. Using GPIO bits, the processor needs to generate all of the signals including the
clocks by toggling GPIO bits on an I/O port, so the software implementation approach requires more
processor effort.
The Universal Serial Bus (USB) 1.0 specification was released in 1996. USB 2.0 is a newer higher speed
standard that also supports USB 1.0 devices. As its name implies, USB is a serial bus that was designed to
support a wide range of peripherals. It transfers data in packets similar to a network, but since the
maximum length is limited to several feet it is technically considered an external bus and not a network.
USB cables contain a +5V power and ground connection and two twisted pair signal wires (D+, D-). The
two signal wires operate both in singled ended and in differential mode (one signal is subtracted from the
other). It uses a NRZI (non return to zero invert) encoding scheme that provides data along with a clock
sync field. Power supply drain on the bus is limited to 500mA.
USB supports three transfer rates, high speed (USB 2.0 only) is 480Mb/s, full speed 12Mb/s, and low
speed 1.5Mb/s. USB is host controlled and only one host is normally allowed per bus. The host is
responsible for initiating all transactions and scheduling bandwidth. Up to 127 different devices can be
connected on a single USB bus.
USB is designed to be hot pluggable. If you look into the end of a USB connector you will notice that the
outer power and ground pins are longer than the two inner signal pins. When a connector is plugged in the
power and ground are connected before the signal lines are connected. If signal wires were connected
before a common ground was established, it could damage the device.
REVIEW QUESTIONS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
8051
UART
F
MAX-232
(Driver)
RS-232
Port
MODEM
(DCE)
RS-232
Cable
Telephone line
8051
MODEM
(DCE)
RS-232
Port
MAX-232
(Driver)
RS-232
Cable
UART
CHAPTER-14
THE 8051 INTERRUPTS
An interrupt is an external (by an interrupt driven I/O device) or internal event that interrupts
microcontroller to inform it that a device needs its service. When an interrupt is accepted, and if
microcontroller transfers execution control to a specific address defined by the manufacturer then
interrupt is called vectored interrupt.
In non-vectored interrupt, there is no specific address for storing the interrupt service routine. However,
interrupted device should give the address of the interrupt service routine.
the
the
the
the
Let understand the basics of Interrupt and its service (Interrupt Service Routine ISR); we can take an
example of a class room. A subject teacher is busy in delivering a lecture in the class room; it is analogous
to the microcontroller is busy in executing of main program. Suppose that a student is come in middle of the
lecture in the class and ask to the teacher may I come in sir while teacher is busy in delivering lecture, it is
analogues to interrupt and interrupting the microcontroller. The teacher suspends the lecture and gives the
permission to attend the class or denial, its analogues to microcontroller gives the service of that device.
I/O device-3
I/O device-1
Service
Cycle
I/O device-4
Interrupt: An interrupt is triggered by an event that is not associated to the main program and calls a
special subroutine, referred to as an interrupt service routine (ISR) that transfers the data. This on-demand
processing is more efficient when data rates are relatively slow or unpredictable.
Whenever any I/O device needs its service (read/write data from/into the microcontroller according to
application of the devices), the I/O device notify to the microcontroller by issuing an interrupt signal. Upon
getting an interrupt signal the microcontroller suspends the current activity and service to the device. The
microcontroller serves the device according to a written program which is associated with the interrupt driven
device, called the interrupt service routine (ISR). In this way, the microcontroller can do other task.
147
An interrupt signal from the I/O device is an event that stops the current processing of the microcontroller so
that the microcontroller can attend the task needing completion because of the event. In data handling, an
interrupt indicates data can be read or written to a device.
Table 14.1: Interrupt versus Polling
Interrupts
Polling
Interrupt
Flag bit
ROM location
Active
Bytes
Priority
Hardware Reset
Hardware Interrupt 0 (I NT0)
Timer 0 Interrupt
Hardware Interrupt 0 (I NT0)
Timer 1 Interrupt
Serial port Interrupt
Timer 2 Interrupt (8052/32)
-IE0
TF0
IE1
TF1
TI and RI
TF2
0000H
0003H
000BH
0013H
001BH
0023H
002BH
External (pin 9)
External (Pin 12)
Internal
External (Pin 13)
Internal
Internal
Internal
3
8
8
8
8
8
8
1
2
3
4
5
6
7
When any interrupt is activated, the Program Counter (PC) holds the corresponding address location as given
in above table. In other words, when an interrupt is invoked, the microcontroller program execution control
transfer to respective ROM location. If two or more interrupt occurs at the same time, the microcontroller
accepts one interrupt, the one which has highest priority among them and executes its ISR; then, accept just
lower priority interrupt and so on.
Note: When we are dealing with interrupts, it is mandatory that assembly language programs started from
address 0033H ( 0040H) in order to leave the interrupt vectors as a reserved space. See the following
example:
ORG 0000H
; Reset address
SJMP MAIN
; Short jump to by-pass interrupt reserved space
ORG 0040H
; Main program starts at 40H of program memory location
MAIN:
END
From the above table, only 3 bytes of ROM space are assigned for the Reset. Only a jump instruction (SJMP
or LJMP) can be fitted into available 3 bytes. Therefore, in above program we place a jump instruction to bypass reserved space.
The address given is the starting address of the relevant interrupt subroutine. If the routine cannot be fitted
into the available 8 bytes, a jump instruction should route the ISR elsewhere in program memory.
External hardware Reset (RST) interrupt has highest priority, but it disables all other interrupts. Reset
interrupt cannot be disabled (unmaskable). Therefore, this interrupt is not used for interrupt driven I/O
programming and multiple interrupts environment, this is why RESET interrupt is not considered as an
interrupt by the many manufacturers. A reset is accomplished by holding the RST pin high for at least two
machine cycles. This is the power-on reset interrupt and discussed in chapter-4. Therefore, we are not
focused on it in this chapter.
Two of the interrupts are triggered by external signals via I NT0 and I NT1 while the remaining interrupts are
generated by internal operations; timer 0, timer 1and the ORed output of RI and TI. The external interrupts
148
could be negative edge triggered or low level triggered except reset. All of the bits that generate interrupts
can be set or cleared by software.
ENABLING AND DISABLING OF INTERRUPTS
The 8051 has a power on reset. When the microcontroller is power up, all interrupts are disabled (masked).
This means that even if they are invoked, none of them will be serving by the microcontroller. For example,
the TF0 bit is set; the 8051 will not execute the interrupt. Assembly program must specifically tell the 8051
to enable interrupts and specifically which interrupts it wishes to enable. Each of maskable interrupt sources
can be enabled/disabled by the setting/clearing of a bit in the IE (Interrupt Enable) SFR (byte address A8H).
Interrupts can be enabled or disabled individually by using the bit addresses of the individual bits of the IE
register. However, the EA (IE.7 bit) flag must be set to 1 to enable interrupts either individually or globally
(all interrupts at the same time). If EA=1, interrupts are enabled and will be served to if their relative bits in
the IE are set to 1. If EA=0, no interrupt will be served, even if all the other bits of the IE are set. This
register, details of which are shown below, also has a global disable bit EA which disables all interrupts at
once.
149
TIMER INTERRUPTS
Timer interrupts can be made to occur when the TF is set at rollover. This is achieved by setting the relative
bits in the interrupt enable (IE) registers as discussed above. In chapter 12, we are used JNB TF, label
address instruction to check TF bit until it is high. It was a polling method and a lot of microcontroller time is
wasted if the TF is not high shortly after the polling begins. This problem is removed by application of timer
interrupt.
When a timer/counter overflows the corresponding timer flag TF0 or TF1 is set to 1. The flag is cleared by
on-chip hardware when the service routine is served. The structure of timer interrupts shown in figure 14.2,
if the timer interrupt in the IE register is enabled, whenever the timer rollover, TF is set to high, and
microcontroller is interrupted. When the microcontroller is interrupted, it suspends current activities and
jumps to the interrupt vector location to serve interrupts ISR. If the interrupt being handled is a timer or
external interrupt, the microcontroller automatically clears the interrupt flag before passing control to the
interrupt handler routine. Therefore, it is not necessary to clear the bit in the program.
Example 14.2: Write a program to display data from port 2 on port 0 continuously and
simultaneously generate a square wave of frequency 10 kHz on the P1.7, using timer 1 interrupt.
Solution: Assume the clock frequency applied to the counter is 1MHz, so that counter is incremented every
1s. to generate a square wave of 10KHz, the port pin should be toggled after every 50 s. the counter is
loaded with the count value of 50 to generate 50 s delay. The timer is initialized in mode 2 (auto reloaded).
ORG 00 00
; Reset address
SJMP MAIN
; Short jump over reserved area
Interrupt service routine (ISR) for timer 1
ORG 001BH
; Timer 1 interrupt vector address
TASK: CPL P1.7
; Complement (i.e. toggle) pin 7 port 1
RETI
; Return from ISR
Main program
ORG 40H
; Program start address at 0040H
MAIN: MOV TMOD, #02H
; Put Timer 0 into mode 2
MOV TH0, #-50
; Auto-reload base count into TH0
MOV P2, #0FFH
; Make P2 an input port
SETB EA
; Enable all
SETB ET1
; Enable Timer 1 interrupt
SETB TR1
; Turn Timer 1 on
AGAIN: MOV A, P2
; Read port 2
MOV P0, A
; Send it to P0
SJMP AGAIN
; Stay here till interrupt occurs
A RETI instruction at the end of the service routine restores the address reached by the PC prior to the interrupt back to the
PC and resets the interrupt logic so that another interrupt, should it occur, can be serviced.
150
Example 14.3: Write a program to generate a square wave of frequency 5 kHz on the P1.7, using
timer 0 interrupt. Assume crystal frequency is 11.0592 MHz.
Solution:
The timer 0 interrupt is used to toggle the logic level on pin 7 port 1 (switched to opposite logic level).
ORG 00
; Reset address
SJMP START
; Short jump over reserved area
ORG 0BH
SJMP TASK
ORG 40H
START: MOV TMOD, #02H
MOV TH0, #A4H
SETB EA
SETB ET0
SETB TR0
AGAIN: SJMP AGAIN
EXTERNAL INTERRUPTS
In the 8051, there are only two external hardware interrupts: INT0 (pin 3.2) and INT1 (pin 3.3). The
interrupt vector locations 0003H and 0013H are assigned for INT0 and INT1, respectively. If we want to
enable the two external interrupts we would use the instruction:
MOV IE, #10000101B
The external interrupts INT0 and INT1 can be level activated or transition activated depending on the value
of the bits IT0 and IT1 in the TCON register. The interrupts are actually generated by the flags IE0 and IE1 in
TCON. Therefore, each of the two external interrupt sources can be defined to trigger on the external signal,
either on a negative going edge or on a logic low level state.
The negative edge trigger is usually preferred as the interrupt flag is automatically cleared by hardware. Any
level-activated interrupt must be reset by the programmer when the interrupt is serviced by the service
subroutine. The low level must be removed from the external circuit before a RETI instruction is executed
151
otherwise an immediate interrupt will occur after the execution of the RETI instruction. Two bits in the TCON
register are used to define the trigger operation. The TCON register is another SFR register and is located at
location 88H in internal RAM.
The eight bits of the TCON register are duplicated pairs of four as shown in following table:
To define negative edge triggering for the two external interrupts use instructions as follows:
SETB IT0
; Negative edge trigger for interrupt 0
SETB IT1
; Negative edge trigger for interrupt 1
Assumed that the main program, is executing when the external interrupt INT0 occurs. The 8051 hardware
will automatically complete the current instruction and save the Program Counter to the stack. The IE
register is also saved to the stack. The IE0 flag is disabled (cleared) so that another INT0 interrupt will be
inhibited while the current interrupt is being serviced. The Program Counter is now loaded with the vector
location 0003H. This vector address is a predefined address for interrupt INT0 so that program execution will
always trap to this address when an INT0 interrupt occurs. Other interrupt sources have uniquely defined
vector addresses for this purpose. The set of these vector addresses is referred to as the interrupt vector
location table.
Program execution is now transferred to address location 0003H. In the given examples a LJMP instruction is
programmed at this address to cause the program to jump to a predefined start address location for the
relevant ISR (Interrupt Service Routine) routine. The ISR routine is a user written routine, which defines
what action is to occur following the interrupt event. It is good practice to save (PUSH) to the stack any
registers used during the ISR routine and to restore (POP) these registers at the end of the ISR routine, thus
preserving the registers contents, just like a register is preserved within a subroutine program. The last
instruction in the ISR routine is a RETI (RETurn from Interrupt) instruction and this instruction causes the
8051 to restore the IE register values, enable the INT0 flag, and restore the Program Counter contents from
the stack.
Since the Program Counter now contains the address of the next instruction which was to be executed before
the INT0 interrupt occurred, the main program continues as if it had never being interrupted. Thus only the
temporal behavior of the interrupted program has been affected by the interrupt; the logic of the program
has not been otherwise affected.
Low-level and edge triggered interrupt handling
The interrupt flags are sampled at every instruction cycle. The samples are polled during the next machine
cycle (or instruction cycle). For the low-level-triggered interrupt, the activation of the external hardware
interrupt at the pin I NTx, the duration of the low-level signal is around 4 machine cycles due to low level
triggered interrupt is not latched. For the edge-triggered interrupts, the external source be held high and
then low for at least one machine cycle to ensure transition is detected by the microcontroller.
152
The external interrupts could be negative edge triggered or low level triggered. All these interrupt, when
activated, set the corresponding interrupt flags. Except for serial interrupt, the interrupt flags are cleared
when the processor transfer program control to the Interrupt Service Routine (ISR). The external interrupt
flags are cleared on branching to Interrupt Service Routine (ISR), provided the interrupt is negative edge
triggered. For low level triggered external interrupt as well as for serial interrupt, the corresponding flags
have to be cleared by software by the programmer.
Example 14.4: The 8051 microcontroller has an oscillator frequency of 11.0592 MHz. Write an assembly language
program that complements the logic level on port 1 pin 7 when an edge triggered interrupt occurs on pin 3 of port 3
(INT1).
Solution:
Figure 14.4 shows a switch circuit where the voltage on P3.3 (port 3 pin 3) is normally 5 V. Pressing the switch causes a
negative edge transition as the voltage switches down from 5V to 0 V. If the switch is pressed and held then a logic 0 level is
held on P3.3. These are the two external interrupt conditions; it can be either edge triggered (transition logic 1 to 0) or level
triggered (logic 0).
The four least significant bits of the TCON register are used to set the external interrupt parameters. IT1=1 INT1 (P3.3)
interrupt activated on a negative edge transition. IE1 flag set to 1 when there is a negative edge transition on INT1 (P3.3),
cleared automatically when servicing the interrupt. IT1=0 INT1 (P3.3) interrupt activated on logic 0 level. IE1 flag set to 1
when there is a logic 0 level on INT1 (P3.3), cleared when the logic level on P3.3 goes back to logic 1. The process for IT0
and IE0 is similar to the above.
ORG 0000
; Reset address
SJMP MAIN
; Jump over reserved area
ORG 0013H
; INT1 address vector
SJMP KEY
; Jump to interrupt routine
ORG 40H
; Program start address
MAIN: SETB IT1
; Interrupt edge triggered
SETB EA
; Enable all set interrupts
SETB EX1
; Enable INT1 interrupt
L1: SJMP L1
; Stay here till interrupt
Interrupt service routine
KEY: CPL P1.7
; Interrupt task
RETI
; Return from interrupt
END
; No more assembly language
Example 14.5: Assume a microcontroller connects with a temperature sensor as shown in figure 14.5. When
temperature goes above to maximum limit, a buzzer which is connected to an output port 1 (P1.1) must be on in
order to indicate the temperature is above maximum limit. Also other task simultaneously performed, is to generate
a square wave on pin 2 of port 1 (P1.2) continuously.
Solution:
These two tasks can be implemented by using 8051 microcontroller system. The first task can be implemented by the help of
an external interrupt, choose one interrupt input (assume INT0) to send information that whether the temperature exceeds
the maximum limit or not. If temperature below to the maximum limit, sensor send a high level signal to the P3.3. If the
temperature above to the maximum specified limit, sensor send a low level signal to P3.3. The second task is that to
generate square wave continuously; therefore, implement it as a main program. Suppose that main program (square wave
generator) interrupted (temp. above max. limit) at during execution of ACALL delay instruction. Microcontroller completes
current instruction (ACALL) execution; then program control transfer to the corresponding ISR, which is turn on the buzzer
153
for a specified time. After that, it return to the main program (square wave generator) and execution will start at SJMP AGAIN
instruction.
ORG 00
; Reset address
SJMP START
; Short jump over reserved area
Assume that an
interrupt occurs
here
ORG 0003H
SJMP TASK
ORG 40H
START: MOV TMOD, #02H
MOV TH0, #A4H
SETB EA
SETB IE.0
SETB TR0
AGAIN: CPL P1.2
ACALL DELAY
SJMP AGAIN
Buzzer
8051
P1.1
Signal
conditioner
interrupt
INT0
P1.2
Temperature
sensor
Figure 14.5: Temprature sensor and buzzer configuration for example 14.5
154
In below flow chart, you can understand the all steps when an interrupt occurs.
Main program
Enable
Interrupt
Interrupt received
Here
-
BODY of ISR
(Executing ISR program, which is a different task from main program)
155
Example 14.6: Figure 14.7 shows and oven control system where a heating oven, as part of a manufacturing
process, is to be controlled within the temperature range, between 190C and 200C. An 8051 microcomputer based
system is used to control the temperature. The oven has two built-in temperature sensors. The low threshold sensor
outputs a logic 0 if the temperature is below 190C, otherwise it outputs a logic high level (say 5 volts). The high
threshold sensor outputs a logic low level if the temperature exceeds 200C, otherwise it outputs a logic high level.
The temperature sensors are connected to the 8051s interrupt inputs, I NT0 and I NT1, as shown in the diagram. Both
of these interrupt inputs are set to trigger at negative voltage transitions. The microcomputer outputs a logic 1 on
the P1.0 output pin to turn on the heater element and it outputs a logic 0 to turn off the heating element. Assume the
necessary hardware driver circuitry, to switch power to the oven, is included in the oven.
Three vector locations are defined at the beginning of the program. The RESET vector, at address 0000H,
contains a jump instruction to the MAIN program. Location 0003H is the vector location for external interrupt
0, and this contains a jump instruction to the relevant ISR routine, ISR0. External interrupt 1uses the vector
location 0013H which contains a jump instruction to the ISR routine, ISR1. In this oven control program
example the main program just loops around doing nothing. When an interrupt occurs, the required action is
carried out by the relevant ISR routine. However, in a more sophisticated program the main program could
be doing something very useful and would be interrupted only when the oven temperature needs to be
adjusted, on or off. Thus the main program does not have to waste time polling the sensor inputs.
ORG 0000
; Entry address for 8051 RESET
LJMP MAIN
; MAIN starts beyond interrupt vector space
ORG 0003H
; Vector address for interrupt 0
LJMP ISR0
; Jump to start of ISR0
ORG 0013H
; Vector address for interrupt 1
156
LJMP ISR1
ORG 0040H
MAIN: MOV IE, #10000101B
SETB IT0
SETB IT1
SETB P1.0
L1: SJMP L1
INTERNAL INTERRUPTS
The serial port interrupt is generated by the logical OR of RI (set to 1 in the SCON register when a data byte is received) and
TI (set to 1 in the SCON register when a data byte has been transmitted). This is achieved by setting the relative bit
(ES or IE0.4) in the interrupt enable (IE) registers (see the structure of serial interrupts in figure 14.9).
Neither flag is cleared by hardware when vectoring to the service routine.
Serial Interrupts are slightly different than the rest of the interrupts. This is due to the fact that there are two
interrupt flags: RI and TI. If either flag is set, a serial interrupt is triggered.
Interrupt driven data transmission
In 8051, when a character is transmitted, SBUF register becomes empty and this generates a serial port
interrupt (TI). TI and RI both point to the vector location 0023H in the program memory. An interrupt service
routine can be written at 0023H to send the next character.
Interrupt driven data reception
When a character is received, if receive mode is enabled, RI flag is set. This leads to the interruption of the
main program and the processor goes to the interrupt vector location, i.e. 0023H for serial port. The
interrupt service routine at 0023H gets executed to read the character so that the next character can be
received.
This means that when serial interrupt is executed, it may have been triggered because the RI flag was set or
because the TI flag was set or because both flags were set. Thus, Interrupt service routine must check the
status of these flags to determine what action is appropriate. Also, since the 8051 does not automatically
clear the RI and TI flags the programmer must clear these bits in ISR. See the following program for a
duplex communication:
CHECK_RI: JNB RI, CHECK_TI
; If the RI flag is not set, jump to check TI
MOV A, SBUF
; If RI is set, Read received data from the SBUF
CLR RI
; Clear the RI bit to receive another character
CHECK_TI: JNB TI, EXIT
; If the TI flag is not set, jump to the exit
CLR TI
; Clear the TI bit before we send another character
MOV SBUF, # A
; Send next data byte to the serial port
EXIT: RETI
Microcontroller checks the status of both interrupts flags. If both flags were set, both sections of code will be executed. Also
note that each section of code clears its corresponding interrupt flag. If programmer forgets to clear the interrupt bits, the
serial interrupt will be executed over and over until you clear the bit. Thus it is very important that programmer always clear
the interrupt flags in a serial interrupt.
157
Example 14.7: Write a program to receive a character from the serial port using interrupt driven method and save it
in R3. While the 8051 is continuously reading from port 1 and display it on port 2. Use 8-bit data, 1 start and stop bit
at 9600 baud rate.
Solution: When a character is received from the serial port, the ISR saves the received byte in R3.
ORG 0000
; Entry address for 8051 RESET
LJMP MAIN
; MAIN starts beyond interrupt vector space
ORG 0023H
; Vector address for serial interrupts
LJMP SERIAL
; Jump to start of SERIAL
ORG 0040H
MAIN: MOV IE, #10010000B
MOV TMOD, # 20H
MOV TH1, # #0FDH
MOV SCON, #50H
SETB TRI
L1: MOV A, P1
MOV P2, A
SJMP L1
158
Example 14.9: Write a program to read port 1 and transfer it serially at baud rate 9600. Assume the 8051
microcontroller has an oscillator frequency of 11.0592MHz. Using timer 1 and configuring the UART port in mode 1.
Solution:
ORG 0000
; Entry address for 8051 RESET
LJMP MAIN
; MAIN starts beyond interrupt vector space
ORG 0023H
; Vector address for serial interrupts
LJMP SERIAL
; Jump to start of SERIAL
ORG 0040H
; Defines where MAIN starts
MAIN: MOV SCON, #40H
; Serial mode 2; REN is disabled, TI and RI bits are cleared
MOV TMOD, #20H
; Timer 1 mode 2
MOV TH1, #0FDH
; Same as MOV TH1, # -3, Baud rate 9600
MOV P1, #0FFH
; Configure port 1 as input port
MOV IE, #10010000B
; Enable serial interrupt
SETB TR1
; Turn timer 1 on
AGAIN: MOV A, P1
; Read port 1
MOV SBUF, A
; Send it serially
ACALL DEALY
; Wait for transfer
SJMP AGAIN
; Continuous send
Interrupt service routine for serial data reception (SERIAL)
ORG 0100H
SERIAL: JNB RI, CHECK_TI
; If the RI flag is not set, jump to check TI
CLR RI
; Clear the RI bit to receive another character
CHECK_TI: JB TI, EXIT
; If the TI flag is set, jump to the exit
RETI
; If TI is not set Return from ISR
EXIT: CLR TI
; Clear the TI bit before we send another character
RETI
Delay Subroutine for wait for data transmission
DELAY: MOV R2, #0FFH
BACK: DJNZ R2, BACK
RET
Interrupt
External 0
External 1
Timer 0
Timer 1
Serial port
Flag bit
IE0
IE1
TF0
TF1
TI and RI
Priority
1
2
3
4
5
The interrupt flags are accessible as flags on the IE, TCON and SCON registers as given in figure:
159
Program Memory
Interrupt Priorities
The 8051 offers two levels of interrupt priority: high and low. By using interrupt priorities programmer may assign higher
priority to certain interrupt conditions. For example, programmer may have enabled Timer 1 Interrupt which is automatically
called every time Timer 1 overflows. Additionally, programmer may have enabled the Serial Interrupt which is called every
time a character is received via the serial port. However, programmer may consider that receiving a character is much more
important than the timer interrupt. In this case, if Timer 1 Interrupt is already executing programmer may wish that the serial
interrupt itself interrupts the Timer 1 Interrupt. When the serial interrupt is complete, control passes back to Timer 1 Interrupt
and finally back to the main program. Programmer may accomplish this by assigning a high priority to the Serial Interrupt and
a low priority to the Timer 1 Interrupt. Interrupt priorities are controlled by the IP SFR (B8H). The IP SFR has the following
format:
160
Interrupted here
(low priority interrupt)
ISR_1
ISR_2
RETI
RETI
MAIN PROGRAM
Figure 14.11: Program execution flow for interrupt inside an interrupt
161
Example 14.11: Discuss the sequence in which the interrupt are serviced if the interrupt priority is set by the
instruction MOV IP, # 00001000B.
Solution: The given instruction will set the timer 1 (TF1) to a higher priority. That means timer 1 has highest
priority compared with the rest of the interrupt. Rest of the interrupt will be polled according to the polling
sequence. Therefore, the following sequence of interrupts will be served by the microcontroller:
1. Timer 1 Interrupt
2. External 0 Interrupt
3. Timer 0 Interrupt
4. External 1 Interrupt
5. Serial Interrupt
Example 14.12: Write an instruction to assign highest priority to serial interrupts.
Solution:
MOV IP, #00010000B or SETB IP.4 is used to assign serial interrupts highest priority. Therefore, the
following sequence of interrupts will be served by the microcontroller:
1. Serial Interrupt
2. External 0 Interrupt
3. Timer 0 Interrupt
4. External 1 Interrupt
5. Timer 1 Interrupt
Example 14.13: Draw an arrangement to connect the 8051 with a smoke sensor and a temperature sensor in an
office. Write a program and assign priority to perform following tasks:
1. If there a smoke in office, turn on Alarm
2. If office temperature goes above 70C, turn on water pump motor.
3. Otherwise, keep monitoring
Solution: If there is smoke in office, it may be happens due to fire or someone smoking in office. If office
temperature goes beyond the 70C, there must be a fire. Therefore, fire sensor should be assigned with
highest priority than smoke sensor. See the figure for the arrangement:
ORG 0000
LJMP MAIN
ORG 0003H
LJMP ISR0
ORG 0013H
LJMP ISR1
ORG 0040H
MAIN: MOV IE, #10000101B
MOV IP, #00000101B
SETB IT0
SETB IT1
L1: SJMP L1
162
RETI
; Return from interrupt
Interrupt service routine to turns on alarm (ISR1)
ISR1: SETB P1.0
; Turn ON alarm
RETI
; Return from interrupt
END
; End of program
To turn off water pump motor or alarm, apply Reset signal to the 8051.
INTERRUPT LATENCY
The 8051 samples the interrupt flags once every processor cycle to determine if any interrupts are pending. An interrupt is
requested by the appropriate signal being set for the processor core to recognize in its next sampling period. Thus, the time
between an interrupt being requested and recognized by the processor is one instruction cycle. At this point, the hardware
will generate a call to the interrupt service routine in the vector which takes two cycles. Thus, the overall process takes three
cycles total. Under ideal conditions (where nothing is blocking the interrupt call) and no instruction is in the works, an interrupt
will be responded to in three instruction cycles. This response time is excellent and provides the user with very fast response
time to system events. There will inevitably be times that an interrupt is not responded to within the three cycles discussed
above. The most significant of these is when an interrupt of equal or higher priority is being serviced. In this case, the latency
to service the pending interrupt depends entirely on the ISR currently being executed.
Another situation in which the latency will be more than three cycles occurs when the processor is executing a multi-cycle
instruction and detects a pending interrupt during this instruction. The pending interrupt will not be serviced until the current
instruction is completed. This situation will add a minimum of one cycle to the latency (assuming that a two cycle instruction
such as a MOVX is executing) to a maximum of three cycles (assuming the interrupt is detected after the first cycle of a
MUL). The maximum condition gives a worst case latency of six instruction cycles (the three cycles due to the architecture
itself and the three cycles due to the completion of the instruction) when the pending interrupt is not blocked by a currently
executing interrupt. The final case in which an interrupt will not be vectored to in three cycles is when the interrupt was
recognized during a write to IE, IP, or during a RETI (return from interrupt) instruction. This prevents very odd real time
conditions from occurring in your system unexpectedly.
REVIEW QUESTIONS
1. What are the functions of IE, SCON, PCON and IP?
2. What is an interrupt?
3. When an interrupt is called control is given to:
163
CHAPTER -15
DATA CONVERTERS AND INTERFACING
Most of the real world physical quantities such as voltage, current, temperature, pressure, time, mass, sound etc. are
available in analog form. Non-electrical physical quantities like pressure, temperature, sound, pressure etc. are
represented by equivalent electrical quantity called analog electrical signals by using electrical sensor or transducers.
On the other hand, microcontroller is a digital device i.e. microcontroller process digital (binary encoded) signals. Even
though an analog signal represents a real physical parameter with accuracy, but it is difficult to process, store or transmit
of the analog signals without introducing considerable error. Digital signal does not have such problems. Therefore, in
microcontroller based control/monitoring systems, it is necessary to translate an analog signal into digital signal and digital
signal back into analog signal.
Figure 15.1 shows a typical application in which analog to digital and digital to analog signal conversion is used. The
analog signal obtained from the transducer. The most common transducers produce an output in the form of voltage,
current, capacitance, and resistance. However, we need to convert these signals to voltage in order to send analog
Physical quantity
Analog signal
Sensor or
transducer
Plant
Analog
Signal
Smoothing
filter
Digital signal
Signal
conditioning
A/D
converter
Staircase signal
D/A
converter
Microcontroller
Digital
signal
voltage input to an analog to digital converter (ADC) device. This conversion (modification) is commonly called signal
conditioning. However, signal conditioning can be current to voltage conversion, signal amplification, signal clipping,
signal clamping or use to make band limited signal by use a low pass filter. For example, a thermister changes resistance
with temperature. The change in resistance must be translated into voltage in order to be use as an input of ADC. The
output of signal conditioning block has to be held constant while conversion is taking place in ADC (analog to digital
converter). This requires that ADC should be preceded by a hold circuit (sample and hold circuit) which is the part of
signal conditioning block. The ADC output is a binary sequence (digital signal). The microcontroller performs the
numerical calculation on the digital signal by use of an appropriate control algorithm. The DAC (digital to analog converter)
is to convert digital signal into analog and hence the function of DAC is exactly opposite to that of ADC. The DAC is
usually have the same conversion time as the ADC. The output of a DAC is commonly a staircase. This staircase like
analog output is passed through a smoothing filter to remove the effect of quantization.
Both ADC and DAC are also known as data converters and are available in monolithic IC form. Some ICs are specially
designed to be compatible with the microcontroller. Typical applications include digital multi-meter, programmable gain
and attenuation, stepper motor control, furnace temperature control, fuel control etc.
The ADC ICs usually includes DAC so we shall first discuss DAC followed by ADC.
The current output DAC provides current as the output signal. The voltage output DAC is the combination of current
output DAC and a current to voltage converter. The voltage output DAC is slower than current output DAC because of the
additional delay in converting the current signal into voltage signal. However, in many applications it is necessary to
convert current into voltage by using operational amplifier (Op-Amp). Multiplying DACs is a digital to analog converter
which uses a varying reference voltage (say VR) is called multiplying DAC.
Basic DAC Technique
164
The schematic of a DAC is shown in figure 15.2. An n-bit binary word input (here 8-bit) is combined with a reference
voltage VR gives an analog output signal V0. Generally, the output of a DAC is in current form, which can be converted
into Voltage form by using Op-Amp.
VR or VFS
(MSB)D7
D6
D5
D4
D3
D2
D1
(LSB)D0
I0
DAC
+
V0
_
n-1
n-2
V0 = (Dn-1 2 + Dn-2 2 ++ D1 2 + D0)
(15.2)
2
For example, let us consider a 3-bit converter. Here, n=3 and we have:
V0 = (D2 4 + D1 2 + D0)
(15.3)
8
A 3-bit binary word input and corresponding output voltage can be calculated using equation 15.3 and given in table 15.1:
Table 15.1
000
001
010
011
100
101
110
111
0
VR/8
2VR/8
3VR/8
4 VR/8
5 VR/8
6 VR/8
7 VR/8
V0 = (4 + 0 + 0) = VR/2
8
V0 = (4 + 2 + 0) = 6VR/8
8
The above analysis shows that the analog output voltage is proportional to the digital input.
Monolithic DACs consisting of R/2R ladder resister network, switches and the feedback resistors are available for 8, 10,
12, 14 and 16-bit resolution from various manufacturers. The MC1408 is an 8-bit DAC with current output. The SE/NE
5018 is also an 8-bit DAC but with a voltage output. However, the hybrid DACs also available as DAC-HZ (DATEL) series
for current as well as voltage outputs.
A typical 8-bit MC 1408 (DAC 808) as shown in figure 15.3 is compatible with TTL and CMOS logic and has a settling time
of 300ns. Settling time is defined as the time required for conversion, and depends on the response time of the switches
and the output amplifier (for a voltage output DAC). It has eight input data lines D7 (MSB) through D0 (LSB). In the
MC1408 (DAC0808), the digital inputs are converted to current (Io) by connecting a resistor network, then we convert
the resulting current into voltage signal. The total current Io is a function of the binary digits at the D0-D7 inputs of the
DAC0808 and the reference current Iref. It requires 2 mA reference current Iref (must be applied to pin 14) for full scale
input and two power supplies VCC=+5v and VEE =-5V (VEE can range from -5V to -15V). The total reference current source
is determined by resister R14 and voltage reference VR and is equal to VR/R14= 5V/2.5K=2mA. The resistor R15=R14 match
to the input impedance of the reference source. The output current I0 is calculated as follow:
I0= 7=0 2
14
1
0
I0=Iref 27 + 46 + 85 + 164 + 323 + 642 + 128
+ 256
(15.4)
For all the inputs to the DAC are high (111111112), the maximum output current is calculated as given below:
5
7
I0=
1 2 = 2mA (255/256) = 1.99218mA
2.5 =0
The output current from the DAC for the input 000000012 (1 LSB) is given as follow
I0=2mA (1/256)=0.00782mA
From the above two examples, we can see and conclude that the maximum output current is 1 LSB less than the full
scale or reference current of 2 mA. Similarly, the maximum output voltage is 1 LSB less than the full scale voltage.
Converting I0 to voltage in DAC 808
We connect the output pin Io to a resister and convert this current to voltage and monitor the output voltage Vo on the
scope. The Io current output is isolated by connecting it to a 741 Op-Amp with RF=5K for the feedback resistor as shown
in figure 15.3. If all the inputs to the DAC are high, the maximum output voltage is as follow:
Vo= 2mA (255/256) 5K = 9.961 V +10V
The output voltage for the input 000000012 (1 LSB) is given as follow:
V0=2mA (1/256) 5K=0.03906
Example 15.1: Assuming RF=5K and Iref=2mA, calculate Vo for the following binary input sequences:
(a) 10011011B
(b) 00000000B
Solution:
(a) IO=2mA (155/256)=1.211 mA and Vo=1.211 mA x 5K=6.055V.
(b) IO=2mA (0/256)=0 mA and Vo=0 mA x 5K=0V.
VCC=+5V
R14=2.5K
(MSB)D7
D6
D5
D4
D3
D2
D1
(LSB)D0
5
13
14
6
7
8
9
808/1408
10
11
4
12
16 3 1 2 15
I0=2mA
VR=+5V
RF=5K
I0
741
+
R15=2.5K
15pF
VEE=-5V
166
Vo (To scope)
The MC1408 (DAC 808) can be calibrated for bipolar range -5V to +5V by adding resistor RB= 5K between VR and output
pin 4 as shown in figure 15.4. The resistor RB supplies VR/RB=1mA current to the output in the opposite direction of the
current generated by the input signal. Therefore, the output current for the bipolar operation I0 is given by
IO=IO - (VR/RB) =
14
7
=0
2 - (VR/RB)
(15.5)
VCC=+5V
R14=2.5K
(MSB)D7
D6
D5
D4
D3
D2
D1
(LSB)D0
5
13
14
6
7
8
9
808/1408
10
11
4
12
16 3 1 2 15
VR=+5V
1mA
RB=5K
RF=5K
I0
I0
741
Vo
+
R15=2.5K
15pF
VEE=-5V
For example, if all the inputs to the DAC are low i.e. binary input word=000000002, then the output voltage VO is
VO=IO RF = (IO-VR/RB) RF= (0-5V/5K) 5K = -5V
If binary input word=100000002, then output voltage VO becomes
VO=IO RF = (IO-VR/RB) RF= [(VR/R14) (128/256)-5V/5K)+ 5K = *(5V/2.5K) (1/2)-5V/5K) 5K
= (1mA-1mA)x 5K=0V
Similarly, for binary input word=111111112, output voltage VO becomes
VO=IO RF = (IO-VR/RB) RF= [(VR/R14) (255/256)-5V/5K)+ 5K = (1.992A-1mA) 5K
= (0.992mA) x 5K= +4.960 +5V
Note: For unipolar calibrated DAC output voltage Vo vary from 0V to 10V, and for Bipolar calibrated DAC output voltage
Vary from -5V to +5V.
Illustration for Interfacing an 8-Bit DAC (MC1408) with the 8051 Microcontroller
All 8051 peripherals are memory mappedthe programming interface is a set of memory-addressed registers. The
interfacing circuit is shown in figure 15.5. The data lines of the DAC chip are directly connected to the port 1 lines of the
microcontroller. The port 1 lines configured as output port upon power on reset otherwise made output port, to send
digital output to the DAC.
Example 15.2: Draw the interfacing diagram to interface the DAC 808 and calibrate DAC for unipolar output voltage
range (0 to 10V) and also write a program to send data to the DAC to generate a continuous stair-step ramp
waveform.
Solution: The interfacing circuit is shown in figure 15.5.
XRL A, A
; Clear Accumulator
Back: MOV P1, A
; Send out data bits to the output port FFH
INC A
ACALL DELAY
; Call delay subroutine
SJMP Back
DELAY: MOV R2, #COUNT
L1: DJNZ L1
RET
The delay in this program is necessary due to the two reasons:
167
1. Set the suitable count value to ensure that next data bits not placed in DAC during conversion process of present
data bits i.e. delay must be greater than settling time of the DAC.
2. The slope of the ramp can be modified by changing the delay time.
VCC=+5V
R14=2.5K
8051
(P1.7) D7
(P1.6) D6
(P1.5) D5
(P1.4) D4
(P1.3) D3
(P1.2) D2
(P1.1) D1
(P1.0) D0
GND
5
13
14
6
7
8
9
808/1408
10
11
4
12
16 3 1 2 15
VR=+5V
Vref(+)
RF=5K
I0
741
Vref (-)
15pF
Vo
R15=2.5K
VEE=-5V
Figure 15.5: Interfacing of the DAC808 (voltage output in unipolar range) with the 8051
Example 15.3: Write a program for the same design (figure 15.5) to generate a square wave.
Solution: The square wave has 0V output for half a period and a voltage of amplitude V1 for another half.
The value to be sent for a particular amplitude voltage V1 is calculated using the following formula:
n
Value for voltage V1= [(2 -1)/ Maximum output voltage] Amplitude of V1
For example, the equivalent value for a 5V output from a DAC with an 8-bit binary input and a maximum output of 10V, is
8
calculated by [(2 -1)/ 10] 5V=128 (whole number)=80H and equivalent value for 0V is 00H.
BACK: MOV P1, #00H
; Send 0 to P1.1
ACALL DELAY
; Delay
MOV P1, #80H
; Send 5V to P1.1
ACALL DELAY
SJMP BACK
Example 15.4: Write a program for the same design (figure 15.5) to generate a Ramp wave on P1.1.
Solution: Here the value 00H to FFH to be sent to DAC for a voltage level 0 to 10V, respectively.
MOV A, #00H
; Load A with 0
BACK: MOV P1, R3
; Send A to port 1
LCALL DELAY
; Delay
INC A
; increment A by 1
SJMP BACK
; Keep sending
RET
Example 15.6: Write a program for the same design (figure 15.5) to generate a sine wave.
Solution: To generate a sine waveform, our first need a look up table whose values are equivalent representation of the
voltage magnitudes of the sine wave of angle varies from 0 to 360 degree. The value of sine function varies from -1 to +1
for 0 to 360 degree angle, respectively.
Table 15.2 shows the angle, the sine value, the voltage magnitude and the values representing the voltage magnitude for
each angle with 30 degree increment. For better shape of sine wave we can use 5, 10, 15 etc. degree increment. To
generate sine wave, we first need a table whose values represent the magnitude of the sine of angles between 0 and
360 degrees. The values for the sine function vary from -1.0 to +1.0 for 0 to 360 angles. We assumed that the full scale
voltage of 10V for DAC output. The full scale output (10V) of the DAC achieved all the data inputs of the DAC is high.
Therefore to achieve the full scale 10V output, we use the following equation V o of DAC for various sine degrees is
calculated as follows:
Vo= 5+5 sin
To find the value to be sent to DAC for various angles simply multiply the Vo voltage by 25.6 because there are 256 steps
(00 to FFH) and full scale output voltage Vo is 10V. Therefore, 256 steps/10V=25.6 steps per volt. For example, the
equivalent value for angle 30, output voltage Vo from a DAC with an 8-bit binary input and a full scale output of 10V, is
calculated by Vo = 5 V + (5 V Sin) =5 V + 5 Sin 30 = 5 V 2.5 = 7.5 V.
DAC input value = 7.5 V 25.6 = 192 (decimal integer).
Table 15.2: Angle versus Voltage magnitude and corresponding value sent to DAC for the sine wave
Angle (degree)
sin
0
30
60
90
120
150
180
210
240
270
300
330
360
0
0.5
0.866
1.0
0.866
0.5
0
-0.5
-0.866
-1.0
-0.866
-0.5
0
5
7.5
9.33
10
9.33
7.5
5
2.5
0.669
0
0.669
2.5
5
128
192
238
256
238
192
128
64
17
0
17
64
128
Program:
Again: MOV DPTR, #4120H
MOV R2, #0DH
MOV R3, #count
Back: MOV A, #00H
MOV A, @DPTR
MOV P1, A
LCALL DELAY
INC DPTR
DJNZ R2, Back
SJMP Again
169
ADC 800 series from National semiconductor. It is also available from many other manufacturers. It works with +5V and
has resolution of 8-bit. In addition to resolution, settling time or conversion time is another major factor in judging an ADC.
Settling time is defined as the time it takes the ADC to convert the analog input to a digital (binary) number. In the
ADC804, the conversion time varies depending on the clocking signals applied to the CLK R and CLK IN pins, but it
cannot be faster than 110 ms. The ADC804 pin diagram shown in figure 15.9 and description as follow:
CS (Chip Select): Chip select is an active low input used to activate the ADC804 chip. To access the ADC804, this pin
must be low.
RD (Read): Read is an active low input signal. The ADC converts the analog input to its binary equivalent and holds it in
an internal register. RD is used to get the converted data out from the ADC804 chip. When CS=0, if a high-to-low pulse
applied to the RD pin, the 8-bit digital output shows up at the DB0-DB7 data pins. The RD pin is also referred to as output
enable.
WR (Write): This is an active low input used to inform the ADC804 to start the conversion process. If CS=0 when W R
makes a low-to-high transition, the ADC804 starts converting the analog input value of V IN to an 8-bit digital number. The
amount of time it takes to convert varies depending on the CLK IN and CLK R values explained below. When the data
conversion is complete, the INTR pin is forced low by the ADC804.
CLK IN and CLK R: CLK IN is an input pin connected to an external clock source when an external clock is used for
timing. However, the 804 has an internal clock generator. To use the internal clock generator of the ADC804 the CLK IN
and CLK R pins are connected to a capacitor and a resistor. In that case clock frequency determined by the equation:
1
fclock =
1.1
Typical values for R=10K and C=150 pF and we get fclock= 606kHz. In that case conversion time is 110 ms.
170
VREF/2 (V)
Not connected
2.0
1.5
1.0
0.5
*step size (resolution) is the smallest change that can be
VIN (V)
0 to 5
0 to 4
0 to 3
0 to 2
0 to 1
observed by an ADC
DB7-DB0 (Data Bus): From DB7 (MSB) to DB0 (LSB) are the data output lines. These are tri-state buffered and converted
data accessed only when CS=0 and RD is forced low. To calculate the output voltage, use the following formula:
Dout=
Where Dout=digital data output (in decimal), VIN=analog input voltage, and step size (resolution) is the smallest change,
which is (2 VREF/2)/256 for an 8-bit ADC.
Analog Ground (AGND) and Digital Ground (DGND): These are the input pins providing the ground for both the analog
VIN while digital ground is connected to the ground of the V+ pin. The reason that we have two ground pins is to isolate the
analog VIN signal from transient voltages caused by digital switching of the output DB7-DB0. Such isolation contributes to
the accuracy of the digital data output. In this book, both are connected to the same ground; however, in the real world of
data acquisition the analog and digital grounds are handled separately.
171
st
1 comparison
nd
rd
comparison
3 comparison
7/8VR
7/8VR
5/8VR
101
5/8VR
1/2VR
100
101
1/2VR
100
3/8VR
3/8VR
011
011
1/4VR
010
DAC output voltage
110
3/4VR
110
3/4VR
111
111
control register
contents 1/8VR
1/4VR
010
1/8VR
001
000
001
START
VIN
EOC
Time
delay
SAR
DB7 (MSB)
DB6
DB5
Analog Comparator
.
.
.
.
Digital Output
Dout
DB0 (LSB)
DAC
VDAC
The successive approximation principle uses a very efficient code search strategy to complete n-bit conversion in just
n-clock periods. Figure 1511 shows an eight bit converter. The circuit uses a successive approximation register (SAR) to
find the required value of each bit by trial and error (first try then check, if any error, moves to next tries and check). The
circuit operates as follows: With the arrival of the START conversion command, the SAR sets the MSB DB7=1 with all
other bits set to zero so that the trial code is 1000000. The DAC converts 1000000 to its analog equivalent. The analog
output VDAC of the DAC is now compared with analog input VIN. If VIN is greater than VDAC then 10000000 is less than the
correct digital representation. The MSB is left at 1 and the next lower significant bit is made 1 and further compared.
However, if VIN is less than the DAC output VDAC, then 10000000 is greater than the correct digital representation. So
reset MSB DB7=0 and the next lower significant bit is made 1 and further compared. This procedure is repeated for all
subsequent bits, one at a time, until all bit positions have been tested.
Whenever the DB0 is set, this can be taken as the end of conversion (EOC). However, when DB 0 is set it will END the
conversion process, which may give inaccurate result. To avoid this we give the suitable time delay to test last bit DB 0 in
mid of DB0 and EOC signal carrying path.
172
Upon receiving interrupt at I NT0 (edge-triggered), the microcontroller should issue a low on the RD signal (low), and read
the data from ADC IC and go to next conversion. From the discussion we concluded a general algorithm for ADC interfacing
contains the following steps:
1. Ensure the stability of analog input, applied to the ADC.
2. Make CS=0 and send a low-to-high pulse to pin WR to start the conversion.
3. Keep monitoring the I NTR pin. If I NTR is low, the conversion is finished and we can go to the step-4. Otherwise keep polling
until I NTR goes low.
4. After the I NTR has become low, we send a high-to-low pulse to the RD pin to read the data from the ADC804 IC. The timing
for this process is shown in figure 15.12:
CS
W R
I NTR
RD
DB7-DB0
Data out
Start conversion
End conversion
data read
Figure 15.12: Data conversion start (write) and read timing for ADC 804
Example 15.7: The microcontroller starts the ADC, reads and stores the results of 16 successive conversions,
then stop. The 16 data bytes are stored in 16 successive memory locations. Write a program to read the analog
input using polling and interrupt driven methods for the figure 15.13.
Program:
+5V
8051
VCC
VIN (analog input)
VIN(+)
VIN(-)
10K
120pF
DB7
DB6
DB5
AGND
DB4
ADC 804 DB3
DGND
DB2
DB1
CLK IN
DB0
VREF/2
I N TR
CS
WR
R D
P1.7
P1.0
P3.3
P2.5
P2.6
Figure 15.13: Interfacing ADC 804 with the 8051
Using polling
MOV P1, #0FFH
MOV R0, #40H
MOV R2, #16
SETB P3.3
NEXT: CLR P2.6
SETB P2.6
L1: JB P3.3, L1
SETB P2.5
CLR P2.5
MOV A, P1
173
MOV @R0, A
INC R0
DJNZ R2, NEXT
END
; Save it in RAM
; Increment data pointer
; Is 16 reading is saved? If not go to next
ORG 000H
SJMP MAIN
ORG 0013H
SJMP ISR1
ORG 40H
MAIN: MOV P1, #0FFH
MOV R0, #40H
MOV R2, #16
SETB P3.3
NEXT: CLR P2.6
SETB P2.6
HERE: SJMP HERE
END
; Reset address
; Jump to main program
; INT1 vector location
; When interrupt occurs go to ISR1
; Make port 1 as input port
; Set internal RAM pointer to save analog input values
; Initialize counter
; Make P3.3 as input pin
; Clear P2.6
; Low to high signal on W R to start conversion
Figure 15.14: The 8051 connection to the ADC804 with clock from XTAL2 of the 8051
inputs using only a single chip. Notice that the ADC0808/0809 has an 8-bit data output just like the ADC804. The 8
analog input channels are multiplexed and selected according to Table 13-3 using three address pins, A, B, and C.
In the ADC0808/0809, Vret(+) and Vref(-) set the reference voltage. If Vref(-) = Gnd and Vref(+) = 5 V, the step size is 5 V/256
= 19.53 mV. Therefore, to get a 10 mV step size we need to set Vref(+) = 2.56 V and Vref(-) = Gnd.
From the figure 15.15, notice the ALE pin. We use A, B, and C addresses to select IN0 - IN7 (table 15.4), and activate ALE
to latch in the address. SC is for start conversion. SC is the same as the WR pin in other ADC chips. EOC is for end-ofconversion, and OE is for output enable (READ). The EOC and OE are the same as the INTR and RD pins respectively.
Table 15.5 shows the step size relation to the Vref voltage. Notice that there is no Vref/2 in the ADC0808/0809 chip.
Table 15.4: ADC0808/0809 Analog Channel Selection
Select an analog channel by providing bits to A, B, and C addresses according to table 15.4.
Activate the ALE (address latch enable) pin. It needs an L-to-H pulse to latch in the address (see figure 15.16).
Activate SC (start conversion) by an L-to-H pulse to initiate conversion.
Monitor EOC (end of conversion) to see whether conversion is finished. H-to- L output indicates that the data is
converted and is ready to be picked up. If we do not use EOC, we can read the converted digital data after a
175
brief time delay. The delay size depends on the speed of the external clock we connect to the CLK pin. Notice
that the EOC is the same as the INTR pin in other ADC chips.
5. Activate OE (output enable) to read data out of the ADC chip. An L-to-H pulse to the OE pin will bring digital data
out of the chip. Also notice that the OE is the same as the RD pin in other ADC chips.
Figure 15.17: The Pin diagram for the MAX 1112 ADC
CH0 CH7: The CH0 CH7 are 8 channels of the analog inputs. In the single-ended mode, each of the channels can be used for an
analog input where the COM pin is used as a ground reference for all the channels. In single-ended mode, 8 channels of input allow
176
us to read 8 different analog inputs. We select the input channel by sending in the control byte via the D IN pin. In differential mode,
we have 4 sets of 2-channel differentials. CH0 and CH1 go together, and CH2 -CH3, and so on.
COM: Ground reference for the analog input in single-ended mode.
CS: Chip select is an active low input used to select the MAX1112 chip. To send in the control byte via the D IN pin, CS must be low.
When CS is high the DOUT is high impedance.
SCLK: Serial clock input. SCLK is used to bring data out and send in the control byte, one bit at a time.
DOUT: Serial data out. The digital data is clocked out one bit at a time on the H-to-L edge (falling edge) of SCLK.
DIN: Serial data in the control byte is clocked in one bit at a time on the L-to-H edge (rising edge) of SCLK.
SSTRB: Serial strobe output. In internal clock mode this indicates end-of-conversion. It goes high when the conversion is complete.
VDD : It is the +5 volt power supply.
AGND, DGND (analog ground and digital ground): Both are input pins providing ground for both the analog and the digital signals.
SHDN: Shutdown is an input and is normally not connected (or is connected to V DD). If low, the ADC is shut down to save power. This
is shut down by hardware. The control byte causes shutdown by software.
REFIN: Reference voltage input. This voltage dictates the step size.
REFOUT: Internal Reference Generator output. A 1 F bypass capacitor is placed between this pin and AGND.
using SCLK. The DIN pin clocks in the control byte on the rising edge of SCLK as shown in figure 15.18.
177
Figure 15.18: MAX 1112 Internal clock mode timing diagram for sending control byte into it
Example 15.8: Find the MAX1112 control byte for (a) CH0, and (b) CH3. Assume single-ended, unipolar, internal clock,
and fully operational modes. Draw the interfacing diagram and write a program to load control byte in control byte
register in the MAX 1112.
Solution:
From table, we have the following:
(a) 10001110B (8EH)
(b) 10111110B (BEH)
When the last bit of the control byte, PDO, is sent in, the conversion starts, and SSTRB goes low. The end-of-conversion
state is indicated by SSTRB going high, which happens after 55 s or after PDO is clocked in. We can either wait 55 s,
or monitor SSTRB before we get the digital data out of the ADC chip. Next we show how to get digital data out of the
MAX1112.
Reading out digital data
The 8-bit converted digital data is brought out of the MAX1112 via the DOUT pin using SCLK. As we apply a negative-edge
pulse to the SCLK pin, the 8-bit digital data is read out one bit at a time with the MSB (D7) coming out first. The SSTRB
goes high to indicate that the conversion is finished. According to the MAX1112 data sheet, after SSTRB goes high, the
second falling edge of SCLK produces the MSB of converted data at the D0 UT pin. In other words, we need 9 pulses to
get data out. To bring data out, CS must be low. See figure 15.19. The following is Assembly program to read digital data
TEMPERATURE MEASUREMENT
As we have seen, an ADC produces a binary code based on a full scale voltage. If you are measuring a temperature, for
example, this information means very little to you. What you really want to know is the temperature of what you are
measuring. There are two series of sensor ICs from the National Semiconductor; LM34 and LM35. The circuit in figure
15.20, shows a commonly used temperature sensor Integrated Circuit (IC), the National Semiconductor LM34A.
The LM34A produces a voltage that is directly proportional to the temperature surrounding it, specifically, 10 mV/F.
The amplifier is designed to have a gain of 2.5, and thus 50 to 300F will produce a voltage of 1.25 to 7.50 volts. By
using an 8-bit ADC, you can obtain a resolution of about 0.342F (350F/256). Note that the ADC can only convert positive
voltages, and thus a bias of 1.25 volts is introduced following the amplification stage to ensure that a positive voltage is
present at the input of the ADC for the complete temperature range. With this bias, 50F will appear as 0 V, 0F will be
1.25V and 300F will be 8.75 V. The value obtained at the ADC is given by:
Where, counts is an industry standard convention that means the binary value of the ADC.
0.01V/F corresponds to the transducer transfer function10 mV/Fspecified by National Semiconductor.
2.5 is the gain of the amplifier stage and is established by the hardware designer.
1.25 is the bias voltage to ensure that the ADC always reads a positive voltage.
255 is the maximum binary value taken by a 8-bit converter.
10VFullScale is the full scale voltage.
179
For example, a temperature of 100F would have a value of 383 counts (actually, 383.625). Note that the ADC can
produce only integer values, and thus the actual value of 383.625 is truncated to 383.
SIGNAL CONDITIONING
Signal conditioning is widely used in the world of data acquisition. The most common transducers produce an output in
the form of voltage, current, charge, etc. However, we need to convert these signals to voltage in order to send input to an
A-to-D converter. This conversion is commonly called signal conditioning. See figure 15.20, voltage amplifier, bias voltage
and filter are used for signal conditioning.
We can also obtain the temperature in degrees Celsius by using an LM35A which gives output voltage is directly
proportional to the Celsius temperature (with sensitivity of 10 mV/C).
Analog Outputs
A typical digital to analog system generally consists of the following circuit elements:
Digital to analog converter (DAC)
Filter
Amplifier
Transducer
Digital-to-analog converters (DACs) are generally inexpensive devices, and thus each analog output channel can have its
own DAC, as shown in figure 15.21. The DAC converts a binary value provided by a microcontroller to either a current or
a voltage (depending on the DAC). The voltage or current is filtered to smooth out the step changes. An amplifier stage is
sometimes used to increase the amplitude or power drive capability of the analog output channel in order to properly
interface with the transducer. The transducer is used to convert the electrical signal to a physical quantity. For example,
transducers are available to convert electrical signals to pressures (known as current-to-pressure transducers, or I to P).
These pressures can beand often areused to control other physical devices.
REVIEW QUESTIONS
1.
2.
3.
4.
5.
6.
7.
8.
180
CHAPTER-16
INTERFACING WITH THE KEYBOARD, SEVEN SEGMENT DISPLAY, LCD AND MOTORS
KEYBOARD
A keyboard uses an arrangement of buttons or keys, to act as mechanical levers or electronic switches. A
switch has a metal strip to connect the circuit, which can be pressed with the help of a fiber or rubber
surface. Metal contact switches simply have a spring-loaded key with a strip of metal on the bottom of the
plunger. When the key is pressed, the metal strip connects the two parts of the circuit. When the
processor finds a circuit that is closed, it compares the location of that circuit on the key array/matrix to
the numeral map in memory. A numeral map is basically a comparison chart or lookup table. It tells the
processor the position of each key in the array/matrix and what each keystroke represents. There are two
types of keyboard, one is simple and other is in matrix form.
KEY DEBOUNCE
The mechanical action of the switch causes some vibration or unsmooth transient response due to multiple
key pressures, called debounce, which the microcontroller system filters out by using one of the two
techniques; one is using a bistable multivibrator at the output of the key to debounce, and other
technique is microcontroller should be made to wait for transient period (30 ms delay), so that transient
response settle down and reaches a steady state.the bouncing of key signals occurs within 5 ms. A human
cannot press and release a switch in less than 30 ms. A debouncing logic will check the signal after 10 ms
and then recognize whether a key is pressed or not. If we press and hold a key for a long time, the
processor recognizes it as the equivalent of pressing a key repeatedly.
CONTACT BOUNCE AND DE-BOUNCING
Push-button switches, toggle switches, and electro-mechanical relays all have one thing in common:
contacts. It's the metal contacts that make and break the circuit and carry the current in switches and
relays. Because they are metal, contacts have mass. And since at least one of the contacts is on a
movable strip of metal, it has springiness. Since contacts are designed to open and close quickly, there is
little resistance (damping) to their movement.
Because the moving contacts have mass and springiness with low damping they will be "bouncy" as they
make and break. That is, when a normally open (N.O.) pair of contacts is closed, the contacts will come
together and bounce off each other several times before finally coming to rest in a closed position. The
effect is called "contact bounce" or, in a switch, "switch bounce" see figure 16.1. Note that contacts can
bounce on opening as well as on closing.
The Problem
If we want our switch or relay to do is turn on a lamp or start a fan motor, then contact bounce is not a
problem. But if we are using a switch or relay as input to a digital counter, a personal computer, or a
microcontroller based equipment, then we must consider contact bounce. The reason for concern is that
the time it takes for contacts to stop bouncing is measured in milliseconds. Digital circuits can respond in
microseconds.
As an example, suppose we want to count objects as they go by on a conveyor belt. We could set up a
sensitive switch and a digital counter so that as the objects are counted by activate the switch and
increment the counter. But what we might see is that the first widget produces a count of 47, the second
widget causes a count of 113, and so forth. What's going on? The answer is we are not counting objects;
we are counting how many times the contacts bounced each time the switch is activated!
The Solution
There are several ways to solve the problem of contact bounce (that is, to "de-bounce" the input signal)
using hardware or software.
Using Hardware
A simple hardware debounce circuit for a momentary N.O. push-button switch is show in figure 16.2 (a), it
uses an RC time constant to remove the bounce. If we multiply the resistance value by the capacitance
value we get the RC time constant. We should choose R and C so that RC time constant is longer than the
181
expected bounce time. An RC value of about 0.1 s is typical. Note the use of a buffer after the switch to
produce a sharp high-to-low transition. And remember that the time delay also means that we have to
wait before push the switch again. If we press it again too soon it will not generate another signal.
(b) Latch
Another hardware approach is shown in figure 16.2 (b) It uses a cross-coupled latch made from a pair of
NAND gates. We can also use an SR flip flop. The advantage of using a latch is that we get a clean
debounce without a delay limitation. It will respond as fast as the contacts can open and close. Note that
the circuit requires both normally open (N.O.) and normally closed (N.C.) contacts. In a switch, that
arrangement is called "double throw". In a relay, that arrangement is called Form C.
Using Software
The software technique uses the wait and watch method. When a signal is sensed from a switch, the
program waits for 30 ms and checks the same key again. If the signal from the switch still indicates the
key press, the program decides that the user has pressed the key. Otherwise, the signal received is
rejected as bounce noise. A key check subroutine is given below in the program.
SIMPLE KEYBOARD AND SEVEN SEGMENT DISPLAY INTERFACE
This type of keys arrangement and interfacing shown in figure 16.3 and table 16.1, the one end of key
terminals of SW7-SW0 is connected to the port of the 8051 through 10K pull-up resister to ensure that the
row is pulled high when no push-button switch is closed and other end is connected to ground. When no
key is pressed or all keys are open, the microcontroller read the FFH at port 1. When a key is pressed, the
corresponding line is grounded. For example, if SW 6 is pressed, the input data at port 1 will be 10111111
(BFH). These types of readings of keys should be encoded into their binary equivalent (as shown in table
16.1) of the digits from 7 to 0 by using conversion program or look-up table.
+5V
10k
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
SW7
SW6
SW5
SW4
SW3
SW2
SW1
SW0
8051
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
74LS240
220
GND
+5V
a
DP
g
f
f
e
d
c
b
a
g
e
Common anode
DP
Figure 16.3: Interfacing the keyboard and seven-segment display with the 8051
182
c
d
The interfacing of seven segment display with the 8051 needs a current driver because seven segment display and the
8051 are not current compatible. In the figure 16.3, the 74LS240 TTL inverter IC driver is used to interface them.
Table 16.1: Related key codes and their encoded binary digits
Key press
Data at Port 1
Description
none
SW 7
SW 6
SW 5
SW 4
SW 3
SW 2
SW 1
SW 0
11111111=FFH
01111111=7FH
10111111=BFH
11011111=DFH
11101111=EFH
11110111=F7H
11111011=FBH
11111101=FDH
11111110=FEH
none
00000111=07
00000110=06
00000101=05
00000100=04
00000011=03
00000010=02
00000001=01
00000000=00
Main Program:
ORG 0040H
MOV P1, #0FFH
Knext: ACALL Kcheck
ACALL Kcode
ACALL Display
SJMP Knext
; Read port A
; Check any key is pressed or not?
; If zero, no key pressed so check again
; If yes, wait for 30 ms to prevent from Debounce
; Read Port A again
; Save a copy of A in R3
; Check any key is pressed or not?
; If zero, no key pressed so check again
; If yes, return to main program to call key encoder routine
Display subroutine
Display: MOV DPTR, #KE7SCODE
MOVC A, @A+DPTR, #KE7SCODE
MOV P2, A
RET
Look-up-table
KE7SCODE: DB 3F, 06, 5B, 4F, 66, 6D, 7D, 07
3F
06
5B
4F
66
6D
7D
07
key 0
key 1
key 2
key 3
key 4
key 5
key 6
key 7
183
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
C-1
2
C-2
3
C-3
R-1
R-2
R-3
R-0
+5volt
8051
P2.0
P2.1
P2.2
P2.3
Display
P00-7
For example, for the figure 16.4, identify the pressed key if P1.3-P1.0=1011 for the row, and P2.3-P2.0=1110 for the
column, the row belongs to P1.2 and the column belongs to P2.0; therefore, key number 8 has been pressed.
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Similarly, identify the pressed key if P1.3-P1.0=0111 for the row, P2.3-P2.0=1101 for the column, the row belongs to P1.3
and the column belongs to P2.1; therefore, key number D has been pressed.
; Column-0
; Column-1
; Column-2
; Column-3
In many applications, it is essential to keep a track of the system working. For example, an oven, washing machine, an
autonomous robot etc. This is achieved by displaying their controlled and controlling parameter on a small display module.
LCD (Liquid Crystal Display) screen is such a display module. A 16x2 LCD display is very basic module and is very
commonly used in various devices and circuits. LCD modules are replacing seven segments and other multi segment
LEDs for these purposes due to LCDs are economical, easily programmable, have no limitation of displaying special and
even custom characters (unlike in seven segments),
animations and so on. LCD can be easily interfaced with
microcontroller to display a message or status of a
device.
A 162 LCD indicates it can display 16 characters per
Symbol
Input/Output
Description
VSS
VCC
VEE
0V
+5V
Contrast adjustment by providing a variable resistor through VCC
RS
Ground
Main power supply
Power supply to control
contrast
Input to register select
R/W
Input
Input
7-14
DB0-DB7
15
16
Led+
-Led
Backlight VCC
Backlight Ground
VEE pin is used for adjusting the contrast of the LCD display and the contrast can be adjusted by varying the voltage at
this pin. This is done by connecting one end of a POT to the Vcc (5V), other end to the Ground and connecting the center
terminal (wiper) of the POT to the VEE pin. See the interfacing diagram.
The 162 LCD module has two built in registers namely data register and command register. Data register is for placing
the data to be displayed, and the command register is to place the commands. The 162 LCD module has a set of
commands each decoded for doing a particular job with the display.
High logic at the RS pin will select the data register and Low logic at the RS pin will select the command register. If we
make the RS pin high and the put a data in the 8 bit data line (DB0 to DB7), the LCD module will recognize it as a data to
be displayed. If we make RS pin low and put a data on the data line, the module will recognize it as a command.
R/W pin is used to select read or write modes. A high at this pin enables read mode and a low at this pin enables write
mode.
E pin is for enabling the module. A high-to-low transition at this pin will enable the module.
DB0 to DB7 are the data lines. The data to be displayed and the command instructions are placed on these lines.
LED+ is the anode of the back light LED and this pin must be connected to Vcc through a suitable series current limiting
resistor.
LED- is the cathode of the back light LED and this pin must be connected to ground.
162 LCD MODULE COMMANDS
186
This LCD module has two registers, namely, Command and Data register. The command/instruction register stores the
command or instruction code given to the LCD by the microcontroller. The command register stores instruction codes,
such as display clear and cursor shift, and address information for display data and character generator. The command
register can only be written from the microcontroller.
The data register temporarily stores the data to be displayed on the LCD. Data written into the data register from the
microcontroller is automatically written into command register by an internal operation. The data register is also used for
data storage when reading data from command register. When address information is written into the command register,
data is read and then stored into the data register from command register by an internal operation. Data transfer between
the microcontroller and LCD is completed when the microcontroller reads the DR. The data is the ASCII value of the
character to be displayed on the LCD.
Busy Flag (BF)
When the busy flag is 1, the LCD module is in the internal operation mode, and the next instruction will not be accepted. When RS =
0 and R/W = 1, the busy flag is output to DB7. The next instruction must be written after ensuring that the busy flag is 0.
The 162 LCD module has a set of preset command instructions. Each command will make the module to do a particular
task. The commonly used commands and their function are given in the table below.
187
188
ACALL CMND
ACALL DELAY
MOV A, #01
ACALL CMND
ACALL DELAY
MOV A, #0C1H
ACALL CMND
ACALL DELAY
MOV A, #06H
ACALL CMND
ACALL DELAY
MOV A, #83H
ACALL CMND
ACALL DELAY
MOV A, # X
ACALL DISPLY
ACALL DELAY
MOV A, # U
ACALL DISPLY
ACALL DELAY
MOV A, # V
ACALL DISPLY
L1: SJMP L1
CMND: MOV P1, A
CLR P2.5
CLR P2.4
SETB P2.3
ACALL DELAY
CLR P2.3
RET
DISPLY: MOV P1, A
SETB P2.5
CLR P2.4
SETB P2.3
ACALL DELAY
CLR P2.3
RET
; Clear LCD
; Display U
; Display V
; Stay here
; Send A to port 1
; RS=0 for command
; R/W=0 for write
; E=1 for high pulse
; E=0 for H-to-L pulse
; Send A to port 1
; RS=1 for data
; R/W=0 for write
; E=1 for high pulse
; E=0 for H-to-L pulse
189
Example 16.2: Write a program to initialize the LCD and display message XUV using the busy flag (D7=P1.7).
Solution:
MOV A, #38H
; Initialize 2 lines, 57 dot matrix
ACALL CMND
; Call command subroutine
ACALL DELAY
; Call delay for 1.52 ms
MOV A, #0EH
; Display on, cursor on
ACALL CMND
MOV A, #01
; Clear LCD
ACALL CMND
MOV A, #0C1H
; Jump to second line, position 1
ACALL CMND
MOV A, #06H
; Shift cursor right
ACALL CMND
MOV A, # X
; Display ASCII letter X
ACALL DISPLY
MOV A, # U
; Display U
ACALL DISPLY
MOV A, # V
; Display V
ACALL DISPLY
HERE: SJMP HERE
; Wait for reset
CMND: ACALL READY
MOV P1, A
CLR P2.5
CLR P2.4
SETB P2.3
CLR P2.3
RET
190
The permanent magnet (PM) stepper has a rotor with alternating north and south poles (see figure 16.8). As the coils are
energized, the rotor is pulled around. This figure shows a single coil to illustrate the concept, but a real stepper would
have stator windings surrounding the rotor. The PM stepper has more torque than an equivalent VR stepper.
The hybrid stepper essentially adds teeth to a permanent magnet motor, resulting in better coupling of the magnetic field
into the rotor and more precise movement.
Bipolar versus Unipolar
A Stepper Motor is a brushless, synchronous DC Motor. There are two types of stepper motors Unipolar and Bipolar. Due to the ease
of operation unipolar stepper motor is commonly used by many users.
All steppers work by creating a rotating magnetic field in the stator, to which the rotor aligns itself. There are two types of
stator winding methods for stepper motors: bipolar and unipolar. Bipolar windings use field coils with no common
connections. The coils must be driven independently to reverse the direction of motor flow and rotate the motor. Unipolar
motors use coils with center-taps. The center-tap is usually connected to the positive supply, and the individual coils are
grounded (through transistors) to drive the motor. Figure 16.9 shows the difference between bipolar and unipolar motors.
Each time the field is changed in a bipolar motor or a different coil is turned on in a unipolar motor, the motor shaft steps
to the next rotation position. Typical step sizes for a stepper are 7.5 or 15. A 7.5 stepper will have 360/7.5 or 48 steps
per revolution. The step size depends on the number of rotor and stator teeth.
191
Commonly used stepper motors have four stator windings that are paired with a center tapped common. Such motors
are called as four-phase or unipolar stepper motor. The stator is a magnet over which the electric coil is wound. One end
of the coil are connected commonly either to ground or +5V. Sequence such that the motor rotates in a particular
direction. Stepper motor shaft moves in a fixed repeatable increment, which allows one to move it to a precise position.
Direction of the rotation is dictated by the stator poles. Stator poles are determined by the current sent through the wire
coils.
Half-Stepping
As was already mentioned, the rotor in a stepper motor aligns itself to the magnetic field generated by applying voltage to
the stator coils. Figure 16.10 shows a simple stepper with a single pair of rotor poles and two stator coils. Say that coil A is
energized, and the rotor aligns itself to magnet A with the North Pole up (position 1), as shown in the figure. If coil A is
turned off and B is energized, the rotor will rotate until the North Pole is at position 3. Now if coil B is turned off and coil A
is energized but in the reverse direction of what it was before, the rotor will go to position 5. Finally, if coil A is turned off
and coil B is energized with the reverse of its original polarity, the rotor will move to position 7. This sequence is called
one-phase-on drive.
Say that instead of energizing one magnet at a time, we energize coils A and B at the same time. The rotor will move to
position 2, halfway between magnets A and B. If we then reverse the current through coil A, the rotor will move to position
4. If we reverse B, the rotor moves to position 6, and, finally, if we reverse A again the rotor moves to position 8. Each of
these methods generates a full step of the rotor (in this case, 45 per step), but the actual position is different for the two
drive methods. If we combine the two, we can half-step the rotor:
A+, B off
: position 1
A+, B+
: position 2
A off, B+
: position 3
A, B+
: position 4
In this simple example, half-stepping permits a step angle of 22.5, as opposed to 45 for a full step. The same principle
applies to a real motor with several rotor teeth. A motor with a 15 full step can be half-stepped in 7.5 increments.
Half-stepping provides smoother rotation and more precise control. It is important to note, though, that for the positions
where only one phase is energized (positions 1, 3, 5, and 7); the coils need more current to get the same torque. This is
because there is only one coil (electromagnet) pulling the rotor. Switching from two coils to one coil reduces the torque by
approximately 30%, so two coils have about 140% of the torque of a single coil. We can compensate for this loss of
torque by increasing the coil current by 140% when driving a single coil.
STEP ANGLE
The total rotation of the motor is divided into steps. The angle of a single step is known as the stepper angle of the motor.
In other word, Step angle is defined as the minimum degree of rotation with a single step. To calculate step angle, simply
divide 360 by number of steps a motor takes to complete one revolution. As we have seen that in half mode, the number
of steps taken by the motor to complete one revolution gets doubled and step angle reduces to half.
As given above, Stepper Motor rotating in full mode takes 4 steps to complete a revolution (360 degree), therefore, step
angle can be calculated as given below:
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Step Angle = 360 / 4 = 90, to move rotor 360 degree, we need to send four times of steps sequence i.e. 4 90=360
degree.
And in case of half mode step angle gets half so 45.
Number of steps per revolution = 360 / step angle
Steps per second = (RPM x steps per revolution) / 60
therefore, this way we can calculate step angle for any stepper motor. Usually, step angle is given in the specification
sheet of the stepper motor. The step angle helps us to calibrate the rotation of motor, also to help us move the motor to
correct angular position.
SWITCHING SEQUENCES FOR THE STEPPER MOTOR
As discussed earlier the coils need to be energized for the rotation. This can be done by sending a bits sequence to one
end of the coil while the other end is commonly connected. The bit sequence sent can make either one phase ON or two
phases ON for a full step sequence or it can be a combination of one and two phase ON for half step sequence. Both are
tabulated below.
A stepper can actually be driven this way. Stepper motors can be driven in two different patterns or sequences, namely:
Full Step Sequence and Half Step Sequence.
Full Step Sequence
In the full step sequence, two coils are energized at the same time and motor shaft rotates. The order in which coils has to
be energized is given in the table below.
Two Phase ON
Clockwise
Step
0
1
2
3
A1
1
0
0
1
Full-Step Sequence
B1
1
1
0
0
A1
1
0
0
0
Full-Step Sequence
B1
0
1
0
0
A2
0
1
1
0
B2
0
0
1
1
CounterClockwise
One Phase ON
Clockwise
Step
0
1
2
3
A2
0
0
1
0
B2
0
0
0
1
CounterClockwise
Step
0
1
2
3
4
5
6
7
Half-Step Sequence
A1
B1
1
1
0
1
0
1
0
0
0
0
0
0
1
0
1
0
A2
0
0
1
1
1
0
0
0
B2
0
0
0
0
1
1
1
0
CounterClockwise
193
sequence is the same as it is for the two coils A1 and B1, and the opposite polarity value is given to A2 and B2. The
sequence is given in the table below:
2-wire Mode Sequence
Step
A
B
0
0
1
1
1
1
2
1
0
3
0
0
STEP SEQUENCE FOR BIPOLAR STEPPER MOTOR
Bipolar motor has simpler construction. It has two windings with no center taps and a permanent magnet at the center just
like unipolar stepper motors. Being simpler in construction, the stepping sequence is a little complex, as the power for
both the coils has to be controlled in such a way that the polarities of the poles get reversed. This polarity sequence is
shown in following table:
Step
0
1
2
3
A1
+ve
-ve
-ve
-ve
Polarity Sequence
A2
-ve
-ve
+ve
-ve
B1
-ve
+ve
-ve
-ve
B2
-ve
-ve
-ve
+ve
The above polarity sequence can be interpreted in terms of logic levels for microcontroller by activating one coil at a time
as shown in the table below:
Step
0
1
2
3
A1
1
0
0
0
Step Sequence
A2
0
0
1
0
B1
0
1
0
0
B2
0
0
0
1
In the next section we will discuss about the various techniques to interface a stepper motor.
194
For example, One-step rotation of the stepper motor is used equals 2. When we program the motor for 180 steps, the
motor makes one complete revolution, i.e. 360 degree. The instruction MOV R2, #0B4H defines the rotation by 180
steps. However, one can change the number of steps in the program as per ones requirement. The following table shows
the step sequence for to energies the two coils of the stepper motor in clockwise and anti-clockwise directions. The rotor
of the stepper motor is in a position of minimum reluctance and maximum flux. Thus by energizing the windings
(represented by A1, A2, B1 and B2), the rotor takes the position accordingly. The instructions RR A and RL A are used
for clockwise and anti-clockwise, respectively.
Clockwise
Step
0
1
2
3
A1
0
0
1
1
A2
0
1
1
0
Full-Step Sequence
B1 B2 A1 A2 B1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
B2
1
0
0
1
Hex value
33H
66H
CCH
99H
CounterClockwise
MOTOR DRIVERS
The microcontroller outputs a current of 1.6 mA. To drive the coil of a stepper motor requiring a torque of 7 kg-cm, 12V
DC and 2 amp/phase, we have to use a driver circuit that amplifies the current from 1.6 mA to 3 A.
We can used BC548 and SL100 as the driver transistors for driving a low-power rated stepper motor such as floppy
drives. But for a 7 kg-cm stepper motor, a driver circuit using transistors SL100 and 2N3055 would be needed to amplify
the current to 2.72 A. Typically, SL100 and 2N3055 each has a gain () of 40, but 2N3055 can handle larger current since
it belongs to the family of power transistors. So a heat-sink is required to dissipate the heat generated.
The output gain of the Darlington pair of SL100 and 2N3055 transistors is:
o = 1 2
= 4040 = 1600
o = Io/Iin = 1600
; where Io is the output current and Iin is the input current of the Darlington
pair.
And Io = 16001.7 mA = 2.7 A
Since the stepper motor has four coils, we need to use four Darlington pairs.
When transistors conduct, +5V (Vcc) is applied to the coils and the currents flowing through them create magnetic fields
and the motor starts rotating. The magnetic field energy thus created is stored in the coils. When transistors stop
conducting, power to the coils is cut off, the magnetic field collapses and a reverse voltage (back EMF) is generated in the
coils. The back EMF can be more than 100 volts. The diodes connected across the coils (known as flyback protection
diode) absorb the reverse voltage spike. This voltage, if not absorbed by the diodes, may produce opposite torque and
cause improper rotation of the motor and also damage the transistors. We can use virtually any type of rectifier or
switching diodes of appropriate current and reverse voltage breakdown rating.
Motor Driver ICs
There are a number of ICs that can control and drive stepper motors. The ULN2003 are used as motor driver with rating
of 500 mA with 50 V output voltage and it includes internal flyback protection diodes.
The L6201 can drive motors up to 5 A with supply voltages up to 48 V. The L6201 includes internal flyback protection
diodes and includes a thermal shutdown that turns the motors off if the part overheats.
The LMD18200 from National is another motor driver IC. This part includes a pin that provides a thermal warning when
the device is about to overheat. Unlike the L6201, the LMD18200 does not require a sense resistor in the ground
connection of the driver transistors. Instead, the LMD18200 has a separate pin that mirrors the current in the H-bridge.
Example 16.3: Write a program to rotate the stepper motor clockwise continuously with full step sequence.
Solution:
MOV A, #66H
; Load full step sequence
BACK: MOV P1, A
; Send it to the motor
RR A
; Rotate right to rotate motor clockwise
ACALL DELAY
; Wait
SJMP BACK
; keep moving
DELAY: MOV R1, #64H
L2: MOV R2, #50H
L1: DJNZ R2, L1
DJNZ R1, L2
RET
Example 16.4: Write a program to monitor the status of the switch (SW). If SW = 0, motor moves clockwise and if
SW = 1, motor moves anticlockwise. Assume a switch is connected to pin P2.7.
Program:
ORG 0000H
SETB P2.7
MOV A, #66H
MOV P1, A
TURN: JNB P2.7, CW
; Monitor switch is pressed or not?
RL A
; Motor moves anticlockwise
ACALL DELAY
MOV P1, A
SJMP TURN
CW: RR A
; Motor moves clockwise
ACALL DELAY
MOV P1, A
SJMP TURN
DELAY subroutine:
Example 16.5: Write an ALP to rotate a motor 90 clockwise. Step angle of motor is 2.
Solution:
Step angle = 2
Steps per revolution = 180
No of rotor teeth = 45
For 90 rotation the no of steps is 45
Program:
ORG 0000H
MOV A, #66H
MOV R0, #45
; Initialize counter with 45 steps
BACK: RR A
MOV P1, A
ACALL DELAY
DJNZ R0, BACK
END
Example 16.6: Rotate the stepper motor continuously clockwise using half-step 8-step sequence. Use LUT.
Solution:
ORG 0000H
START: MOV R0, #08
; Initialize counter with 8 steps
MOV DPTR, #HSS
; Initialize data pointer
BACK: CLR A
MOVC A, @A+DPTR
MOV P1, A
ACALL DELAY
INC DPTR
DJNZ R0, RPT
SJMP START
ORG 0200H
HSS: DB 09, 08, 0CH, 04, 06, 02, 03, 01
END
DC MOTOR INTERFACING WITH 8051
A DC motor has a positive and negative terminal. When a DC power supply of suitable current rating is applied to the
motor it will rotate. If the polarity of the supply is switched with reference to the motor terminals, the motor will rotate in the
opposite direction. The speed of the motor is roughly proportional to the applied voltage up to the rated voltage of the
motor. Basic difference between Stepper and DC motor is stepper motor moves in steps while DC motor moves
continuously. Another difference is with stepper motor the number of steps can be counted while it is not possible in DC
motor. Maximum speed of a DC motor is indicated in RPM. The RPM is either with no load it is few thousands to tens of
thousands or with load RPM decreases with increase in load.
196
Voltage and current rating: Nominal voltage is the voltage for a motor under normal condition. It ranges from 1V to 150V.
As voltage increases, RPM goes up. Current rating is the current consumption when the nominal voltage is applied with
no load that is 25mA to a few amperes. As load increases, RPM increases, unless voltage or current increases implies
torque increases. With fixed voltage, as load increases, power consumption of a DC motor is increased.
Unidirectional Control
Figure 16.13 shows the rotation of the DC motor in clockwise and anticlockwise direction.
H-Bridge
In this bridge all transistor works as a switch and can be controlled by microcontroller port pins. If we take inputs A and
D high at the same time, transistors Q1 and Q3 both turn on and the motor turns in one direction. If B and C are both
high, the other pair turns on and the motor turns in the opposite direction.
Now, suppose the motor is turning and inputs B and D go low, then inputs A and C are both driven high. This turns
on transistors Q1 and Q4. One side of the motor will be more positive than the other; lets say it is the left side for this
example. Current will flow from the positive supply, through Q4, through the motor winding, through D2, and back to the
positive supply. The motor is effectively shorted out by Q4 and D2. This will stop the motor quickly. If the right side of the
motor is the positive one, the current will flow through Q1 and D3. If we drive inputs B and D high instead of A and
C, we get the same effect, with the current flowing through Q3/D1 or Q2/D4.
(a)
197
Figure 16.15 shows the H-Bridge motor configuration. It consists of four switches and based on the closing and opening
of these switches the motor either rotates in clockwise or anticlockwise direction. As seen in figure 16.15 (a), all the
switches are open hence the motor is not running. In b, turning of the motor is in one direction when the switches 1 and
4 are closed that is clockwise direction. Similarly, in c the switches 2 and 3 are closed so the motor rotates in
anticlockwise direction, while in figure d all the switches are closed which indicates an invalid state or a short circuit.
Example 16.7: A switch is connected to pin P1.7. Write a program to monitor the status of the SW. If SW = 0, DC
motor moves clockwise and if SW = 1, DC motor moves counter-clockwise. Use H-bridge switch circuits.
Solution: See the figure 16.15.
ORG 0000H
SETB P1.7
; Configure pin 1.7 as input pin to read switch status
L1: JNB P1.7, CLW
; Monitor switch status? if not press, jump to CLW
SETB P1.0
; otherwise move motor clockwise
CLR P1.1
CLR P1.2
SETB P1.3
SJMP L1
CLW: CLR P1.0
SETB P1.1
SETB P1.2
CLR P1.3
SJMP L1
END
Many motor H-bridge ICs include braking capability. These include the L283D and LMD18200. The L6201 has two inputs
to control the two halves of the bridge circuit. If the both inputs are brought to the same level (high or low), the driver IC
will break the motor.
The L293D is a dual H-Bridge motor driver, so with one IC we can interface two DC motors which can be controlled in
both clockwise and counter clockwise direction and if we have motor with fix direction of motion then we can make use
of all the four I/Os to connect up to four DC motors. L293D has output current of 600mA and peak output current of
1.2A per channel. Moreover for protection of circuit from back EMF output diodes are included within the IC. The output
supply has a wide range from 4.5V to 36V, which has made L293D a best choice for DC motor driver.
198
Example 16.8: A switch is connected to pin P1.7. Write a program to monitor the status of the SW. If SW = 0, DC
motor moves clockwise and if SW = 1, DC motor moves counter-clockwise. Use H-bridge IC L293D.
Solution: See the figure 16.16.
ORG 0000H
SETB P1.7
; Configure pin 1.7 as input pin to read switch status
L1: JNB P1.7, CLW
; Monitor switch status? if not press, jump to CLW
SETB P1.0
; otherwise move motor clockwise
CLR P1.1
SJMP L1
CLW: CLR P1.0
SETB P1.1
SJMP L1
END
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The main advantage of PWM is that power loss in the switching devices is very low. When a switch is off there is
practically no current, and when it is on, there is almost no voltage drop across the switch. Power loss, being the product
of voltage and current, is thus in both cases close to zero. PWM works also well with digital controls, which, because of
their on/off nature, can easily set the needed duty cycle. Using pulse width modulation has several advantages over
analog control. Using PWM to dim a lamp would produce less heat than an analog control that converts some of the
current to heat. Also, if we use PWM, the entire control circuit can be digital, eliminating the need for digital-to-analog
converters. Using digital control lines will reduce the susceptibility of your circuit to interference. Finally, motors may be
able to operate at lower speeds if you control them with PWM. When we use an analog current to control a motor, it will
not produce significant torque at low speeds. The magnetic field created by the small current will be too weak to turn the
rotor. On the other hand, a PWM current can create short pulses of magnetic flux at full strength, which can turn the rotor
at extremely slow speeds.
Servo motor
A servo motor provides a precision angular rotation for an applied pulse width modulation duty cycle. As the duty cycle of
the applied signal is varied, the angular displacement of the motor also varies. This type of motor is used to change
mechanical positions such as the steering angle of a wheel.
REVIEW QUESTIONS
1. Interface LCD display with 8051? W.A.P. to display 10 characters whose ASCII code is stored in internal memory
addressed by 20H?
2. List the various LCD command codes?
3. Draw schematic diagram to interface stepper motor with 8051 microcontroller. Define any one specification of
stepper motor.
4. Write an assembly language program to rotate stepper motor continuously, assume step angle of 1.8.
5. Indicate the steps to detect the key press in simple keyboard and matrix keyboard.
6. What is PWM, and how is it used in DC motor control?
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CHAPTER-17
INTERFACING TO EXTERNAL MEMORY
What is the purpose of interfacing circuit? The interfacing process (such as voltage, current etc.) involves matching the
memory or I/O devices signals requirements with the microcontroller signals. The interfacing circuit therefore should be
designed in such a way that it matches the memory or peripherals signals requirements with the signals of the
microcontroller. For example, for carrying out a READ process, the microcontroller should initiate a read signal (RD) which
the memory requires to read a data. In simple words, the primary function of a memory interfacing circuit is to aid the
microcontroller in reading and writing a data to the given register of a memory chip. Other reasons are incompatibility of
digital ICs and to interface an analog device to digital device. The prime function of the interfacing is to provide electrical
signal compatibility between the devices. For example: The CMOS and TTL are the two most widely used logic families.
Although ICs are belonging to the same logic family have no special interface requirements, that is, the output of one can
directly feed to the input of the other, but the same is not true if we have to interconnect digital ICs belonging to different
logic families. Incompatibility of ICs belonging to different families mainly arises from different voltage levels and current
requirements associated with LOW and HIGH logic states at the inputs and outputs. The microcontroller is a digital device
but the real world remains analog in nature i.e. the electronic world is nearly all digital, but it the real world is not. For
example, the temperature in our workplace is not just hot or cold, but varies over a wide range. We can use a
thermometer to determine what the temperature is, but how do we convert the temperature to a digital value for use in a
microcontroller-controlled thermostat? The ignition control microcontroller in our petrol vehicle has to measure the engine
speed to generate a spark at the right time. A microcontroller- controlled machine tool has to position the cutting bit in the
right place to cut a piece of steel. In such type applications, analog to digital converter and digital to analog converter
needed to interface.
Consider that we have a microcontroller interfaced to both the input and output device and also a memory chip. Now, how
a user selects the devices according to the requirement of operations? For this purpose an address decoding circuit is used.
An address decoding circuit aids in selecting the required I/O device or a memory chip.
DECODER
The simplest method of address decoding circuitry is the use of NAND gate with active low output and fortunately the chip
select (CS) of memory IC also active low makes them a perfect match. In cases where the CS input is active high an AND
(NAND + inverter gate) must be used. Using a combination of NAND gates and inverters, one can decode any address
range. For example: figure 17.1 shows that A15-A12 must be 00112 in order to select Chip (CS). The address lines A0-A11 are
decoded by internal decoder of memory IC. This result in the given assignment of address 3000H to 3FFFH to this memory
chip.
A0-A11
A0-A15
From
Microcontroller
A0-A11
4Kx8
A12
A13
A14
A15
D0-D7
CS
RD
WR
RD
W R
Figure 17.1: Address decoding using NAND gate as a decoder
(a)
201
A0-A11
A 3X8
B DECODER
C
G2A
G2B
G1
A13
A14
A15
GND
VCC
4K8
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
CS
RD
D0-D7 to microcontroller
data bus
D0-D7
WR
(b)
RD
W R
Figure 17.2: (a) 74LS138 decoder (b) interfacing between microcontroller and memory through 74LS138 decoder
Table 17.1: Functional table for 74LS138 decoder
X
0
1
1
1
1
1
1
1
1
1
X
0
0
0
0
0
0
0
0
1
X
0
0
0
0
0
0
0
0
Input
C B A
X
X
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
Output
Y0
1
1
0
1
1
1
1
1
1
1
X
X
0
1
0
1
0
1
0
1
Y1
1
1
1
0
1
1
1
1
1
1
Y2 Y3 Y4 Y5
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 1 1 1
1 0 1 1
1 1 0 1
1 1 1 0
1 1 1 1
1 1 1 1
Y6
1
1
1
1
1
1
1
1
0
1
Y7
1
1
1
1
1
1
1
1
1
0
CLK
CLK
Low
High
High
D(I/P)
X
0
1
Q(O/P)
No change
0
1
Example for the D-flip-flop/Latch, the device 74ALS373 is the octal D latch with tri-state buffers and requires
inputting control signal clock (CLK) and output enable/control (OE). When the clock input signal is high, the
data changes in flip-flops corresponding to data line. When clock input goes low, data latched at the output of
a latch. The output control signal is active low and it enables the tri-state buffers to send output signal to the
output devices (LED display) as shown in figure 17.4.
Data line (1 or 0)
Enable
D
Latch
CLK
Q
LED
output control (OE)
202
Output
(OE)
control
0
0
0
1
Clock(E)
Q (output)
1
1
0
x
1
0
x
x
1
0
Previous state (data hold)
High impedance
word 0
word 1
word 2
word 3
word 4
word 5
word 6
word 7
1000
1001
1010
1011
1100
1101
1110
1111
word 8
word 9
word 10
word 11
word 12
word 13
word 14
word 15
Example 17.2: How much number of registers, memory cells, flip-flops and bits can be stored in a 644 memory chip? Also how
many address lines are needed to address the registers/locations of chip and data lines to access data?
Solution: The memory chip store the information in organized array of addressable locations.
The size of the memory chip is described by the two number M and N as M N. Where M specifies the number of word (locations or
register) in the memory chip and N specifies the number of bits in the word (locations or register).
In this example memory size is 644 i.e. the number of registers or word are 64 and each register is 4-bit wide; therefore, the total number
of bits can stored or capacity of memory in it is 64x4=256 bits.
The memory cell is a flip-flop and it can store only one bit. Hence, the number of flip-flops=256.
The number of address lines are X=log264=6.
The number of data lines are equal to N=4.
Example 17.3: A memory has size or capacity of 8Kx8. Find the number of data I/O lines and address lines.
Solution: The word size given in example is 8-bit. Therefore, the numbers of data I/O lines are 8 and the total number of words=8K =
81024 =8192. Thus number of register addresses are 8192 and number of address lines are required for decoder to address 8192 locations
are 213=8192 or X=log28192=13. Hence 13 address lines are required.
MEMORY EXPANSION
The expansion of the memory in terms of the number of words or word size or both is recommended, where
single chip IC not satisfies these two requirements. Therefore, several ICs can be connected to expand
memory capacity. The possibilities of expansion are
1. Expanding word size or word width
2. Expanding number of words or word capacity
3. Expanding both, word size and capacity
203
Expanding Word Size: If it is required to expand the memory word size to n and word size of the available memory ICs
is N (n>N), N should be a multiple of n, so that a number of similar ICs can be combined together to get desired word size.
The number of ICs required is an integer next higher to the value n/N. For example: suppose we have memory ICs with 4bit word width wide each and want to expand word size 8-bit. To design 8-bit word size memory from 4-bit word size
memory we need two similar 4-bit word size ICs and connect them as shown in figure 17.5. The procedure to connect two
or more ICs to expand word size as follow:
1. Connect the corresponding address lines of each location of IC individually.
2. Connect the control I/O signal lines (active low RD and WR enable) of each memory together.
As a result the number of data (I/O) lines will be equal to the product of the number of memory ICs used and word size of
the memory chip. Figure 17.5 shows two 84 memories being used to expend of size of 88 memory. The corresponding
address lines are common so that any address activates each row of same number in each memory and produces an 8-bit
word.
A0
A1
A2
Address
Decoder
74LS138
(38)
RD Enable
W R Enable
84
84
RAM/ROM
RAM/ROM
D7 D6 D5 D4
D3 D2 D1 D0
Expanding number of words: Memory ICs can be combined together to expand number of words or number of registers
of the memory i.e. to get desired numbers of address locations of a memory. In order to expand a memory of capacity m
words by using ICs which have M words capacity. The number of ICs required is an integer higher next to value m/M.
These ICs are connected as:
(i) Connect the corresponding address lines of each IC individually.
(ii) Connect the control inputs (RD, WR, CS etc.) of each IC together.
(iii) Use a decoder of proper size and connect each of its outputs to one of the CS terminals of memory IC.
Figure 17.6 shows that how two 8x4 memory ICs are connected together to make 16x4 memory size.
A0
A1
A2
Address
Decoder
74LS138
(3x8)
8x4
8x4
ROM/RAM
(Chip-1)
CS
A3
ROM/RAM
(Chip-2)
CS
RD enable
W R enables (not for ROM)
D3 D2 D1 D0
Figure 17.6: Designing a 16x4 memory by using two 8x4 memory ICs
204
When CS=0, memory get activated; if A3=1, the left memory (chip-1) activated and if A3=0, the right memory (chip-2) activated. Thus four
address lines addressed 8 locations from 0000 2 to 01112 for right memory, and for left memory four address lines addressed another eight
location from 10002 to 11112 and share common I/O word bits from D0 to D3.
Expanding word size and words number: The word size and word numbers can be expand by combining the two above configurations.
Figure 17.7 shows, the four 8X4 memory ICs are combined together to get a 16x8 memory size.
RD Enable
W R Enable
A0
A1
A2
RD
Address
Decoder
74LS138
(3x8)
WR
RD
WR
8x4
8x4
ROM*/RAM
ROM*/RAM
CS
CS
A3
RD
WR
RD
8x4
WR
8x4
ROM*/RAM
ROM*/RAM
CS
CS
D7 D6 D5 D4
D3 D2 D1 D0
* if we extend ROM memory not need of WR enable signal line, on the other hand to extend RAM both WR enable as well as RD enable lines are needed.
Figure 17.7: Designing a 16x8 memory by using four 8x4 memory ICs
Example 17.4: The memory chip size is 1024 4 bits. How many chips are you needed to make a 16K byte memory? How many
address lines are needed to address 16K byte memory?
Solution: The number of bits in 16K byte= 16 1024 8 bits.
The size of available memory ICs=1024 4 bits.
Total number of ICs required = (16 1024 8) / (1024 4) = 32 ICs are needed.
The number of address lines to address 16K byte memory= 16 1024=16384=214 = 16384
Hence, X=log216384=14 address lines are required to address 16384 memory locations.
205
address, the 8051 microcontroller make use of 16 address lines to identify unique memory location in the
system. That means some address lines are used to identify which memory IC to be access while remaining
address lines select the exact memory location to read or write into. As shown in above figure 17.7; A3 used to
access particular memory IC, while A0, A1 and A2 used to find exact location for read-write operation.
Example 17.5: The 8051 microcontroller has 16 address lines and RD line. Four 4Kx8 ROMs are to be connected to it to make
16K8 size of memory. Design the decoding scheme and give the memory map also.
Solution: For 4K8 ROM ICs, each IC requires 12 address lines for addressing internal memory locations i.e. from A0 to A11 and
remaining address lines from A12 to A15 are used for chip selection by making use of IC 74138 decoder. A memory IC requires a Chip
select (CS) input signal to wake up the chip.
The 8051 microcontroller has 16-bit address lines/Bus, some of these 16 lines are used to chip select or activate CS through an interfacing
logic/decoder such as NOT/NAND gate or 74138 address decoder IC and Remaining address lines are used to locate register within
selected memory IC through an internal address decoder. The memory map is given below:
Memory address
From
To
0000H
1000H
2000H
3000H
0FFFH
1FFFH
2FFFH
3FFFH
Figure 17.8: Interfacing with microcontroller/address decoding of memories through 74LS138 decoder
206
Example 17.6: What change has to be made if only one 4Kx8 ROM IC used instead of four IC in above example 17.5?
Solution: The address lines A0- A11 used for find memory location and remaining address line A12-A15 used for chip select.
Address decoding Scheme
The previous example specified that all addressable memory space was to be implemented but there are some situations
where this requirement is not necessary or affordable. If only a portion of the addressable space is going to be
implemented there are two basic address decoding strategies:
(i) Full address decoding
Since not all the address space is implemented, only a subset of the address lines are needed to point to the
physical memory locations.
Each physical memory location is identified by several possible addresses (using all combinations of the address
lines that were not used).
We can summarize that how to decode particular memory location is selected from memory ICs.
1. How the particular memory IC selects and how the particular location (register) selects from the selected IC
memory? The address lines used to identify a particular memory location/register within memory IC. However, few
address lines may be used to identify memory chip by CS(Active low chip select) through NOT/NAND (Interfacing
device) gate or using decoder IC and remaining address lines are used to identify particular location of register
through internal address decoder within selected memory by enabling (Latch Enable) registers Latches.
2. How the read/write operation performed on selected register? After selection of register location of memory,
microcontroller issue control signal RD or WR signal to enable read (output enable OE) or write Tristate buffer
(write enable WE) of memory IC respectively. The contents of selected registers bits put on data lines/bus and
vice versa. Hence, microcontroller gets or sends data via data bus through tri-state buffer from/to memory.
Example 17.7:
1. Calculate the address lines required for an 8K-byte memory chip.
2. Calculate the number of memory chips needed to design 8K-byte memory if the memory chip size is 10241.
Solution:
1. The 8K byte of memory has 81024=8192 memory locations. Number of address lines are required X=log 28196=13. Hence, 13
address lines are required to addressing of 8K-Byte of memory.
2. The total number of chips are (810248) / (10241) = 64. Hence, the 64 chips of 10241 size are needed to design 8K-Byte
memory.
Example 17.8: How many memory locations are possible with the address lines (a) 8 (b) 12 (c) 16?
Solution:
(a) With 8 address lines there will be total 2 8 i.e. 256 memory locations from 00H to FFH.
(b) Similarly, with 12 address lines there will total be 212 i.e. 4096=4K memory locations from 000H to FFFH.
(c) With 16 address lines there will be total 216 i.e. 65536=64K memory locations from 0000H to FFFFH.
Example 17.10: (a) How many 1288 RAM chips are required to provide a memory capacity of 2048 bytes?
(b) How many address lines/Bus must be used to access 2048 bytes of memory? How many lines of these will be common to each
chip?
(c) How many address lines must be decoded for chip select? What is the size of decoder?
Solution: (a) Number of chips required=2048/128=16.
(b) Address lines for 2048 bytes will be X=log22048=11.
Address lines for 128 bytes will be X=log2128=7. Thus, seven address lines are common.
(c) The number of address lines to be decoded will be 11-7=4 so the size of decoder will be 4 to 16.
Example 17.11: The memory address of the last location of a 2K byte memory chip is F000H. Find starting address of the memory
chip.
Solution: the total locations of 2K byte memory are 2048 or 800H.
Number of address lines to address 2K memory location are 11.
Address location range from 000H to 7FFH, but given last location of the memory F000H.
Therefore, Starting address equal to F000H 7FFH=E801H.
207
EA
P2.0-P2.7
ALE
P0.0-P0.7
74LS373
Latch
8051/31
A7
A6
A5
A4
A3
A2
A1
A0
D7-D0
~IOR
P3.6
P3.7
PSEN
WR
RD
PSEN
Data bus
Write strobe
Read strobe
Figure 17.10: Data, address and control buses to external memory access for the 8051/31
208
The external memory is always accessed with 16-bit addresses. Accesses to external Data Memory can use either a 16-bit
address (MOVX @DPTR) or an 8-bit address (MOVX @Ri). Whenever a 16-bit address is used, the high byte of the address
comes out on Port 2, where it is held for the duration of the read or write cycle.
Note that the Port 2 drivers use the strong pull-ups during the entire time that they are emitting address bits that are 1s. This is
during the execution of a MOVX @DPTR instruction. During this time the Port 2 latch (the Special Function register) does not
have to contain 1s, and the contents of the Port 2 SFR are not modified. If the external memory cycle is not immediately
followed by another external memory cycle, the undisturbed contents of the Port 2 SFR will reappear in the next cycle. If an 8bit address is being used (MOVX @ Ri), the contents of the Port 2 SFR remain at the Port 2 pins throughout the external
memory cycle. This will facilitate paging.
In any case, the low byte of the address is time-multiplexed with the data byte on Port 0. The address/data signal drives both
FETs in the Port 0 output buffers. Thus, in this application the Port 0 pins are not open-drain outputs, and do not require
external pull-ups. Signal ALE (address latch enable) should be used to capture the address byte into an external latch. The
address byte is valid at the negative transitions of ALE. Then, in a write cycle, the data byte to be written appears on Port 0 just
before WR signal is activated, and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted
at Port 0 just before the read RD signal is deactivated.
During any access to external memory, the CPU writes 0FFH to the Port 0 latch (the Special Function Register), thus
formatting whatever information the Port 0 SFR may have been holding.
EA (External Access) pin
When EA pin is connected to ground, to indicate that, the program (hex code) is stored in external ROM. If we connect EA pin
to Vcc, it indicates that the program code is stored in the on-chip ROM of the 8051.
However, external program Memory is accessed under two conditions:
1. Whenever signal E A is active low (EA=0) or
2. Whenever the program counter (PC) contains a number that is larger than the on-chip memory size. In other word, if EA=1,
the internal program memory is accessed for the on-chip address range 0000H to 0FFFH (8051) and the external program is
accessed for addresses greater than 0FFFH (8051).
This requires that the ROM-less versions (8031) have EA wired low (EA=0) to enable the program code to be fetched from
external memory.
PSEN (Program store enable) pin
This is an output signal and must be connected to OE pin of an external ROM. The read signal for program code from external
ROM fetches is PSEN. PSEN is not activated for internal fetches. When the CPU is accessing external Program Memory,
PSEN is activated twice every machine cycle (except during a MOVX instruction) whether or not the byte fetched is actually
needed for the current instruction. In the 89C51/8751 based system, EA is connected to Vcc, these chips (has programmable
ROM) do not activate the PSEN signal to read.
ALE (Address Latch Enable) pin
The main function of ALE is to provide a properly timed signal to latch the low byte of an address from P0 to an external latch
during fetches from external Program Memory. For that purpose ALE is activated twice every machine cycle. This activation
takes place even when the cycle involves no external fetch. The only time an ALE pulse doesnt come out is during an access
to external Data Memory. When ALE=0, port 0 is used as data bus and if ALE=1, port 0 is used as address bus.
EXTERNAL PROGRAM ROM INTERFACING
External ROM for code
To access code from external program memory a required circuit arrangement as shown in figure 17.11. When EA pin is
connected to ground, the 8051/31 fetches op-code from external ROM by using PSEN. Connecting E A to ground will disable
the internal program memory and enable external program memory access. In the 89C51/8751 based system, EA is
connected to Vcc.
In 8051, each machine cycle has six states. Each state has two clock periods. Port 0 acts as a multiplexed address/data bus,
sending the lower byte of the PC (PCL) as an address and then waiting for the arrival of the code byte from external memory.
209
The signal ALE clocks the PCL byte into the address latch during the period of time that the PCL byte is valid on port 0. The
latch will hold the low address byte stable at the input to the external memory while the multiplexed bus is made ready to
receive the code byte from the external memory. Port 2 sends the PC higher byte (PCH) directly to the external memory; the
signal PSEN then strobes the external memory allowing the code byte to be read by the microcontroller (see figure 17.12).
Figure 17.12: Timing diagram for external program memory access (without MOVX)
To access data from external program memory a required circuit arrangement as shown in figure 17.13. To access the data
from ROM, the RD signal is connected to OE pin of data containing ROM. Notice the function of PSEN and RD, PSEN is used
to access the code while RD is used to access data in external ROM.
We are used an instruction MOVC A, @A+DPTR to access data from code space in (external or internal) ROM. To access the
external data from ROM, we must use the instruction MOVX A, @DPTR; this instruction read the data from ROM location
which is pointed by DPTR.
Figure 17.14: Timing diagram for external data access (with MOVX)
210
external RAM, respectively (see figure). To read and write data byte in the external RAM, we use the instruction MOVX A,
@DPTR and MOVX @DPTR, A.
A typical timing diagram for a read cycle from external memory is shown in figure 17.16. The timing for a write cycle is similar
except that the WR line pulses low, RD stays high and data is placed on port 0 lines as an input to the microcontroller.
Figure 17.16: Timing diagram for a read cycle from external memory
Example 17.9: Interface 16KB EPROM and 48 KB SRAM to 8051 with the help of 8KB EPROM ICs and 8KB SRAM ICs. Draw
the address map and show the address decoding logic.
Solution: Number of EPROM chips required=16KB/8KB=2 and the number of SRAM chips required=48KB/8KB=6.
So, total number of memory ICs are needed =8.
Each 8Kx8 EPROM or SRAM IC requires 13 address lines (213=8K) for addressing internal memory locations i.e. from A0 to A12 and
remaining address lines from A13 to A15 are used for eight ICs selection (23=8) by making use of 74138 decoder IC.
The 8051 microcontroller has 16-bit address lines that can address 64K memory location (0000H to FFFFH), 3 address lines (A13 to A15) of
these 16 lines are used to chip select (CS) through an interfacing logic/decoder 74138 address decoder IC and Remaining address lines (A 0
to A12) are used to locate register within selected memory IC through an internal address decoder. The schematic for memories decoding
and memory addressing is shown in figure 17.17. Memory map or memory address range is given in following table: Memory IC
number
1 (EPROM)
2 (EPROM)
3 (SRAM)
4 (SRAM)
5 (SRAM)
6 (SRAM)
7 (SRAM)
8 (SRAM)
Memory address
From
0000H
2000H
4000H
6000H
8000H
A000H
C000H
E000H
To
1FFFH
3FFFH
5FFFH
7FFFH
9FFFH
BFFFH
DFFFH
FFFFH
211
W R (P3.6)
RD (P3.7)
A0-A12 from microcontroller
A0-A11
OE
WE
8Kx8(EPROM-1)
CS
D0-D7
3X8
DECODER
A13-A15 from
microcontroller
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A0-A11
OE
WE
8Kx8(EPROM-2)
CS
D0-D7
A0-A11
CS
A0-A11
CS
A0-A11
CS
A0-A11
CS
A0-A11
CS
A0-A11
CS
OE
8Kx8(SRAM-3)
WE
D0-D7
OE
8Kx8(SRAM-4)
WE
D0-D7
RD
8Kx8(SRAM-5)
WE
D0-D7
OE
8Kx8(SRAM-6)
WE
D0-D7
OE
8Kx8(SRAM-7)
WE
D0-D7
OE
8Kx8(SRAM-8)
WE
D0-D7
Figure 17.17: Interfacing of 16KB EPROM and 48KB SROM with the 8051
REVIEW QUESTIONS
1.
2.
3.
4.
5.
6.
7.
8.
9.
212
D0-D7 to
microcontroller
data bus
CHAPTER-18
THE 8051/31 INTERFACING WITH 8255 (EXPENDING I/O PORTS)
In this chapter we will study the 8255 programmable-peripheral-interface chip, one of the most widely used
parallel I/O chip.
27-34
36
35
Group A
Control
Group B
Control
Group A
Port A
(8-lines)
I/O
Group B
Port C
(Upper 4-lines)
Group A
Port C
(Lower 4-lines)
I/O
I/O
Pin 17-14 for PC3-PC0
Group B
Port B
(8-lines)
I/O
pin 25-18 forPB7-PB0
Figure 18.1: Functional Block diagram for 8255 PIO (Programmable input/output port)
213
The 8255 signals (pins) and blocks description (shown in figure 18.1 and 18.3 (b)) are as follow:
PA7-PA0: These are 8 lines of port A that works as either latched output or externally buffered input lines, I/O
operation depends upon control word register contents.
PC7-PC4: Upper 4 lines of port C that acts as either latched output or externally buffered input lines. This port
can also be used as handshaking signal lines to provide synchronization between two devices in mode-1 and
mode-2.
PC3-PC0: These are lower 4 lines of port C and work same as PC7-PC4 lines.
PB7-PB0: These are the 8 lines of port B and work same as PA7-PA0 lines.
RD: This is a control signal driven by microcontroller and should be low to perform the read operation from a
selected I/O port depending upon the control word loaded into the control word register (CWR).
WR: This is another control signal driven by microcontroller to enable the write operation. When this signal is
active low, it performs write operation into selected I/O port depending upon the control word loaded into the
control word register (CWR).
CS: This is chip select signal. This signal line is connected to the address lines of microcontroller through
interface such as address decoder. If this line goes low it enables the 8255 to respond to RD and WR signal
otherwise read or write operation cannot be performed.
A1-A0: These are the address input lines driven by the microcontroller. The three lines, CS, A0, and A1 together
specify addressing of one of the four I/O port and control word register as given in table 18.1 and shown in
figure 18.2:
Table 18.1: 8255 port selection
CS
0
0
0
0
1
A1
A0
Specification
0
0
1
1
x
0
1
0
1
x
Port A selected
Port B selected
Port C selected
control word register (CWR) selected
8255 not selected
Port A
A0
A1
Internal
decoder
(8255)
00
01
10
11
Enable
Port B
CS
Enable
Control word
Register
Port B
Enable
Enable
WR
RD
Figure 18.2: ports and control register selection
For the read/ write operation for 8255, A1, A0, RD, and WR lines works together and performs read/ write
operation with four ports and control word register as shown in table 18.2.
214
RD
0
0
0
0
1
1
1
1
X
1
WR
1
1
1
1
0
0
0
0
X
1
CS
0
0
0
0
0
0
0
0
1
0
A1
0
0
1
1
0
0
1
1
X
X
A0
0
1
0
1
0
1
0
1
X
X
RESET: This is logic high signal to clear the control word register of 8255. All ports are set as input port by
default after resting.
D7-D0: These are the data lines used to carry data or control word from/ to microcontroller.
CS
D7-D0
RD
WR
A0
A1
PA7-PA0
8
2
5
5
PB7-PB0
PC7-PC0
RESET
(a)
(b)
Figure 18.3 (a) The 8255 block diagram (b) The 8255 pin diagram
Group A and Group B control: The two 8-bit ports (port A and Port B) and two 4-bit ports (upper port CU and
lower port CL of port C) are divided into two groups on the basis of their control, group A and group B.
Group A consists of port A and CU, while group B contains port B and CL. The control word is given to CWR
that control the mode of operation of both groups.
Control word register: This is an 8- bit register used to specify an I/O function for each port. The contents of
this register known as control word. The control word can be written (but not read) when A0 and A1 are at
logic high as mention in above table. An appropriate control word is to be written on control register to select
the operation mode of the four ports to read (input) or write (output) data. The ports of the 8255 can be
programmed in any of the following four modes.
Modes of operation: The two basic modes of 8255 are bit set/reset (BSR) mode and I/O mode. The I/O mode
is further divided in mode-0, mode-1 and mode-2.
215
Operation modes
I/O mode
Mode-0
All ports Simple I/O
Mode-1
Port A and port B
Handshake with
I/O Devices, and
Handshaking signals
Provided by port C
Mode-2
Port A as bidirectional I/O
port with handshaking
capabilities whose signals
are provided by port C.
port B either in simple I/O
Mode (mode-0) or
Handshake (mode-1)
There are two types of control word format one for Bit set/reset mode of operation and other for I/O modes
(Mode-0, mode-1 and mode-2) of operation. The D7 bit of control word specify either the I/O mode or Bit set/
reset (BSR) mode.
BSR mode: In BSR mode only port C is involved and individual bit of port C can be programmed to function as
input or output.
I/O modes: All ports can be selected and whole port can be made to work as input/output port but not
individual bit of any port can be made I/O.
Mode-0 (simple I/O): In this mode, any of the ports A, B, CL and CU can be programmed as input or output.
The vast majority of application involving the 8255 uses this simple I/O mode.
Mode-1: In this mode, port A and port B can be used as input or output with handshaking capabilities.
Handshaking signals are provided by the bits of port C.
Mode-2: In this mode, port A can be used as a bidirectional I/O port with handshaking capabilities whose
signal is provided by port C. Port B can be used either in simple I/O mode or handshaking mode.
Mode selection of the 8255
The bit wise specification and the format of control word to select mode of operation is given in figure 18.4:
D7
1-I/O mode
0-BSR mode
D6
D5
D4
D3
D2
D1
D0
Mode selection of
Group-B
0-mode 0
1-mode 1
Mode selection of
Group-A
Port A
1-input
0-output
00-mode 0
01-mode 1
0x-mode 2
Group A
Port CU
1-input
0-output
Port CL
1-input
0-output
Port B
1-input
0-output
Group B
Bit Set/Reset mode (BSR): BSR mode is selected by reset (set to 0) the D7 bit of CWR. The BSR mode
concerns only with any bit of two 4-bit ports (CU and CL) can be set (read or input) or reset (write/output) is
216
depending on D0 of the control word. Any one bit from PC0 to PC7 of port C can be selected by bit select flags
D3, D2 and D1 of the CWR as given in figure 18.5.
Salient feature of the BSR mode:
1. Only the individual bit of port C (two 4-bit ports CU and CL) can be made input or output at a time,
according to control word i.e. single bit control of port C at a time.
2. O/P lines are latched, and I/P lines are not latched but can be externally buffered.
3. Only one 8-bit port is available, so that eight input or/and eight output configuration are possible.
4. BSR control word does not affect any previously I/O mode of operations of Port A and Port B.
D7
D6
D5
D4
D3
D2
D1
D3
D2
D1
000-PC0
001-PC1
010-PC2
011-PC3
100-PC4
101-PC5
110-PC6
111-PC7
D0
S/R
D7
0
0
D6
0
1
D5
0
1
D4
0
1
D3
1
1
D2
0
0
D1
1
1
D0
1 = 0BH
1 =7BH
D2
0
0
D1
1
1
D0
0 = 0AH
0 =7AH
D7
0
0
D6
0
1
D5
0
1
D4
0
1
D3
1
1
To set PC5 bit control word register loaded with 0BH or 7BH control word, and to reset CWR is loaded with 0AH or 7AH
control word.
Note: To set or reset bits of port C, a control word is written in the control register and not in port C and control word affects only one bit
in port C.
217
In absolute memory mapped I/O addressing technique, the 16-bit address lines of 8051 microcontroller are used.
The A0 and A1 are used to select port and control word register within chip and 8255 chip is selected by CS signal
which is generated using remaining 14 address lines from A18 to A2. However, any two address lines can be used
for port/register selection, and remaining 14 address lines for chip select. The RD (P3.7) and W R (P3.6) signal
from microcontroller to connect with RD and W R pins of the 8255, respectively. For example, see the following
table, the 14 address lines are used to generate CS signal to chip select and remaining two lines are used to
select ports and CWR in 8255 chip:
A18
1
1
1
1
CS (chip select)
A14 A13 A12 A11 A10 A9 A8
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
Port/register selects
A7 A6 A5 A4 A3 A2
A1 A0
0 0 0 0 0 0
0 0
0 0 0 0 0 0
0 1
0 0 0 0 0 0
1 0
0 0 0 0 0 0
1 1
HEX address
Port/register
8000H
8001H
8002H
8003H
Port A
Port B
Port C
CWR
The detailed interfacing diagram using above table is given in figure 18.6:
(P2.7) A18
A14
(P2.0) A8
ALE
A14
A8
CLK
~Q
AD7-AD0
(P0.0-P0.7)
8
0
5
1
Microcontroller
CS
A1
8
2
5
5
A0
PPI
A7
A2
74LS373 Latch
PA
D7-D0
PB
PC
(P3.7) R D
R D
(P3.6) WR
WR
RESET
Figure 18.6: Interfacing of 8051 with 8255 using absolute memory mapped I/O technique
2. Calculate a control word in control word register according to the application of mode of operations.
3. Write program to interface (communicate) with peripheral through port A, B and C.
Example 18.2: Interface the 8051 to the 8255, and write program PC3 bit/line of the 8255 to generate a square
waveform of time period 100 ms continuously.
Solution:
Step-1: Here, We are using partial memory mapped I/O technique to interface the 8051 with the 8255. Assume Control
word register address=0BH. Therefore, the value of address lines from A7 to A0 are 00001011 (0BH) in which A1 and A0
used to select control register and A7 to A2 used to select chip (CS) as shown in figure 18.7:
218
ALE
AD7-AD0
(P0.0-P0.7)
8
2
5
5
A0
A1
74LS373
Latch
A2
A3
A4
8
0
5
1
Microcontroller
CS
PPI
A7
D7-D0
PC3
(P3.7 )R D
R D
(P3.6) WR
WR
RESET
Step-3: Program:
BACK: MOV A, #07H
; Load control word to set PC3 in Accumulator
MOV R0, #0BH
; Load CWR address
MOVX @R0, A
; Write control word in control register which is set PC3 bit i.e. PC3=1
CALL DELAY
; Call delay subroutine for 50ms time delay
MOV A, #06H
; Load control word to Reset PC3 in Accumulator
MOVX @R0, A
; Reset PC3=0
SJMP BACK
; Infinite loop
To generate a pulse of 100 ms time period just write END in place of SJMP BACK instruction.
Example 18.3: Write a program to set bits PC5 and PC3 and reset them after 50 ms. Assume control register
address is 83H.
Solution:
MOV A, #0BH
MOV R0, #83H
MOVX @R0, A
MOV A, #07H
MOVX @R0, A
CALL DELAY
MOV A, #0AH
MOVX @R0, A
MOV A, #06H
MOVX @R0, A
END
I/O MODES
The CWR of the 8255 can be programmed in any of the following modes.
Mode-0 (Simple I/O mode): in this mode, data can be simply read from and write to the each of the
three ports. Control word format (refer figure 18.5) for this mode as given in figure 18.8:
The salient features of mode-0 are as follows:
1. Each of the four ports (two 8-bit ports A and B, port CU and CL are two 4-bit port of port C) can
used as simple input or output. However, two 4-bit ports can be used in combination to make third
8-bit input or output port C.
2. Input lines are not latched but can be buffered externally. O/P are latched that O/P data remain on
ports until next byte of data write on ports.
219
3. In this mode, the ports are not capable to handshake or interrupt driven because all bit of each
port are in or all bits are out i.e. individual bit cannot be controlled in this mode.
Note: A given port cannot be used as both an input and output port at the same time.
D4
D3
D1
D0
Mode selection of
Group-B
1-I/O mode
0-mode 0
Mode selection of
Group-A
00-mode 0
Port A
1-input
0-output
Port CU
1-input
0-output
Port CL
1-input
0-output
Port B
1-input
0-output
Example 18.4: Find the control word of the 8255 for the following configurations (mode-0):
a. All the ports of A, B and C are input ports.
b. Port A and port C upper input, Port B and port C lower output.
Solution: From figure 18.8, we get:
a. 10011011=9BH
b. 10011000=98H
Example 18.5: For the figure 18.9.
(a) Find the I/O port address assigned to ports A, B, C and control word register.
(b) Program the 8255 for ports A, B and C to be output ports.
(C) Write a program to generate square wave to all port bits continuously.
ALE
AD7-AD0
(P0.0-P0.7)
8
2
5
5
A0
A1
74LS373
Latch
A4
8
0
5
1
Microcontroller
CS
PPI
PA
D7-D0
PB
PC
(P3.7) R D
R D
(P3.6) WR
WR
RESET
Solution: (a) Notice the RD, W R and CS signal in figure 18.9, given configuration is a partial memory mapped I/O
scheme. Find the port and CWR addresses from figure 18.8. The base address of 8255 is given below:
220
CS (chip select)
A7 A6 A5 A4 A3
0 0 0 1 0
0 0 0 1 0
0 0 0 1 0
0 0 0 1 0
A2
0
0
0
0
Port/register selects
A1 A0
0 0
0 1
1 0
1 1
HEX address
10H =Port A
11H =Port B
12H =Port C
13H =CWR
(b) Calculate control word to make all ports as output from figure 18.8, we get: 10000000B=80H
Program:
MOV A, #80H
; Load A with control word
MOV R0, #13H
; Load CWR address
MOVX @R0, A
; Write control word in the control register
END
(c)Program to generate square wave on 8255 ports:
MOV A, #80H
; Load A with control word
MOV R0, #13H
; Load CWR address
MOVX @R0, A
; Write control word in the control register
MOV A, #55H
; A=55H
BACK: MOV R0, #10H
; Load port A address
MOVX @R0, A 10H
; Write Accumulator in the port A
INC R0
; Port B address
MOVX @R0, A
; Write Accumulator in the port B
INC R0
; Port C address
MOVX @R0, A
; Write Accumulator in the port C
CALL DELAY
; Wait
CPL A
; Toggle bits of Accumulator
SJMP BACK
; Continue (infinite loop)
Port A,
Port B
And
Port C
Example 18.6: For figure 18.10, (a) Find the I/O port address assigned to ports A, B, C and control word register.
(b) Program the 8255 for ports A, B and C to be output ports. (C) Write a program to generate square wave to all
port bits continuously.
(P2.7)
A18
CS
8
2
5
5
ALE
AD7-AD0
(P0.0-P0.7)
8
0
5
1
Microcontroller
CLK
~Q
PPI
74LS373 Latch
A1
A0
PA
D7-D0
PB
PC
(P3.7) R D
R D
(P3.6) WR
WR
Figure 18.10: Interfacing of the 8051 with the 8255
221
RESET
Solution: (a) Notice the RD, WR and CS signal in figure 18.10; this is a partial memory mapped I/O scheme. Now find
the ports and CWR addresses. The base address of 8255 is as follow:
CS (chip select)
A18 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
1 x x x x x x x x x x x x x
1 x x x x x x x x x x x x x
1 x x x x x x x x x x x x x
1 x x x x x x x x x x x x x
Port/register selects
A1 A0
0 0
0 1
1 0
1 1
HEX address
8000H or FFFCH=Port A
8001H or FFFDH= Port B
8002H or FFFEH=Port C
8003H or FFFFH=CWR
(b) Calculate control word to make all ports output from figure 18.8: we get, 10000000B=80H.
Program:
MOV A, #80H
; Load A with control word
MOV DPTR, #8003H
; Load CWR address
MOVX @DPTR, A
; Write control word in the control register
END
(c)Program to generate square wave on the 8255 ports:
MOV A, #80H
; Load A with control word
MOV DPTR, #8003H
; Load CWR address
MOVX @DPTR, A
`
; Write control word in the control register
MOV A, #55H
; A=55H
BACK: MOV DPTR, #8000H
; Load DPTR with port A address
MOVX @DPTR, A
; Write A in the port A
INC DPTR
; Port B address
MOVX @DPTR, A
; Write A in the port B
INC DPTR
; Port C address
MOVX @DPTR, A
; Write A in the port C
CALL DELAY
; Wait
CPL A
; Toggle
SJMP BACK
; Loop
Port A,
Port B
And
Port C
Example 18.7: (a) Interface the 8255 with 8051 microcontroller for the addresses of port A, B, C and CWR are
2000H, 2001H, 2002H and 2003H, respectively.
(b) Write control word to make port A=input, port B and port C=output.
(c) Write a program to get data from port A and send it to both ports B and C.
Solution:
(a) We can use either partial or absolute memory mapped I/O technique. The detailed interfacing diagram is given in
figure 18.11. We are using absolute addressing to map 8255 as given below:
CS (chip select)
A18 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0 0 0 0 0
Port Select
A1 A0
0 0
0 1
1 0
1 1
Port/Register selects
2000H=Port A
2001H=Port B
2002H=Port C
2003H=CWR
(b) Calculate control word to make port A input and port B and C output from figure 18.9: Control word is 10010000=90H.
222
(c) Program:
ORG 0500H
MOV A, #90H
MOV DPTR, #2003H
MOVX @DPTR, A
MOV DPTR, #2000H
MOVX A, @DPTR
INC DPTR
MOVX @DPTR, A
INC DPTR
MOVX @DPTR, A
END
Note: For a memory-mapped I/O device, the peripheral (8255) device is treated as a memory location in the External memory map. In
other word, the addresses of 8255 chip, ports and CWR cannot be used for data memory access. For example: In above program if we
store this program from 2000H (start with ORG 2000H) memory location, then this program is not work because of same addresses of
port A and program.
A18
A14
A13
A12
A8
ALE
CS
CLK
~Q
AD7-AD0
From 8051
A1
8
2
5
5
A0
PPI
A7
A2
74LS373 Latch
PA
D7-D0
PB
PC
R D
R D
WR
WR
RESET
Figure 18.11: Interfacing of 8051 with 8255 using absolute memory mapped I/O technique
223
+5V
10k
8255
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PC7-0
SW7
SW6
SW5
SW4
SW3
SW2
SW1
SW0
Left Unconnected
10k
GND
DP
g
f
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
a
f
e
d
c
b
a
b
g
e
Common anode
DP
c
d
GND
Figure 18.12: Interfacing the keyboard and seven-segment display to the 8051 through 8255 in mode-0
Table 18.2: Related key codes and their encoded binary digits
Key press
Data at Port A
Description
none
SW 7
SW 6
SW 5
SW 4
SW 3
SW 2
SW 1
SW 0
11111111=FFH
01111111=7FH
10111111=BFH
11011111=DFH
11101111=EFH
11110111=F7H
11111011=FBH
11111101=FDH
11111110=FEH
none
00000111=07
00000110=06
00000101=05
00000100=04
00000011=03
00000010=02
00000001=01
00000000=00
Main Program:
ORG 0050H
MOV A, #CONTROL WORD
MOV R0, #CRA
MOVX @R0, A
Knext: ACALL Kcheck
ACALL Kcode
ACALL Display
SJMP Knext
224
Mode-1 (Strobed I/O with handshaking capability): one of the most powerful features of the 8255 is
its ability to handle handshaking signals. Handshaking refers to the process of how two smart devices
communicate with each other. The features of mode-1 are:
1. Port A of group A and Port B of group B can be configured either as input port or output port.
2. Handshaking signals for each port provided by three lines of their respected group from port CU/CL.
In other word, handshaking signals for port A and port B provided by three lines of port C upper
and port C lower respectively and remaining two line of port C can use for simple independent I/O
functions.
3. Both input and output lines are latched.
4. This mode supports interrupt logic.
The handshaking or communication control signals for both the ports in input and output function
explained separately as follows:
Mode-1: Outputting data with handshaking signals
As shown in figure 18.14, port A and B can be used as output ports to send data to a device with
handshaking signals. The handshaking signals for both ports A and B are provided by the six bits of port
C.
The following paragraphs provide the explanation of and reasoning behind handshaking signals only for
port A, but in concept they are exactly the same as for port B.
OBFA
(A indicates port A) output buffer full for port A: this is an active-low signal going out from PC7
to indicate that the microcontroller has written data to the specified output ports A. The OBFA must be
connected to a receiving peripheral device to inform it that new data are ready to read data byte from port
A latch. This signal goes high again after the 8255 receive an ACKA from the receiving peripheral.
ACKA (A indicates port A) acknowledge for port A: This is an active-low input signal received at PC6
of the 8255. Through ACKA, the 8255 knows that the data at port A has been picked up by the receiving
device. When the receiving device reads the data from port A, it must inform to the 8255 through the
ACKA signal. The 8255 in turns makes OBFA high, to indicate that the data at the port A is now old data.
OBFA will not go low until the microcontroller unit writes a new byte of data to port A.
INTRA (interrupt request for port A): This is active high signal going out from PC3 that can be used to
interrupt the microcontroller unit when a receiving device acknowledges the data received from the
microcontroller via 8255. In other words, this high signal on INTRA can be used to get attention of the
microcontroller unit. The microcontroller unit is informed through INTRA that the receiving device has
received the last byte and is ready to receive another one. INTR A interrupts the microcontroller unit in
whatever it is doing and forces it to write the next byte to port A to be outputted. It is important to note
that INTRA is set to logic 1 only if INTEA, OBFA and ACKA are all high. It is reset to zero when the
microcontroller unit writes a byte to port A. This signal is reset by rising edge of W R signal.
INTEA (interrupt enable for port A): The 8255 can disable INTRA to prevent it from interrupting the
microcontroller unit. This is the function of INTEA. INTEA is an internal flip-flop designed to mask (disable)
INTRA. INTEA can be set or reset through port C in BSR mode since the INTE A flip-flop is controlled through
PC6. INTEB is controlled by PC2 in BSR mode.
225
WR
INTEA
PA0-PA7
Port A output
PC7
OBFA
PC6
ACKA
Group A
INTRA
PC3
PB0-PB7
INTEB
PC1
PC2
Port B output
OBFB
ACKB
Port B handshake signals
Group B
PC0
PC4 and PC5
INTRB
I/O
WR
O BF
INTR
A CK
Output data
226
D3
Mode selection of
Group-B
1-I/O mode
Mode selection of
Group-A
01-mode 1
1-mode 1
Port A
0-output
PC4,5
1-input
0-output
Port B
0-output
Status Word
The 8255 enables monitoring of the status of signals INTR, OBF, and INTE for both ports A and B. This is done by
reading port C into the accumulator and testing the bits. This feature allows the implementation of polling instead of a
hardware interrupt.
D7
D6
D5
D4
D3
INTRA
O BFA
INTEA
I/O
D3
D1
INTEB
O BFB
D0
INTRB
I/O
Figure 18.16: Status word format Mode-1 Output
227
R D
PA0-PA7
Port A Input
INTEA
PC4
STBA
PC5
IBFA
Group A
INTRA
PC3
PB0-PB7
Port B Input
INTEB
STBB
PC1
IBFB
PC2
INTRB
PC0
I/O
PC6 and PC7
INTE (Interrupt Enable): same as for mode-1 output, explained earlier. The INTEA and INTEB are enabled or disabled
through PC4 and PC2 respectively.
Figure 18.18: Timing waveform for Mode-1 strobe input
STB
IBF
INTR
R D
Input data
228
Control and Status word: the control word format as given in figure 18.19 to configure Pot A and B as input ports in
mode-1. Status word shown in figure 18.20 and same as describe earlier for mode-1 output configuration.
PC6,7
1-input
0-output
1-I/O mode
Mode selection of
Group-A
01-mode 1
D3
Mode
selection of
Group-B
1-mode 1
Port A
1-input
Port B
1-input
D7
D6
D5
D4
D3
INTRA
I/O
I/O
IBFA
D3
D1
INTEB
IBFB
D0
INTRB
INTEA
Figure 18.20: Status word format Mode-1 input
Mode-2 (Strobed bidirectional I/O): Parallel I/O (high speed) with handshake is used to bidirectional data transfer
between two microcontroller units. The bidirectional communication between two smart units can be done using the
8255PPI in mode-2. In this mode, only port A of 8255 works as an 8-bit bidirectional port with handshaking signals.
Handshaking signals are provided by 5-bits of port C and data transfer direction for bidirectional port A decided by two
other (R D and WR ) control signals.
The salient features of this mode:
1. Only 8-bit port A can be configured as bidirectional port.
2. The handshaking signals for 8-bit bidirectional data transfer provided by 5-bits (PC3-PC7) of port C.
3. Both input and output lines are latched.
4. Remaining 3-lines (PC0-PC2) of port C can be used as simple I/O.
5. Port B can be used either in mode-0 (simple I/O) or mode-1.
Handshaking/control signals illustration in mode-2:
INTR (interrupt request): This signal is same as for mode-1. This signal is used for input as well as output operation.
Handshaking signals for output (write) operation:
OBF: An active low on this signal indicates that the microcontroller unit has written data to port A.
ACK: When this signal falls to low level, acknowledge that the data byte is received by the destination peripheral and
ready to receive next data byte from the microcontroller unit.
INTE1 (a bit associated with OBF): This signal can be controlled by BSR mode with PC6.
229
INTR
PC3
RD
WR
8255(1)
PC4-7
D0-D7
A0 A1
CS
8051(1)
AD0-AD7
ALE
PC3
PA0-PA7
8051(2)
PC4-7
Control lines
CS
Address
decoder
Octal Latch
INTR
RD
WR
8255(2)
D0-D7
A0 A1
ALE
Address
decoder
AD0-AD7
Octal Latch
Figure 18.21: Interfacing between two 8051 microcontroller using two 8255 in mode-2
To 8051(1)
INT0
PC3
PC3
Sender/receiver
D7-D0
PA0-PA7
8255(1)
A0
PC7
A1
PC4
RD
PC6
WR
PC5
OBF (1)
STB(1)
Receiver/sender
STB(2) PC7
OBF(2)
PC4
IBF(2) PC
6
ACK(2)
PC5
ACK(1)
IBF(1)
CS
To 8051(2)
INT0
D7-D0
8255(2)
A0
A1
RD
WR
CS
A7
A7
A2
A2
Figure 18.22: interfacing between two 8255 PPIs in mode-2
The control word format for mode-2 bidirectional data transfer as shown in figure 18.23.
1
D2
D1
D0
Mode
selection of
Group-B
1-I/O mode
PC2,1&0
0-output
1-input
0-mode 0
1-mode 1
Mode selection of
Group-A
1X-mode 2
Port B
0-output
1-input
Figure 18.23: Control word format to select mode-2 bidirectional data transfer configuration
The status bits of status word can be checked by rotating with Carry in Accumulator or can be used masking using
ANDing operation between appropriate word and status word in Accumulator.
D7
D6
D5
D4
D3
INTRA
O BF A
INTE1
IBFA
INTEA
Figure 18.24: Status word format Mode-2 bidirectional
PA0
PA1
PA2
PA3
row 1
row 2
row 3
8255
PB0
PB1
PB2
PB3
Figure 18.25: Matrix (hex-keyboard) keyboard interfacing to the 8051 through 8255
Example 18.8: From figure 18.25, identify the pressed key for each of the following.
(a)PA3-PA0=1011 for the row, PB3-PB0=1110 for the column
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REVIEW QUESTIONS
1.
2.
3.
4.
5.
6.
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CHAPTER-19
INTRODUCTION TO ADVANCED MICROCONTROLLERS
In this chapter, we discuss Intel 8096, Motorola MC68HC11 and ARM processor features, architectures and their
applications.
INTRODUCTION TO INTEL 8096
High speed digital signals are frequently encountered in modern control applications. In addition, there is often a
requirement for high speed 16-bit and 32-bit precision in calculations. The MCS-96 product line, generically referred to as
the 8096, is designed to be used in applications which require high speed calculations and fast I/O operations. The 8096
is a 16-bit microcontroller with dedicated I/O subsystems and a complete set of 16-bit arithmetic instructions including
multiply and divide operations.
The salient features of MCS-96 are:
16-bit architecture
8K bytes of ROM
232 bytes of RAM
Six addressing modes
High speed I/O with 4 dedicated and 4 programmable I/O lines.
10-bit A to D converter
Full duplex serial port
Watch dog timer to recover from errors
Programmable 8 source priority interrupt system
Available in 48 pin DIP or 68 pin Flat pack
THE 8096 GENERAL DESCRIPTION
Unlike microprocessors, microcontrollers are generally optimized for specific applications. Intel's 8048 was optimized for
general control tasks while the 8051 was optimized for 8-bit math and single bit Boolean operations. The 8096 has been
designed for high speed/high performance control applications. Because it has been designed for these applications the
8096 architecture is different from that of the 8048 or 8051. There are two major sections of the 8096; the CPU section
and the I/O section. Each of these sections can be subdivided into functional blocks as shown in figure 19.1.
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CPU SECTION
The CPU of the 8096 uses a 16-bit ALU which operates on a 256-byte register file instead of an accumulator. Any of the
locations in the register file can be used for sources or destinations for most of the instructions. This is called a register to
register architecture (RALU). Many of the instructions can also use bytes or words from anywhere in the 64K byte address
space as operands. A memory map is shown in figure 19.2. In the lower 24 bytes of the register file are the register
mapped I/O control locations, also called Special Function Registers or SFRs. These registers are used to control the onchip I/O features. The remaining 232 bytes are general purpose RAM, the upper 16 of which can be kept alive using a low
current power-down mode.
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The three operand instructions combined with the register to register architecture almost eliminate the necessity of using
temporary registers. This results in a faster processing time than machines that have equivalent instruction execution
times, but use a standard architecture. Long (32-bit) operations include shifts, normalize, and multiply and divide. The
word divide is a 32-bit by 16- bit operation with a 16-bit quotient and 16-bit remainder.
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The word multiply is a word by word multiply with a long result. Both of these operations can be done in either the signed
or unsigned mode. The direct unsigned modes of these instructions take only 6.5 microseconds.
A normalize instruction and sticky bit flag have been included in the instruction set to provide hardware support for the
software floating point package (FPAL-96).
INTERRUPTS
The flexibility of the instruction set is carried through into the interrupt system. There are 20 different interrupt sources that
can be used on the 8096. The 20 sources vector through 8 locations or interrupt vectors. The vector names and their
sources with their locations listed in figure 19.5. Apart from TRAP, external interrupts are serial port interrupt, software
timer interrupt, the HSI interrupt, the HSO interrupt, the high speed data available interrupt, the A/D conversion completes
interrupt and the timer overflow interrupts. These interrupts can be masked, and can be assigned a priority. .
ON-CHIP I/O SECTION
All of the on-chip I/O features of the 8096 can be accessed through the special function registers, as shown in figure 19.3.
The advantage of using register-mapped I/O is that these registers can be used as the sources or destinations of CPU
operations. There are seven major I/O functions. Each one of these will be considered with a section of code to exemplify
its usage. The first section covered will be the High Speed I/O, (HSIO), and subsystem. This section includes the High
Speed Input (HSI) unit, High Speed Output (HSO) unit, and the Timer/Counter section.
TIMER/COUNTERS
The 8096 has two time bases, Timer 1 and Timer 2. Timer 1 is a 16-bit free running timer which is incremented every 8
state times. (A state time is 3 oscillator periods, or 0.25 microseconds with a 12 MHz crystal.) Its value can be read at any
time and used as a reference for both the HSI section and the HSO section.
Timer 1 can cause an interrupt when it overflows, and cannot be modified or stopped without resetting the entire chip.
Timer 2 is really an event counter since it uses an external clock source. Like Timer 1, it is 16-bits wide, can be read at
any time, can be used with the HSO section, and can generate an interrupt when it overflows. Control of Timer 2 is limited
to incrementing it and resetting it. Specific values cannot be written to it.
HIGH SPEED INPUTS (HSI)
The HSI unit can be thought of as a message taker which records the line which had an event and the time at which the
event occurred. Four types of events can trigger the HSI unit. The HSI
unit can measure pulse widths and record times of events with a 2
microsecond resolution. It can look for one of four events on each of four
lines simultaneously, based on the information in the HSI Mode register.
HIGH SPEED OUTPUTS (HSO)
Just as the HSI can be thought of as a message taker, the HSO can be
thought of as a message sender. At times determined by the software, the
HSO sends messages to various devices to have them turn on, turn off,
start processing, or reset. Since the programmed times can be referenced
to either Timer 1 or Timer 2, the HSO makes the two timers look like
many. For example, if several events have to occur at specific times, the
HSO unit can schedule all of the events based on a single timer. The
events that can be scheduled to occur and the format of the command
written to the HSO Command register.
SERIAL PORT
Controlling a device from a remote location is a simple task that frequently requires additional hardware with many
processors. The 8096 has an on-chip serial port to reduce the total number of chips required in the system. The serial port
is similar to that on the MCS-51 product line. It has one synchronous and three asynchronous modes. In the
asynchronous modes baud rates of up to 187.5 Kbaud can be used, while in the synchronous mode rates up to 1.5
Mbaud are available. The chip has a baud rate generator which is independent of Timer 1 and Timer 2, so using the serial
port does not take away any of the HSI, HSO or timer flexibility or functionality.
Control of the serial port is provided through the SPCON/SPSTAT (Serial Port CONtrol/Serial Port STATus) register.
The four modes of the serial port are referred to as modes 0, 1, 2 and 3. Mode 0 is the synchronous mode, and is
commonly used to interface to shift registers for I/O expansion. In this mode the port outputs a pulse train on the TXD pin
and either transmits or receives data on the RXD pin. Mode 1 is the standard asynchronous mode, 8 bits plus a stop and
start bit are sent or received. Modes 2 and 3 handle 9 bits plus a stop and start bit. The difference between the two is, that
in Mode 2 the serial port interrupt will not be activated unless the ninth data bit is a one; in Mode 3 the interrupt is
activated whenever a byte is received. These two modes are commonly used for interprocessor communication.
A to D CONVERTER
Analog inputs are frequently required in a microcontroller application. The 8096 has a 10-bit A to D converter that can use
any one of eight input channels. The conversions are done using the successive approximation method, and require 168
state times (42 microseconds with a 12 MHz clock.) The results are guaranteed monotonic by design of the converter.
This means that if the analog input voltage changes, even slightly, the digital value will either stay the same or change in
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the same direction as the analog input. When doing process control algorithms, it is frequently the changes in inputs that
are required, not the absolute accuracy of the value. For this reason, even if the absolute accuracy of a 10-bit converter is
the same as that of an 8-bit converter, the 10-bit monotonic converter is much more useful.
PWM (Pulse Width Modulation) Output
Analog outputs are just as important as analog inputs when connecting to a piece of equipment. True digital to analog
converters are difficult to make on a microprocessor because of all of the digital noise and the necessity of providing an
on chip, relatively high current, rail to rail driver. They also take up a large amount of silicon area which can be better used
for other features.
The A to D converter does use a D to A, but the currents involved are very small. For many applications an analog output
signal can be replaced by a Pulse Width Modulated (PWM) signal. This signal can be easily generated in hardware, and
takes up much less silicon area than a true D to A. The signal is a variable duty cycle, fixed frequency waveform that can
be integrated to provide an approximation to an analog output. The frequency is fixed at a period of 64 microseconds for a
12 MHz clock speed. Controlling the PWM simply requires writing the desired duty cycle value (an 8-bit value) to the PWM
Register.
WATCH DOG TIMER
If the software fails to reset the watch dog every 64K states, the 8096 is reset. This is graceful method of recovering from
software failure.
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The HCMOS MC68HC11A8 is an advanced 8-bit microcontroller (MCU) with highly sophisticated on-chip
peripheral capabilities. A fully static design and high-density complementary metal-oxide semiconductor
(HCMOS) fabrication process allow E-series devices to operate at frequencies from 3 MHz to DC, with very
low power consumption.
FEATURES
The following are some of the hardware and software features:
Hardware Features
8 Kbytes of ROM
512 Bytes of EEPROM
256 Bytes of RAM (All Saved During Standby) Relocatable to any 4K Boundary
Enhanced 16-Bit Timer System:
Four Stage Programmable Pre-scaler
Three Input Capture Functions
Five Output Compare Functions
8-Bit Pulse Accumulator Circuit
Enhanced NRZ Serial Communications Interface (SCI)
Serial Peripheral Interface (SPI)
Eight Channel, 8-Bit Analog-to-Digital Converter
Real Time Interrupt Circuit
Computer Operating Properly (COP) Watchdog System
Available in Dual-In-Line or Leaded Chip Carrier Packages
Software Features
Enhanced M6800/M6801 Instruction Set
16 x 16 Integer and Fractional Divide Features
Bit Manipulation
WAIT Mode
STOP Mode
General Description
The high-density CMOS technology (HCMOS) used on the MC68HC11A8 combines smaller size and higher speeds with
the low power and high noise immunity of CMOS. On-chip memory systems include 8 Kbytes of ROM, 512 bytes of
electrically erasable programmable ROM (EEPROM), and 256 bytes of static RAM.
A block diagram of the MC68HC11A8 is shown in figure 19.6. Major peripheral functions are provided on-chip. An
eight channel analog-to-digital (A/D) converter is included with eight bits of resolution. An asynchronous serial
communications interface (SCI) and a separate synchronous serial peripheral interface (SPI) are included. The main
16-bit free-running timer system has three input capture lines, five output compare lines, and a real-time interrupt
function. An 8-bit pulse accumulator subsystem can count external events or measure external periods.
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Self monitoring circuitry is included on-chip to protect against system errors. A computer operating
properly (COP) watchdog system protects against software failures. A clock monitor system generates a
system reset in case the clock is lost or runs too slow. An illegal op-code detection circuit provides a nonmaskable interrupt if an illegal op-code is detected. Two software controlled operating modes, WAIT and
STOP, are available to conserve additional power.
PROGRAMMING MODEL
In addition to being able to execute all M6800 and M6801 instructions, the MC68HC11A8 allows execution
of 91 new op-codes. Figure 19.7 shows the seven CPU registers which are available to the programmer
OPERATING MODES
During reset, MODA and MODB are used to select one of the four operating modes for the MC68HC11A8:
single-chip operating mode, expanded multiplexed operating mode, special bootstrap operating mode, and
special test operating mode.
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The bootstrap mode is considered a special operating mode as distinguished from the normal single-chip
operating mode. This is a very versatile operating mode since there are essentially no limitations on the
special purpose program that can be loaded into the internal RAM. The boot loader program is contained
in the 192 byte bootstrap ROM. This ROM is enabled only if the MCU is reset in special bootstrap operating
mode, and appears as internal memory space at locations $BF40H-$BFFFH. The boot loader program will
use the SCI to read a 256 byte program into on-chip RAM at locations $0000-$00FF. After the character
for address $00FF is received, control is automatically passed to that program at location $0000.
Special Test Operating Mode
The test mode is a special operating mode intended primarily for factory testing. This mode is very similar
to the expanded multiplexed operating mode. In special test operating mode, the reset and interrupt
vectors are fetched from external memory locations $BFC0$BFFF rather than $FFC0$FFFF. There are no
time limits for protection of the TMSK2, OPTION, and INIT registers, so these registers may be written
repeatedly. Also a special TEST1 register is enabled which allows several factory test functions to be
invoked. The special test operating mode is not recommended for use by an end user because of the
reduced system security; however, an end user may wish to come out of reset in special test operating
mode. Then, after some initialization, the SMOD and MDA bits could be rewritten to select a normal
operating mode to re-enable the protection features.
ON-CHIP MEMORY
This section describes the on-chip ROM, RAM, and EEPROM memories. The memory maps for each mode
of operation are shown and the RAM and l/O mapping register (INIT) is described. The INIT register allows
the on-chip RAM and the 64 control registers to be moved to suit the needs of a particular application.
Memory Maps
Composite memory maps for each mode of operation are shown in figure 19.8. Memory locations are
shown in the shaded areas and the contents of these shaded areas are shown to the right. These modes
include single-chip, expanded multiplexed, special bootstrap, and special test. Single-chip operating
modes do not generate external addresses.
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241
Each conversion is accomplished in 32 MCU E clock cycles, provided the E clock rate is greater than 750
kHz. For systems which operate at clock rates less than 750 kHz, an internal R-C oscillator must be used
to clock the A/D system. The internal R-C oscillator is selected by setting the CSEL bit in the OPTION
register.
PARALLEL I/O
The MC68HC11A8 has 40 I/O pins arranged as five 8-bit ports. All of these pins serve multiple functions
depending on the operating mode and data in the control registers. This section explains the operation of
these pins only when they are used for parallel l/O. Ports C and D are used as general purpose input
and/or output pins under direct control of their respective data direction registers. Ports A, B, and E, with
the exception of port A pin 7, are fixed direction inputs or outputs and therefore do not have data
direction registers. Port B, port C, the STRA pin, and the STRB pin are used for strobed and/or handshake
modes of parallel l/O, as well as general purpose l/O.
PROGRAMMABLE TIMER
The timer has a single 16-bit free-running counter which is clocked by the output of a four-stage prescaler
(divide by 1, 4, 8, or 16), which is in turn driven by the MCU E clock. Input functions are called input
captures. These input captures record the count from the free-running counter in response to a detected
edge on an input line. Output functions, called output compares, cause an output action when there is a
match between a 16-bit output-compare register and the free-running counter. This timer system has
three input capture registers and five output compare registers.
RESETS
The MCU has four possible types of reset: an active low external reset pin (RESET), a power-on reset, a
computer operating properly (COP) watchdog timer reset, and a clock monitor reset.
COMPUTER OPERATING PROPERLY (COP) RESET
The MCU includes a computer operating properly watchdog system to help protect against software
failures. To use a COP watchdog timer, a watchdog timer reset sequence must be executed on a regular
periodic basis so that the watchdog timer is never allowed to time out.
INTERRUPTS
When an external or internal (hardware) interrupt occurs, the interrupt is not serviced until the current
instruction being executed is completed. Until the current instruction is complete, the interrupt is
considered pending. After completion of current instruction execution, unmasked interrupts may be
serviced in accordance with an established fixed hardware priority circuit. Seventeen hardware interrupts
and one software interrupt (excluding reset type interrupts) can be generated from all of the possible
sources. The interrupts can be divided into two basic categories, maskable and non-maskable. In the
MC68HC11A8 fifteen of the interrupts can be masked using the condition code register I bit. In addition to
being maskable by the I bit in the condition code register, all of the on-chip interrupt sources are
individually maskable by local control bits.
PORT SIGNALS
Ports A, D, and E signals are independent of the operating mode. Port B provides eight general purpose
output signals in single-chip operating modes and provides eight high-order address signals when the
microcontroller is in expanded multiplexed operating modes. Port C provides eight general purpose
input/output signals when the microcontroller is in single chip operating modes. When the microcontroller
is in expanded multiplexed operating modes, port C is used for a multiplexed address/data bus.
Port A
Port A may be configured for: three input capture functions (IC1, IC2, IC3), four output compare functions
(OC2, OC3, OC4, OC5), and either a pulse accumulator input (PAI) or a fifth output compare function
(OC1). Any port A pin that is not used for its alternate timer function may be used as a general purpose
input or output line.
Port B
While in single-chip operating modes, all of the port B pins are general-purpose output pins. During MCU
reads of this port, the level sensed at the input side of the port B output drivers is read. Port B may also
be used in a simple strobed output mode where an output pulse appears at the STRB signal each time
data is written to port B. When in expanded multiplexed operating modes, all of the port B pins act as high
order address output signals. During each MCU cycle, bits 8 through 15 of the address are output on the
PB0-PB7 lines respectively.
Port C
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While in single-chip operating modes, all port C pins are general-purpose input/output pins. Port C inputs
can be latched by providing an input transition to the STRA signal. Port C may also be used in full
handshake modes of parallel l/O where the STRA input and STRB output act as handshake control lines.
When in expanded multiplexed operating modes, all port C pins are configured as multiplexed
address/data signals. During the address portion of each MCU cycle, bits 0 through 7 of the address are
output on the PC0-PC7 lines. During the data portion of each MCU cycle (E high), pins 0 through 7 are
bidirectional data signals (D0-D7). The direction of data at the port C pins is indicated by the R/W signal.
PORT D
Port D pins 0-5 may be used for general-purpose l/O signals. Port D pins alternately serve as the serial
communications interface (SCI) and serial peripheral interface (SPI) signals when those subsystems are
enabled. Pin PD0 is the receive data input (RxD) signal for the serial communication interface (SCI). Pin
PD1 is the transmit data output (TxD) signal for the SCI. Pins PD2 through PD5 are dedicated to the SPI.
PD2 is the master-in-slave-out (MISO) signal. PD3 is the master-out-slave-in (MOSI) signal. PD4 is the
serial clock (SCK) signal and PD5 is the slave select (SS) input.
Port E
Port E is used for general-purpose inputs and/or analog-to-digital (A/D) input channels. Reading port E
during the sampling portion of an A/D conversion could cause very small disturbances and affect the
accuracy of that result. If very high accuracy is required, avoid reading port E during conversions.
LOW POWER MODES
There are two programmable low power modes: STOP and WAIT. In the WAIT mode, the on-chip oscillator
remains active, but in STOP mode, oscillator is stopped. Both mode can be terminated by any unmaskable
interrupt.
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operations (for example, a divide operation) by combining several simple instructions. Each instruction is a fixed
length to allow the pipeline to fetch future instructions before decoding the current instruction. In contrast, in CISC
processors the instructions are often of variable size and take many cycles to execute.
Figure 19.9: CISC vs. RISC. CISC emphasizes hardware complexity. RISC emphasizes compiler complexity
2. PipelinesThe processing of instructions is broken down into smaller units that can be executed in parallel by
pipelines. Ideally the pipeline advances by one step on each cycle for maximum throughput. Instructions can be decoded
in one pipeline stage. There is no need for an instruction to be executed by a mini-program called microcode as on CISC
processors.
3. RegistersRISC machines have a large general-purpose register set. Any register can contain either data or an
address. Registers act as the fast local memory store for all data processing operations. In contrast, CISC processors
have dedicated registers for specific purposes.
4. Load-store architectureThe processor operates on data held in registers. Separate load and store instructions
transfer data between the register bank and external memory. Memory accesses are costly, so separating memory
accesses from data processing provides an advantage because you can use data items held in the register bank multiple
times without needing multiple memory accesses.
In contrast, with a CISC design the data processing operations can act on memory directly. These design rules allow a
RISC processor to be simpler, and thus the core can operate at higher clock frequencies. In contrast, traditional CISC
processors are more complex and operate at lower clock frequencies. Over the course of two decades, however, the
distinction between RISC and CISC has blurred as CISC processors have implemented more RISC concepts.
The ARM Design Concept
There are a number of physical features that have driven the ARM processor design. First, portable embedded systems
require some form of battery power. The ARM processor has been specifically designed to be small to reduce power
consumption and extend battery operationessential for applications such as mobile phones and personal digital
assistants (PDAs).
High code density is another major requirement since embedded systems have limited memory due to cost and/or
physical size restrictions. High code density is useful for applications that have limited on-board memory, such as mobile
phones and mass storage devices.
In addition, embedded systems are price sensitive and use slow and low-cost memory devices. For high-volume
applications like digital cameras, every cent has to be accounted for in the design. The ability to use low-cost memory
devices produces substantial savings.
Another important requirement is to reduce the area of the die taken up by the embedded processor. For a single-chip
solution, the smaller the area used by the embedded processor, the more available space for specialized peripherals. This
in turn reduces the cost of the design and manufacturing since fewer discrete chips are required for the end product.
ARM has incorporated hardware debug technology within the processor so that software engineers can view what is
happening while the processor is executing code. With greater visibility, software engineers can resolve issues faster,
which has a direct effect on the time to market and reduces overall development costs.
The ARM core is not a pure RISC architecture because of the constraints of its primary applicationthe embedded
system. In some sense, the strength of the ARM core is that it does not take the RISC concept too far. In todays systems
the key is not raw processor speed but total effective system performance and power consumption.
Instruction Set for Embedded Systems
The ARM instruction set differs from the pure RISC definition in several ways that make the ARM instruction set suitable
for embedded applications:
Variable cycle execution for certain instructionsNot every ARM instruction executes in a single cycle. For example,
load-store-multiple instructions vary in the number of execution cycles depending upon the number of registers being
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transferred. The transfer can occur on sequential memory addresses, which increases performance since sequential
memory accesses are often faster than random accesses.
Inline barrel shifter leading to more complex instructionsThe inline barrel shifter is a hardware component that
preprocesses one of the input registers before it is used by an instruction. This expands the capability of many instructions
to improve core performance and code density.
Thumb 16-bit instruction setARM enhanced the processor core by adding a second 16-bit instruction set called
Thumb that permits the ARM core to execute either 16- or 32-bit instructions. The 16-bit instructions improve code density
by about 30% over 32-bit fixed-length instructions.
Conditional executionAn instruction is only executed when a specific condition has been satisfied. This feature
improves performance and code density by reducing branch instructions.
Enhanced instructionsThe enhanced digital signal processor (DSP) instructions were added to the standard ARM
instruction set to support fast 1616-bit multiplier operations and saturation. These instructions allow a faster-performing
ARM processor in some cases to replace the traditional combinations of a processor plus a DSP.
These additional features have made the ARM processor one of the most commonly used 32-bit embedded processor
cores. Many of the top semiconductor companies around the world produce products based around the ARM processor.
ARM-BASED EMBEDDED SYSTEM
Figure 19.10 shows a typical embedded device based on an ARM core. Each box represents a feature or function. The
lines connecting the boxes are the buses carrying data. We can separate the device into four main hardware components:
The ARM processor controls the embedded device. Different versions of the ARM processor are available to suit the
desired operating characteristics. An ARM processor comprises a core (the execution engine that processes instructions
and manipulates data) plus the surrounding components that interface it with a bus. These components can include
memory management and caches.
Controllers coordinate important functional blocks of the system. Two commonly found controllers are interrupt and
memory controllers.
The peripherals provide all the input-output capability external to the chip and are responsible for the uniqueness of the
embedded device.
A bus is used to communicate between different parts of the device.
ARM Bus Technology
Embedded systems use different bus technologies than those designed for x86 PCs. The most common PC bus
technology, the Peripheral Component Interconnect (PCI) bus, connects such devices as video cards and hard disk
controllers to the x86 processor bus. This type of technology is external or off-chip (i.e., the bus is designed to connect
mechanically and electrically to devices external to the chip) and is built into the motherboard of a PC. In contrast,
embedded devices use an on-chip bus that is internal to the chip and that allows different peripheral devices to be
interconnected with an ARM core.
There are two different classes of devices attached to the bus. The ARM processor core is a bus mastera logical device
capable of initiating a data transfer with another device across the same bus. Peripherals tend to be bus slaveslogical
devices capable only of responding to a transfer request from a bus master device.
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A bus has two architecture levels. The first is a physical level that covers the electrical characteristics and bus width (16,
32, or 64 bits). The second level deals with protocolthe logical rules that govern the communication between the
processor and a peripheral. ARM is primarily a design company. It seldom implements the electrical characteristics
of the bus, but it routinely specifies the bus protocol.
AMBA Bus Protocol
The Advanced Microcontroller Bus Architecture (AMBA) was introduced in 1996 and has been widely adopted as the onchip bus architecture used for ARM processors. The first AMBA buses introduced were the ARM System Bus (ASB) and
the ARM Peripheral Bus (APB). Later ARM introduced another bus design, called the ARM High Performance Bus
(AHB). Using AMBA, peripheral designers can reuse the same design on multiple projects.
Because there are a large number of peripherals developed with an AMBA interface, hardware designers have a wide
choice of tested and proven peripherals for use in a device. A peripheral can simply be bolted onto the on-chip bus
without having to redesign an interface for each different processor architecture. This plug-and-play interface for hardware
developers improves availability and time to market.
AHB provides higher data throughput than ASB because it is based on a centralized multiplexed bus scheme rather than
the ASB bidirectional bus design. This change allows the AHB bus to run at higher clock speeds and to be the first ARM
bus to support widths of 64 and 128 bits. ARM has introduced two variations on the AHB bus: Multi-layer AHB and AHBLite. In contrast to the original AHB, which allows a single bus master to be active on the bus at any time, the Multi-layer
AHB bus allows multiple active bus masters. AHB-Lite is a subset of the AHB bus and it is limited to a single bus master.
This bus was developed for designs that do not require the full features of the standard AHB bus.
AHB and Multi-layer AHB support the same protocol for master and slave but have different interconnects. The new
interconnects in Multi-layer AHB are good for systems with multiple processors. They permit operations to occur in parallel
and allow for higher throughput rates.
A programmer can think of an ARM core as functional units connected by data buses, as shown in figure 19.11, where,
the arrows represent the flow of data, the lines represent the buses, and the boxes represent either an operation unit or a
storage area. The figure shows not only the flow of data but also the abstract components that make up an ARM core.
Data enters the processor core through the Data bus. The data may be an instruction to execute or a data item. The
instruction decoder translates instructions before they are executed. Each instruction executed belongs to a particular
instruction set.
The ARM processor, like all RISC processors, uses a load-store architecture. This means it has two instruction types for
transferring data in and out of the processor: load instructions copy data from memory to registers in the core, and
conversely the store
instructions copy data from registers to memory. There are no data processing instructions that directly manipulate data in
memory. Thus, data processing is carried out solely in registers.
Data items are placed in the register filea storage bank made up of 32-bit registers. Since the ARM core is a 32-bit
processor, most instructions treat the registers as holding signed or unsigned 32-bit values. The sign extend hardware
converts signed 8-bit and 16-bit numbers to 32-bit values as they are read from memory and placed in a register.
ARM instructions typically have two source registers, Rn and Rm, and a single result or destination register, Rd. Source
operands are read from the register file using the internal buses A and B, respectively.
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The ALU (arithmetic logic unit) or MAC (multiply-accumulate unit) takes the register values Rn and Rm from the A and B
buses and computes a result. Data processing instructions write the result in Rd directly to the register file. Load and store
instructions use the ALU to generate an address to be held in the address register and broadcast on the Address bus.
One important feature of the ARM is that register Rm alternatively can be preprocessed in the barrel shifter before it
enters the ALU. Together the barrel shifter and ALU can calculate a wide range of expressions and addresses.
Processor Modes
The processor mode determines which registers are active and the access rights to the cpsr register itself. Each
processor mode is either privileged or non-privileged: A privileged mode allows full read-write access to the cpsr.
Conversely, a non-privileged mode only allows read access to the control field in the cpsr but still allows read-write access
to the condition flags.
There are seven processor modes in total: six privileged modes (abort, fast interrupt request, interrupt request, supervisor,
system, and undefined) and one non-privileged mode (user).
The processor enters abort mode when there is a failed attempt to access memory. Fast interrupt request and interrupt
request modes correspond to the two interrupt levels available on the ARM processor. Supervisor mode is the mode that
the processor is in after reset and is generally the mode that an operating system kernel operates in. System mode is a
special version of user mode that allows full read-write access to the cpsr. Undefined mode is used when the processor
encounters an instruction that is undefined or not supported by the implementation. User mode is used for programs and
applications.
Banked Registers
Figure 19.12 shows all 37 registers in the register file. Of those, 20 registers are hidden from a program at different times.
These registers are called banked registers and are identified by the shading in the diagram. They are available only
when the processor is in a particular mode; for example, abort mode has banked registers r13_abt, r14_abt and spsr_abt.
Banked registers of a particular mode are denoted by an underline character post-fixed to the mode mnemonic or _mode.
Every processor mode except user mode can change mode by writing directly to the mode bits of the cpsr. All processor
modes except system mode have a set of associated banked registers that are a subset of the main 16 registers. A
banked register maps one-to-one onto a user mode register. If you change processor mode, a banked register from the
new mode will replace an existing register.
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PIPELINE
A pipeline is the mechanism a RISC processor uses to execute instructions. Using a pipeline speeds up execution by
fetching the next instruction while other instructions are being decoded and executed. One way to view the pipeline is to
think of it as an automobile assembly line, with each stage carrying out a particular task to manufacture the vehicle.
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The pipeline design for each ARM family differs. For example, The ARM9 core increases the pipeline length to five
stages, as shown in Figure 19.15. The ARM9 adds a memory and write back stage, which allows the ARM9 to process
on average 1.1 Dhrystone MIPS per MHzan increase in instruction throughput by around 13% compared with an ARM7.
The maximum core frequency attainable using an ARM9 is also higher. The ARM10 increases the pipeline length still
further by adding a sixth stage, as shown in figure 19.16. The ARM10 can process on average 1.3 Dhrystone MIPS per
MHz, about 34% more throughput than an ARM7 processor core, but again at a higher latency cost. Even though the
ARM9 and ARM10 pipelines are different, they still use the same pipeline executing characteristics as an ARM7. Code
written for the ARM7 will execute on an ARM9 or ARM10.
ARM7 Family
The ARM7 core has a Von Neumannstyle architecture, where both data and instructions use the same bus. The core
has a three-stage pipeline and executes the architecture ARMv4T instruction set.
The ARM7TDMI was the first of a new range of processors introduced in 1995 by ARM. It is currently a very popular core
and is used in many 32-bit embedded processors. It provides a very good performance-to-power ratio. The ARM7TDMI
processor core has been licensed by many of the top semiconductor companies around the world and is the first core to
include the Thumb instruction set, a fast multiply instruction, and the Embedded ICE debug technology.
ARM9 Family
The ARM9 family was announced in 1997. Because of its five-stage pipeline, the ARM9 processor can run at higher clock
frequencies than the ARM7 family. The extra stages improve the overall performance of the processor. The memory
system has been redesigned to follow the Harvard architecture, which separates the data D and instruction I buses. The
first processor in the ARM9 family was the ARM920T, which includes a separate D + I cache and an MMU. This processor
can be used by operating systems requiring virtual memory support. ARM922T is a variation on the ARM920T but with
half the D +I cache size.
The latest core in the ARM9 product line is the ARM926EJ-S synthesizable processor core, announced in 2000. It is
designed for use in small portable Java-enabled devices such as 3G phones and personal digital assistants (PDAs). The
ARM926EJ-S is the first ARM processor core to include the Jazelle technology, which accelerates Java byte code
execution. It features an MMU, configurable TCMs, and D +I caches with zero or nonzero wait state memories.
ARM10 Family
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The ARM10, announced in 1999, was designed for performance. It extends the ARM9 pipeline to six stages. It also
supports an optional vector floating-point (VFP) unit, which adds a seventh stage to the ARM10 pipeline. The VFP
significantly increases floating-point performance and is compliant with the IEEE 754.1985 floating-point standard.
The ARM1020E is the first processor to use an ARM10E core. Like the ARM9E, it includes the enhanced E instructions. It
has separate 32K D + I caches, optional vector floating-point unit, and an MMU. The ARM1020E also has a dual 64-bit
bus interface for increased performance.
ARM1026EJ-S is very similar to the ARM926EJ-S but with both MPU and MMU. This processor has the performance of
the ARM10 with the flexibility of an ARM926EJ-S.
ARM11 Family
The ARM1136J-S, announced in 2003, was designed for high performance and power efficient applications. ARM1136J-S
was the first processor implementation to execute architecture ARMv6 instructions. It incorporates an eight-stage pipeline
with separate load-store and arithmetic pipelines. Included in the ARMv6 instructions are single instruction multiple data
(SIMD) extensions for media processing, specifically designed to increase video processing performance. The
ARM1136JF-S is an ARM1136J-S with the addition of the vector floating-point unit for fast floating-point operations.
The ARM processor can be abstracted into eight componentsALU, barrel shifter, MAC, register file, instruction decoder,
address register, incrementer, and sign extend. ARM has three instruction setsARM, Thumb, and Jazelle. The register
file contains 37 registers, but only 17 or 18 registers are accessible at any point in time; the rest are banked according to
processor mode. The current processor mode is stored in the cpsr. It holds the current status of the processor core as
well interrupt masks, condition flags, and state. The state determines which instruction set is being executed. An ARM
processor comprises a core plus the surrounding components that interface it
with a bus. The core extensions include the following:
Caches are used to improve the overall system performance.
TCMs are used to improve deterministic real-time response.
Memory management is used to organize memory and protect system resources.
Coprocessors are used to extend the instruction set and functionality. Coprocessor 15 controls the cache, TCMs, and
memory management.
An ARM processor is an implementation of a specific instruction set architecture (ISA). The ISA has been continuously
improved from the first ARM processor design. Processors are grouped into implementation families (ARM7, ARM9,
ARM10, and ARM11) with similar characteristics.
APPLICATIONS
ARM processors are found in numerous market segments, including networking, automotive, mobile and consumer
devices, mass storage, and imaging. Within each segment ARM processors can be found in multiple applications.
For example, the ARM processor is found in networking applications like home gateways, DSL modems for high-speed
Internet communication, and 802.11 wireless communications. The mobile device segment is the largest application area
for ARM processors because of mobile phones. ARM processors are also found in mass storage devices such as hard
drives and imaging products such as inkjet printersapplications that are cost sensitive and high volume.
In contrast, ARM processors are not found in applications that require leading-edge high performance. Because these
applications tend to be low volume and high cost, ARM has decided not to focus designs on these types of applications.
References:
1. Intel 8096 reference manual.
2. Motorola M68HC11 reference manual.
3. ARM System Developers Guide, Elsevier.
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CHAPTER-20
INTRODUCTION TO EMBEDDED SYSTEM DESIGN
An embedded system is an applied computer system, as distinguished from other types of computer systems such as personal
computers (PCs) or supercomputers. However, we will find that the definition of embedded system is difficult to pin down, as it
constantly evolves with advances in technology and dramatic decreases in the cost of implementing various hardware and software
components.
An embedded system is any computer/control system, which is hidden inside a product other than a computer that is, system within
a system. The embedded systems have a microcontroller (microprocessor, memory and serial port etc.) in center as heart to control
surround system. An embedded system is designed and programmed by the manufacturers to perform a specific task, thus called
dedicated system. Software (program) and hardware works together to perform a specific task. Also embedded system can be
defined as a real time system. A real-time system is one that must process information and produce a response within a specified
time limit. They usually do not have keyboards, screens or disk drive to perform task. An embedded system is a complete device
including hardware and mechanical parts. All smart applications are the example of embedded systems such as Air traffic control,
digital watches, digital cameras, microwave ovens, DVD player, TV, printers mp3 player, iPod, mobile phones, sewing machine,
washing machine, traffic lights, factory control, temperature control, nuclear power plant control, videogame console etc.
A small microcontroller in the toothbrush provides programmable speed control and a battery state of charge indication. High end
automobiles can contain over fifty embedded microcontrollers. A typical middle class household has over fifty embedded devices. For
every PC in the world there are over one hundred embedded devices. All told, embedded devices account for most of the worlds
production of microprocessors. In recent years, the field has outgrown many of its traditional descriptions. Following are a few of the
more common descriptions of an embedded system:
1. Embedded systems are more limited in hardware and/or software functionality than a personal computer (PC). This holds true for a
significant subset of the embedded systems family of computer systems. In terms of hardware limitations, this can mean limitations in
processing performance, power consumption, memory, hardware functionality, and so forth. In software, this typically means limitations
relative to a PCfewer applications, scaled-down applications, no operating system (OS) or a limited OS, or less abstraction-level
code. However, this definition is only partially true today as boards and software typically found in PCs of past and present have been
repackaged into more complex embedded system designs.
2. An embedded system is designed to perform a dedicated function. Most embedded devices are primarily designed for one specific
function. However, we now see devices such as personal data assistant (PDA)/cell phone hybrids, which are embedded systems
designed to be able to do a variety of primary functions. Also, the latest digital TVs include interactive applications that perform a wide
variety of general functions unrelated to the TV function but just as important, such as e-mail, web browsing, and games.
3. An embedded system is a computer system with higher quality and reliability requirements than other types of computer systems.
Some families of embedded devices have a very high threshold of quality and reliability requirements. For example, if a cars engine
controller crashes while driving on a busy freeway or a critical medical device malfunctions during surgery, very serious problems result.
However, there are also embedded devices, such as TVs, games, and cell phones, in which a malfunction is an inconvenience but not
usually a life-threatening situation.
Some texts define embedded systems as computing systems or devices without a keyboard, display, or mouse. These texts use the
look characteristic as the differentiating factor by saying, embedded systems do not look like ordinary personal computers; they look
like digital cameras or smart mobile phones. These statements are all misleading!
A general definition of embedded systems is: embedded systems are computing systems with tightly coupled hardware and software
integration that are designed to perform a dedicated function. The word embedded reflects the fact that these systems are usually an
integral part of a larger system, known as the embedding system. Multiple embedded systems can coexist in an embedding system.
This definition is good but subjective. In the majority of cases, embedded systems are truly embedded, i.e., they are systems within
systems. They either cannot or do not function on their own. For example, the digital set-top box (DST) found in many home
entertainment systems nowadays. The digital audio/video decoding system, called the Audio /Video decoder, which is an integral part
of the DST, is an embedded system. The A/V decoder accepts a single multimedia stream and produces sound and video frames as
output. The signals received from the satellite by the DST contain multiple streams or channels. Therefore, the A/V decoder works in
conjunction with the transport stream decoder, which is yet another embedded system. The transport stream decoder de-multiplexes
the incoming multimedia streams into separate channels and feeds only the selected channel to the A/V decoder. In some cases,
embedded systems can function as standalone systems. The network router is a standalone embedded system. It is built using a
specialized communication processor, memory, a number of network access interfaces (known as network ports), and special software
that implements packet routing algorithms. In other words, the network router is a standalone embedded system that routes packets
coming from one port to another, based on a programmed routing algorithm.
The definition also does not necessarily provide answers to some often-asked questions. For example: Can a personal computer be
classified as an embedded system? Why? Can an HCL notebook that is used only as a DVD player to be called an embedded system?
A single comprehensive definition does not exist. Electronic devices in just about every engineering market segment are classified as
embedded systems (see table 20.1). In short, outside of being types of computer systems, the only specific characterization that
continues to hold true for the wide spectrum of embedded system devices is that there is no single definition reflecting them all.
Therefore, we need to focus on the characteristics of embedded systems from many different perspectives to gain a real understanding of what embedded systems are and what makes embedded systems special.
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I/P device
Processor
O/P device
Memory
Figure 20.1: A typical Embedded System
Within the exception of these few common features, rest of the embedded hardware is usually unique and varies from application to
application. Each system must meet a completely different set of requirements.
DESIGN PARAMETERS
The common critical features and design requirements of an embedded hardware include
1. Processing Power: Selection of the processor/microcontroller is based on the amount of processing power to get the job done
and also on the basis of interrupts and register bit-width required.
2. Throughput: The system may need to handle a lot of data in a short period of time i.e. operating clock frequency.
3. Response: The system has to react within a time limit.
4. Memory: Hardware designer must make his best estimate of the memory requirement and must make provision for expansion.
5. Power Consumption: Systems generally work on battery and design of both software and hardware must take care of power
saving techniques.
6. Number of units: The number of units expected to be produced and sold will dictate the Trade-off between production cost and
development cost.
7. Expected Lifetime: Design decisions like selection of components to system development cost will depend on how long the
system is expected to run.
8. Program Installation: Installation of the software on to the embedded system needs special tools.
9. Testability and Debug-ability: Setting up test conditions and equipment will be difficult and finding out what is wrong with the
software will become a difficult task without a keyboard and the usual display screen.
10. Reliability: It is critical parameter if embedded system is a space shuttle or a car but in case of a toy it doesnt always have to
work right.
EMBEDDED SYSTEMS DESIGN
When we are approaching embedded systems architecture design from a systems engineering point of view, several models can be
applied to describe the cycle of embedded system design. Most of these models are based upon one or some combination of the
following development models:
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1.
The big-bang model, in which there is essentially no planning or processes in place before and during the development of a
system.
2. The code-and-fix model, in which product requirements are defined but no formal processes are in place before the start of
development.
3. The waterfall model, in which there is a process for developing a system in steps, where results of one step flow into the next
step.
4. The spiral model, in which there is a process for developing a system in steps, and throughout the various steps, feedback is
obtained and incorporated back into the process.
INTRODUCTION TO THE EMBEDDED SYSTEM DESIGN PROCESS
Step-1: Creating the architecture
The model shown in figure 20.2, refer to as the Embedded Systems Design and Development Lifecycle Model. This model is based on
a combination of the popular waterfall and spiral industry models. The embedded system design and development process is divided
into three phases: creating the architecture, implementing the architecture, testing and maintaining the system. The initial conceptual
design phase of a new product involves envisioning a product based on market forecasts, customer needs, and technology roadmaps.
In product planning, a business case is made for the product with estimates for units sold, pricing, and margins. This results in an initial
product mock-up, a design specification, and product marketing plans. The most common of these challenges include:
Cost limitations
Working within the confines of available elemental functionality (i.e., processing power, memory, battery life, etc.)
Deterministic requirements
Embedded system architecture can be used to resolve these challenges early in a project. Without defining or knowing any of the
internal implementation details, the architecture of an embedded device can be the first tool to be analyzed and used as a high-level
blueprint defining the infrastructure of a design, possible design options, and design constraints. What makes the architectural
approach so powerful is its ability to informally and quickly communicate a design to a variety of people with or without technical
backgrounds, even acting as a foundation in planning the project or actually designing a device. Because it clearly outlines the
requirements of the system, architecture can act as a solid basis for analyzing and testing the quality of a device and its performance
under various circumstances.
Defining and understanding the architecture of an embedded system is an essential component of good system design. Every
embedded system has an architecture, whether it is or is not documented, because every embedded system is composed of interacting
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elements (whether hardware or software). An architecture by definition is a set of representations of those elements and their
relationships. Rather than having a faulty and costly architecture forced on you by not taking the time to define an architecture before
starting development, take control of the design by defining the architecture first.
THE EMBEDDED SYSTEMS MODEL
What the Embedded Systems Model indicates is that all embedded systems share one similarity at the highest level; that is, they all
have at least one layer (hardware) or all layers (hardware, system software and application software) into which all components fall.
The hardware layer contains all the major physical components located on an embedded board, whereas the system and application
software layers contain all of the software located on and being processed by the embedded system.
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Timing constraints include finish time, or both start time and finish time .However, they are not necessarily respond fast, but
must meet some timing deadline.
Single event
Or
Multiple events
(Input)
Real-Time System
Single output
Or
Multiple outputs
(Timing deadline)
A good way to understand the relationship between real-time systems and embedded systems is to view them as two intersecting
circles, as shown in figure 20.5. It can be seen that not all embedded systems exhibit real-time behaviors nor are all real-time systems
embedded. However, the two systems are not mutually exclusive, and the area in which they overlap creates the combination of
systems known as real-time embedded systems.
The most basic and essential characteristics of the real-time systems; they must produce correct computational results, called logical or
functional correctness, and that these computations must conclude within a predefined period, called timing correctness.
Real-time systems are defined as those systems in which the overall correctness of the system depends on both the functional
correctness and the timing correctness. The timing correctness is at least as important as the functional correctness. It is important to
note that we said the timing correctness is at least as important as the functional correctness. In some real-time systems, functional
correctness is sometimes sacrificed for timing correctness.
Similar to embedded systems, real-time systems also have substantial knowledge of the environment of the controlled system and the
applications running on it. This reason is one why many real-time systems are said to be deterministic, because in those real-time
systems, the response time to a detected event is bounded. The action (or actions) taken in response to an event is known a priori. A
deterministic real-time system implies that each component of the system must have a deterministic behavior that contributes to the
overall determinism of the system.
HARD AND SOFT REAL-TIME SYSTEMS
What differentiates hard real-time systems and soft real-time systems are the degree of tolerance of missed deadlines, usefulness of
computed results after missed deadlines, and severity of the penalty incurred for failing to meet deadlines.
For hard real-time systems, the level of tolerance for a missed deadline is extremely small or zero tolerance. The computed results after
the missed deadline are likely useless for many of these systems. The penalty incurred for a missed deadline is catastrophe. For soft
real-time systems, however, the level of tolerance is non-zero. The computed results after the missed deadline have a rate of
depreciation. The usefulness of the results does not reach zero immediately passing the deadline, as in the case of many hard real-time
systems. The physical impact of a missed deadline is non-catastrophic.
A hard real-time system is a real-time system that must meet its deadlines with a near-zero degree of flexibility. The deadlines must
be met, or catastrophes occur. The cost of such catastrophe is extremely high and can involve human lives. The computation results
obtained after the deadline have either a zero-level of usefulness or have a high rate of depreciation as time moves further from the
missed deadline before the system produces a response.
A soft real-time system is a real-time system that must meet its deadlines but with a degree of flexibility. The deadlines can contain
varying levels of tolerance, average timing deadlines, and even statistical distribution of response times with different degrees of
acceptability. In a soft real time system, a missed deadline does not result in system failure, but costs can rise in proportion to the
delay, depending on the application.
The weapons defense and the missile guidance systems are hard real-time systems. Using the missile guidance system for an
example, if the navigation system cannot compute the new coordinates in response to approaching mountain terrain before or at the
deadline, not enough distance is left for the missile to change altitude. This system has zero tolerance for a missed deadline. The new
coordinates obtained after the deadline are no longer useful because at subsonic speed the distance is too short for the altitude control
system to navigate the missile into the new flight path in time. The penalty is a catastrophic event in which the missile collides with the
mountain. Similarly, the weapons defense system is also a zero-tolerance system. The missed deadline results in the missile sinking
the destroyer, and human lives potentially being lost. Again, the penalty incurred is catastrophic.
On the other hand, the DVD player is a soft real-time system. The DVD player decodes the video and the audio streams while
responding to user commands in real time. The user might send a series of commands to the DVD player rapidly causing the decoder
to miss its deadline or deadlines. The result or penalty is momentary but visible video distortion or audible audio distortion. The DVD
player has a high level of tolerance because it continues to function. The decoded data obtained after the deadline is still useful.
SOFTWARE PARTITIONING
Code for embedded systems (such as the real-time embedded operating system, the system software, and the application software) is
commonly stored in ROM and NVRAM memory devices. Upgrading an embedded system can mean building new PROM, deploying
special equipment and/or a special method to reprogram the EPROM, or reprogramming the flash memory. The choice of software
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storage device has an impact on development. The process to reprogram an EPROM when small changes are made in the software
can be tedious and time-consuming, and this occurrence is common during development. Removing an EPROM device from its socket
can damage the EPROM; worse yet, the system itself can be damaged if careful handling is not exercised.
The choice of the storage device can also have an impact on the overall cost of maintenance. Although PROM and EPROM devices
are inexpensive, the cost can add up if a large volume of shipped systems is in the field. Upgrading an embedded system in these
cases means shipping replacement PROM and EPROM chips. The embedded system can be upgraded without the need for chip
replacement and can be upgraded dynamically over a network if flash memory or
EEPROM is used as the code storage device.
A personal computer is not an embedded system because it is built using a general-purpose processor and is built independently from
the software that runs on it. The software applications developed for personal computers, which run operating systems such as
FreeBSD or Windows, are developed natively (as opposed to cross-developed) on those operating systems. For the same reasons, an
Apple iBook used only as a DVD player is used like an embedded system but is not an embedded system.
HARDWARE AND SOFTWARE CO-DESIGN MODEL
Commonly both the hardware and the software for an embedded system are developed in parallel. Constant design feedback between
the two design teams should occur in this development model. The result is that each side can take advantage of what the other can
do. The software component can take advantage of special hardware features to gain performance. The hardware component can
simplify module design if functionality can be achieved in software that reduces overall hardware complexity and cost. Often design
flaws, in both the hardware and software, are uncovered during this close collaboration.
The hardware and software co-design model reemphasizes the fundamental characteristic of embedded systems they are applicationspecific. An embedded system is usually built on custom hardware and software. Therefore, using this development model is both
permissible and beneficial.
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CHAPTER-21
INTRODUCTION TO REAL-TIME OPERATING SYSTEM (RTOS)
Several software and hardware tools commonly support the programming of general-purpose processors. First, we
must distinguish between two processors we deal with when developing an embedded system. One processor is the
development processor, on which we write and debug our program. This processor is part of our desktop computer.
The other processor is the target processor, to which we will send our program and which will form part of our
embedded systems implementation. For example, we may develop our system on a Pentium processor, but use an
Intel 8051 as our target processor. Of course, sometimes the two processors happen to be the same, but this is
mostly a coincidence.
As we have discussed earlier that Assemblers translate assembly instructions to binary machine instructions. In
addition to just replacing op-code and operand mnemonics by binary equivalents, an assembler may also translate
symbolic labels into actual addresses. For example, a programmer may add a symbolic label END to an instruction A,
and may reference END in a branch instruction. The assembler determines the actual binary address of A, and
replaces references to END by this address. The mapping of assembly instructions to machine instructions is one-toone. A linker allows a programmer to create a program in separately-assembled files; it combines the machine
instructions of each into a single program, perhaps incorporating instructions from standard library routines.
Compilers translate structured programs into machine (or assembly) programs. Structured programming languages
possess high-level constructs that greatly simplify programming, such as loop constructs, so each high-level construct
may translate to several or tens of machine instructions. Compiler technology has advanced tremendously over the
past decades, applying numerous program optimizations, often yielding very size and performance efficient code. A
cross-compiler executes on one processor (our development processor), but generates code for a different processor
(our target processor). Cross-compilers are extremely common in embedded system development.
Debuggers help programmers evaluate and correct their programs. They run on the development processor and
support stepwise program execution, executing one instruction and then stopping, proceeding to the next instruction
when instructed by the user. They permit execution up to user-specified breakpoints, which are instructions that when
encountered cause the program to stop executing. Whenever the program stops, the user can examine values of
various memory and register locations. A source-level debugger enables step-by-step execution in the source program
language, whether assembly language or a structured language. A good debugging capability is crucial, as todays
programs can be quite complex and hard to write correctly. Device programmers burn or write a binary machine
program from the development processors memory into the target processors memory.
Emulators support debugging of the program while it executes on the target processor. An emulator typically
consists of a debugger coupled with a board connected to the desktop processor via a cable. The board consists of the
target processor plus some support circuitry (often another processor). The board may have another cable with a
device having the same pin configuration as the target processor, allowing one to plug this device into a real
embedded system. Such an in-circuit emulator enables one to control and monitor the programs execution in the
actual embedded system circuit. In circuit emulators are available for nearly any processor intended for embedded
use, though they can be quite expensive if they are to run at real speeds. The availability of low-cost or high-quality
development environments for a processor often heavily influences the choice of a processor.
AN OPERATING SYSTEM
An operating system is a layer of software that provides low-level services to the application layer, a set of one or
more programs executing on the CPU consuming and producing input and output data. The task of managing the
application layer involves the loading and executing of programs, sharing and allocating system resources to these
programs, and protecting these allocated resources from corruption by non-owner programs.
One of the most important resources of a system is the central processing unit (CPU), which is typically shared among
a number of executing programs. The operating system, thus, is responsible for deciding what program is to run next
on the CPU and for how long. This is called process/task scheduling and is determined by the operating systems
preemption policy. Another very important resource is memory, including disk storage, which is also shared among
the applications running on the CPU.
In addition to implementing an environment for management of high-level application programs, the operating system
provides the software required for servicing various hardware-interrupts, and provides device drivers for driving the
peripheral devices present in the system. Typically, on startup, an operating system initializes all peripheral devices,
such as disk controllers, timers and input/output devices and installs hardware interrupt (interrupts generated by the
hardware) service routines (ISR) to handle various signals generated by these devices. Then, it installs software
interrupts (Interrupts generated by the software) to process system calls (calls made by high-level applications to
request operating system services).
A system call is a mechanism for an application to invoke the operating system. This is analogous to a procedure or
function call, as in high-level programming languages and a subroutine call, as in assembly languages. When a
program requires some service from the operating system, it generates a predefined software interrupt that is
serviced by the operating system. Parameters specific to the requested services are typically passed from (to) the
application program to (from) the operating system through CPU registers. In summary, the operating system
abstracts away the details of the underlying hardware and provides the application layer an interface to the hardware
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through the system call mechanism. The operating system itself is loaded into memory by a small program that
typically resides in a special ROM and is always executed after a power-on reset. The operating system organizes and
controls the hardware and it is that piece of software that turns the collection of hardware blocks into a powerful
computing tool. Broadly the tasks of the Operating system are:
Processor Management: The main tasks in processor management are ensuring that each process and application
receives enough of the processor's time to function properly, using maximum processor cycles for real task as is
possible and switch between processes in a multi-tasking environment.
Memory and Storage Management: The tasks include allotting enough memory required for each process to execute and
efficiently use the different types of memory in the system.
Device Management: The operating system manages all hardware not on the computer's motherboard through driver
programs. Drivers provide a way for applications to make use of hardware subsystems without having to know every
detail of the hardware's operation. The driver's function is to be the translator between the electrical signals of the
hardware subsystems and the high-level programming languages of the operating system and application programs.
One reason that drivers are separate from the operating system is for upgradability of devices.
Providing Common Application Interface: Application program interfaces (APIs) let application programmers use
functions of the computer and operating system without having to directly keep track of all the details in the CPU's
operation. Once the programmer uses the APIs, the operating system, connected to drivers for the various hardware
subsystems, deals with the changing details of the hardware.
Providing Common User Interface: A user interface (UI) brings a formal structure to the interaction between a user and
the computer. Recently all developments in user interfaces have been in the area of the graphical user interface
(GUI). UNIX and Microsoft's Windows are the popular GUIs. Four types of Operating systems, based on the kind of
applications they support are:
i) Single-user, single task - This operating system is designed to manage the computer so that one user can
effectively do one thing at a time. The Palm OS for Palm hand-held computers is a good example.
ii) Single-user, multi-tasking - This is the type of operating system most of us use on our desktop and laptop
computers today. Windows and the MacOS are examples of OS that let a single user have several programs in
operation at the same time.
iii) Multi-user - A multi-user operating system allows many different users to take advantage of the computer's
resources simultaneously. The operating system must make sure that the requirements of the various users are
balanced, and that each of the programs they are using has sufficient and separate resources so that a problem with
one user doesn't affect the other users. UNIX is an example of multi-user operating system.
iv) Real-time operating system (RTOS) The main task of a RTOS is to manage the resources of the computer such
that a particular operation executes in precisely the same amount of time every time it occur. In a complex machine,
having a part move more quickly just because system resources are available may be just as catastrophic as having it
not to move at all because the system is busy.
Why is a desktop OS (General purpose OS, in short GPOS) not suited for real-time embedded system?
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Figure 21.1: High-level view of an RTOS, its kernel, and other components found in embedded systems
Figure 21.2 illustrates these components, each of which is described next. There are some functional similarities
existing between RTOS and GPOS, many important differences occur as well. These differences help explain why
RTOS are better suited for real-time embedded systems.
Some core functional similarities between a typical RTOS and GPOS include:
Faster performance,
Support for diskless embedded systems by allowing executables to boot and run from ROM or RAM, and
Kernel is the core supervisory software that provides minimal logic, scheduling, and resource-management
algorithms. Every RTOS has a kernel.
Scheduler-is contained within each kernel and follows a set of algorithms that determines which task
executes when. Some common examples of scheduling algorithms include round-robin and preemptive
scheduling.
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A regular process is a process that has its own virtual address space (stack, data, and code) and system
resources.
Tasks are like functions, each with its own stack and task control block (TCB). Unlike most functions,
however, a task is almost always an infinite loop. That is, once it has been created, it will never exit.
A thread, in contrast, is really a sub-process within a process. It is a lightweight process that typically has
only a program counter, stack and register; it shares its address space and system resources with other
threads. Since threads are small compared to regular processes, they can be created quickly, and switching
between threads by an operating system does not incur very heavy costs. Furthermore, threads can share
resources and variables so they can communicate quickly and efficiently.
Objects-are special kernel constructs that help developers create applications for real-time embedded
systems. Common kernel objects include tasks, semaphores, and message queues.
Services-are operations that the kernel performs on an object or, generally operations such as timing,
interrupt handling, and resource management.
Messages allow us to send data to one or more tasks. These messages can be of almost any size and are
usually implemented as a mailbox or a queue.
A mailbox is a FIFO (first-in, first-out) buffer and each item in the mailbox has a predefined fixed size.
A queue is a FIFO (first-in, first-out) buffer and each item in the queue has a dynamic size.
There are three major differences between queues and mailboxes:
1. Queues accept messages of various sizes.
2. Retrieving a message from the queue does not copy the message, but returns a pointer to the message
along with its size.
3. For queues, the retrieving function has to delete every queue message after processing it. Otherwise the
message will remain in the queue.
Event Flags are basically Boolean flags which tasks can set or reset that other tasks can wait for. Event flags
are used in cases where a task has to synchronize with occurrence of multiple events. A task can be
synchronized when any of the events have occurred as in disjunctive synchronization (logical OR) or may be
synchronized when all the events have occurred as in conjunctive synchronization (logical AND). More than
one task can wait for same event. RTOS can form groups of events and tasks can wait for any subset of
events in a group.
THE SCHEDULER
Scheduler is also known as Dispatcher. The heart and soul of any operating system is its scheduler. This piece of the
operating system decides which of the ready tasks has the right to use the processor (go into running state) at a
given time. Some of the common scheduling algorithms used in mainstream operating systems are first-in-first-out
(FIFO), shortest job first and round robin. The FIFO scheduling is used in DOS, which is not a multitasking operating
system. Here each task runs until it is finished and only after that next task is started. In shortest job first scheduler
each time a running task completes or blocks itself, next task selected is one that will require the least amount of
processor time to complete. Round robin is the only scheduling algorithm of the three in which the running task can
be pre-empted, that is, interrupted while it is running. In this case, each task runs for some predetermined amount of
time. After that interval has elapsed, the running task is preempted by the operating system and the next task in line
gets its chance to run.
Unfortunately embedded operating systems cannot use any of these simple scheduling algorithms. Embedded
systems, particularly real-time systems, almost always require a way to share the processor that allows the most
important tasks to grab the control of processor as soon as they need it. A deadline driven scheduling mechanism is
the ideal one. However, the current state of technology does not allow this. Therefore most embedded operating
systems utilize a priority based scheduling algorithm that supports pre-emption. We also need that interrupt handling
in case of different simultaneous interrupts should be handled in a preemptive way.
A good embedded RTOS should have provision for lot of priority levels. A number of high priority levels have to be
dedicated to the system processes and threads. And in a complex application with large number of threads, it is
essential to be able to place all the real-time threads on a different priority level above the non real-time threads.
There is also necessary to have a backup scheduling policy. This is the scheduling algorithm to be used in the event
that several ready tasks have same priority. The most common backup algorithm used is the round robin. If there are
no tasks in ready state when a scheduler is called, the idle task will be executed which is basically an infinite loop
that does nothing. Idle task will have the lowest priority and will always be in ready state.
The actual process of changing from one task to another is called a context switch. Since the contexts are processorspecific, the code that implements this is also processor-specific.
So it is always written in assembly language. For real-time systems the context switch should take only the bare
minimum of time because this determines the response.
Multitasking
Multitasking is the ability of the operating system to handle multiple activities within set deadlines. A real-time kernel
might have multiple tasks that it has to schedule to run. One such multitasking scenario is illustrated in figure 21.3.
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In this scenario, the kernel multitasks in such a way that many threads of execution appear to be running
concurrently; however, the kernel is actually interleaving executions sequentially, based on a preset scheduling
algorithm (see Scheduling Algorithms). The scheduler must ensure that the appropriate task runs at the right time.
An important point to note here is that the tasks follow the kernels scheduling algorithm, while interrupt service
routines (ISR) are triggered to run because of hardware interrupts and their established priorities.
As the number of tasks to schedule increases, so do CPU performance requirements. This fact is due to increased
switching between the contexts of the different threads of execution.
SCHEDULING ALGORITHMS
As mentioned earlier, the scheduler determines which task runs by following a scheduling algorithm (also known as
scheduling policy). Most kernels today support two common scheduling algorithms:
An event-driven scheduler can be either preemptive or non-preemptive. In a preemptive system each task can be
interrupted by a task which has a higher priority. In a non-preemptive system the executing task will finish its
execution, even if a task with higher priority becomes ready for execution during execution of a task.
Most real-time kernels (RTOS) use preemptive priority based scheduling by default. As shown in figure 21.5 with this
type of scheduling, the task that gets to run at any point is the task with the highest priority among all other tasks
ready to run in the system.
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With a preemptive priority-based scheduler, each task has a priority, and the highest-priority task runs first. If a task
with a priority higher than the current task becomes ready to run, the kernel immediately saves the current tasks
context and switches to the higher-priority task. As shown in figure 21.5, task-1 is preempted by higher-priority task2, which is then preempted by task 3. When task-3 completes, task-2 resumes; likewise, when task-2 completes,
task-1 resumes.
Although tasks are assigned a priority when they are created, a tasks priority can be changed dynamically using
kernel-provided calls. The ability to change task priorities dynamically allows an embedded application the flexibility to
adjust to external events as they occur, creating a true real-time, responsive system. Note, however, that misuse of
this capability can lead to priority inversions, deadlock, and eventual system failure.
Round-robin scheduling
The most common time-sharing algorithm is called Round-Robin. With round-robin scheduling, the scheduler has a list
of the tasks that make up the system and it uses this list to check for the next task that is ready to execute. If a task
is READY, that task will execute. Associated with each task is its time-slice. This time-slice is the maximum time a
task can execute for each round the scheduler makes. In other word, Round-robin scheduling provides each task an
equal share of the CPU execution time (see figure 21.6).
Task-2
Task-3
Service
Cycle
Task-1
Task-4
Figure 21.6: Round-robin scheduling
Pure round-robin scheduling cannot satisfy real-time system requirements because in real-time systems, tasks
perform work of varying degrees of importance. Instead, preemptive, priority based scheduling can be augmented
with round-robin scheduling which uses time slicing to achieve equal allocation of the CPU for tasks of the same
priority as shown in figure 21.7.
With time slicing, each task executes for a defined interval, or time slice, in an ongoing cycle, which is the round
robin. A run-time counter tracks the time slice for each task, incrementing on every clock tick. When one tasks time
slice completes, the counter is cleared, and the task is placed at the end of the cycle. Newly added tasks of the same
priority are placed at the end of the cycle, with their run-time counters initialized to 0. If a task in a round-robin cycle
is preempted by a higher-priority task, its run-time count is saved and then restored when the interrupted task is
again eligible for execution. This idea is illustrated in figure 21.7, in which task-1 is preempted by a higher-priority
task-4 but resumes where it left off when task-4 completes.
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PRIORITY INVERSION
Generally speaking, priority inversion occurs when two tasks of differing priority share a resource, and the higher priority task
cannot obtain the resource from the lower-priority task. To prevent this condition from exceeding a fixed and bounded interval of
time, an RTOS may provide a choice of mechanisms including priority inheritance and priority ceiling emulation. We could not
possibly do justice to both mechanisms here, so let us focus on a simple example of priority inheritance.
WHY OPERATING SYSTEMS FOR REAL-TIME APPLICATIONS
Operating system is not a required component of any computer system. A simple microwave oven does not require an
operating system. But as the complexity of applications expands beyond simple tasks the benefits of an operating
system far outweighs the associated costs. Since embedded systems (PDAs, cell phones, VCRs, industrial robot
control, or even the toaster) are becoming more complex hardware-wise with every generation, and more features
are put into them in each iteration, applications they run require more and more to run on actual operating system
code in order to meet the system response requirements and to keep the development time reasonable.
Real-time Operating System allows real-time applications to be designed and expanded easily. Functions can be added
without major changes to the software. The use of an RTOS further simplifies the design process by splitting the
application code into separate tasks. With a pre-emptive RTOS all time critical events are handled as quickly and
efficiently as possible. An RTOS allows one to make better use of the system resources by providing valuable services
such as semaphores, mailboxes, queues, time delays, time out etc.
TASK-ORIENTED DESIGN
Designing applications for an embedded application is almost always challenging, to say the least. One way to
decrease the complexity of our application is to use a task-oriented design and divide a project into different modules
(or tasks). Each module is then responsible for some part of the application. With such a system we would like to be
able to specify that some modules (or tasks) are more important than others. That is, some tasks have real-time
requirements. They have to respond quickly and correctly. If our system employs a professional RTOS, features that
prioritize tasks are already part of the package. In addition to task prioritization, a clean and well-tested API is
included that eases communicate between different tasks. So, if we think about using an RTOS we will have the tools
to:
Make complex applications easier to develop and maintain. Its easier to develop and maintain smaller tasks,
than to have to deal with the entire application as a whole.
Distribute different parts of the application among several developers. Each developer can be responsible for
one or more tasks within the application and a clean Application Programming Interface (API) will be available
for communication between the different modules/tasks as they are developed.
Applications can be divided into different tasks (modules) with or without the use of an RTOS. For example, one task
can be responsible for reading the keyboard, another for checking temperature, a third for printing messages on a
LCD screen, and so on. With an RTOS we not only get the tool to create tasks, but also tools to communicate between
the tasks, and tools to ensure that tasks that are time critical are executed in time. Since the interface between the
different tasks becomes very clean when using an RTOS we will save time both in development and in maintenance of
the application.
HOW DOES AN RTOS WORK?
The core of an RTOS is known as the kernel. An API is provided to allow access to the kernel for the creation of tasks,
among other things. A task is like a function that has its own stack, and a Task Control
Block (TCB). In addition to the stack, which is private to a task, each task control block holds information about the
state of that task.
The kernel also contains a scheduler. The scheduler is responsible for executing tasks in accordance with a scheduling
mechanism. The main difference among schedulers is how they distribute execution time among the various tasks
they are managing.
The heartbeat of the kernel is the system tick, often called just systick. For every system tick the kernel will check to
determine if a task switch needs to be performed. The system tick is often implemented using one of the hardware
timers within the microcontroller.
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Perhaps the best way to get started with an RTOS application is to think about how the application can be divided into
distinct modules. For example, a somewhat simple engine input control application could be divided into the following
modules:
Engine temperature
Oil pressure
RPM
User input
These modules can then be set up as tasks, or can be divided into sub-modules. For example:
Engine temperature
- Read engine temperature
- Update LCD with current temperature
Oil pressure
- Read current oil pressure
- Conduct emergency engine shutdown
RPM
- Read RPM
- Update LCD with current RPM
User input
- Get gas pedal angle
- Get current gear
This division into sub-modules can continue until each module is suitable to be handled by a single task.
CASE STUDIES
Some of the popular RTOSs are reviewed here to identify their salient features which make them suitable for different
embedded real-time applications. One of the General Purpose Operating Systems is also discussed here to highlight
why a General Purpose Operating System is not suitable for real-time applications.
QNX RTOS v6.1
The QNX RTOS v6.1 has a client-server based architecture. QNX adopts the approach of implementing an OS with a
10 Kbytes micro-kernel surrounded by a team of optional processes that provide higher-level OS services .Every
process including the device driver has its own virtual memory space. The system can be distributed over several
nodes, and is network transparent. The system performance is fast and predictable and is robust.
It supports Intel x86family of processors, MIPS, PowerPC, and Strong ARM. Documentation is extensive except for the
details on the APIs. QNX has successfully been used in tiny ROM-based embedded systems and in several-hundred
node distributed systems
VRTX
VRTX has multitasking facility to solve the real-time performance requirements found in embedded systems. Preemptive scheduling is followed ensuring the best response for critical applications. Inter-task communication is by use
of mailboxes and queues. Mailbox is equivalent to an event signal and events can pass data along with the event.
Queues can hold multiple messages and this buffering facility is useful when sending task produces messages faster
than the receiving task can handle them. Dynamic memory allocation is supported and allocation and release is in
fixed size blocs to ensure predictable response times. VRTX has been designed for development and target system
independence as well as real-time clock independence. VRTX provides core services which every microprocessor can
use to its advantage.
Embedded Linux
Due to its low cost and ease of customization, Linux has been shipped in many consumer devices. Devices covering
PDAs (like the Sharp Zaurus family), TomTom GPS navigation devices, residential gateways like the Linksys WRT54G
series or smartphones such as the Motorola exz series, Openmoko handsets, and the Nokia N900 and Nokia N9. A
Linux kernelbased operating system known as Android, developed by Google, has become a highly competitive
platform for smartphones and tablets. First introduced in 2008, in July 2012, Android's smartphone market share in
the United States was 52%.
The advantages of embedded Linux over proprietary embedded operating systems include multiple suppliers for
software, development and support; no royalties or licensing fees; a stable kernel; the ability to read, modify and
redistribute the source code. The technical disadvantages include a comparatively large memory footprint (kernel and
root file system); complexities of user mode and kernel mode memory access, and a complex device drivers
framework.
Windows CE 3.0
Windows CE 3.0 is an Operating system rich in features and is available for a variety of hardware platforms. It
exhibits true real-time behavior most of the times. But the thread creation and deletion has periodic delays of more
than 1 millisecond occurring every second. The system is complex and highly configurable. The configuration of CE 3.0
is a complicated process. The documentation does not give in depth knowledge about inner workings of the system
though the APIs are well documented. The system is robust and no memory leak occurs even under stressed
conditions. CE 3.0 uses virtual memory protection to protect itself against faulty applications.
pSOSystem/x86 2.2.6
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pSOS+ is a small kernel suitable for embedded applications. This uses the software bus to communicate between
different modules. The choice of module to be used can be done at compile time making it suitable for embedded
applications. System has a flat memory space. All threads share the same memory space and also share all objects
such as semaphores. So it has more chances of crashing. Around 239 usable thread priority levels available making it
suitable for Rate monotonic scheduling. pSOS has a multiprocessor version pSOS+m which can have one node as
master and a number of nodes as slaves. Failure in master will however lead to system crash. The Integrated
Development Environment is comprehensive and is available for both Windows and UNIX systems. The drawback of
this RTOS is that it is available only for selected processors and that lack of mutexes in some versions leads to priority
inversion.
VxWorks (Wind River Systems )
VxWorks is the premier development and execution environment for complex real-time and embedded applications on
a wide variety of target processors. Three highly integrated components are included with VxWorks; a high
performance scalable real-time operating system which executes on a target processor; a set of powerful crossdevelopment tools; and a full range of communications software options such as Ethernet or serial line for the target
connection to the host. The heart of the OS is the Wind microkernel which supports multi-tasking, scheduling, inter
task management and memory management. All other functionalities are through processes. There is no privilege
protection between system and application and also the support for communication between processes on different
processors is poor.
Windows NT
The overall architecture is good and may be a suitable RTOS for control systems that need a good user interface and
can tolerate the heavy recourse requirements demanded for installation. It needs hard disk and a powerful processor.
Configuration and user interaction requires a dedicated screen and keyboard. The choice of selecting components for
installation is limited and it is not possible to load and unload major components dynamically. Because of all these
limitations Windows NT not suitable for embedded applications. It is neither suitable for other real time applications
because of the following factors:
a) There are only 7 priority levels and there is no mechanism to avoid priority inversion
b) The Queue of threads waiting on a semaphore is held in a FIFO order. Here there is no regard for
priority, hampering the response times of highest priority tasks.
c) Though ISR responses are fast, the Deferred Procedure Calls (DPC) handling is a problem since they are
managed in a FIFO order.
d) The thread switch latency is high (~ 1.2 ms), which is not acceptable in many real-time applications.
RTOS FEATURES
Real time Operating systems play a major role in the field of embedded systems especially for mission critical
applications are involved. Selection of a particular RTOS for an application can be made only after a thorough study of
the features provided by the RTOS. Since IC memories are getting denser scaled down versions of general operating
systems are able to compete with traditional Real Time Operating Systems for the embedded product market. The
choice of Operating System generally comes after the selection of the processor and development tools. Every RTOS
is associated with a finite set of microprocessors and a suite of development tools. Hence the first step in choosing an
RTOS must be to make the processor, real-time performance and the budget requirements clear. Then look at the
available RTOS to identify the one which suits our application. Generally an RTOS for embedded application should
have the following features:
i) Open Source
ii) Portable
iii) ROM able
iv) Scalable
v) Pre-emptive
vi) Multi-tasking
vii) Deterministic
viii) Efficient Memory Management
ix) Rich in Services
x) Good Interrupt Management
xi) Robust and Reliable
Within the class of real-time embedded systems, the general feature is that system and its application are fixed for
the life of a product or the system. Thus there is a real need for a general purpose architecture which would be
flexible enough to meet the varied requirements of these systems(wide range of sensors, threats, and scenarios), but
which would still be dedicated and matched to an application through the use of special configurations of general
modules. Even though most of the current kernels (RTOS) are successfully used in today real-time embedded
systems, but they increase the cost and reduce flexibility. Next generation real-time operating systems would demand
new operating systems and task designs to support predictability, and high degree of adaptability.
References:
1. David E Simon, An Embedded Software Primer. Reading, MA: Addison-Wesley, 1999.
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2. Michael Barr, Programming Embedded systems in C and C++. CA : OReilly & Associates,1999.
3. Jean J Labrosse, MicroC/OS-II The Real-Time Kernel . 2nd ed. Gilroy, CA: CMP Books, 2002.
4. Dedicated Systems Experts, What makes a good RTOS. Brussels, Belgium: Dedicated Systems Experts, 2001.
5. James F. Ready, VRTX: A Real-Time Operating System for embedded Microprocessor Applications, IEEE Micro. 6(4), Aug.1986, pp.8-17.
6. John A. Stankovic, Krithi Ramamritham, The Design of the Spring Kernel, Proc. IEEE- Real-Time Systems Symposium, Dec.1987, pp.146-57.
7. Robert G Arnold, A Modular Approach to Real-Time Super systems, IEEE Transactions on Computers 31(5): May 1982, pp.358-98.
8. Brian Santo, Embedded Battle Royale, IEEE Spectrum, Dec. 2001, pp.36-41.
REVIEW QUESTIONS
1. What is message queue?
2. What is the role of a scheduler? How does it function?
3. What is the difference between a normal OS and RTOS?
4. What is preemption?
5. What is preemptive multi-tasking/time-sharing? What is its difference with co-operative multi-tasking/timesharing?
6. Threads are described as lightweight because switching between threads does not involve changing the
memory context - True/False?
7. What are the factors considered for a RTOS selection?
8. What is a semaphore?
9. What is preemptive multitasking?
10. What is non-preemptive multitasking?
11. What is time-slice?
..END
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PART- A (2 marks)
1. What is Micro controller?
2. What is the difference between microprocessor and micro controller?
3. List the addressing modes of 8051?
4. Explain the instructions used to access external RAM and ROM.
5. List the features of 8051 microcontroller?
6. Explain the interrupts of 8051 microcontroller?
7. What is the function of program counter in 8051?
8. Write about the jump statement?
9. Write about CALL statement in 8051?
10. Which peripheral will be added to the microcontroller to expend I/O pins?
PART-B (5 marks)
11. Explain the operating mode0 of 8051 serial ports?
12. Explain the operating mode2 of 8051 serial ports?
13. Explain the mode3 of 8051 serial ports?
14. With neat sketch explain the architecture of 8051 microcontroller.
15. Draw the Pin Diagram of 8051 and explain the function of various signals.
16. Draw the pin configuration of 8051, explain each pin.
17. Explain the memory structure of 8051.
18. Explain the I/O port structure of 8051.
19. Explain the instruction set of 8051.
20. Draw the format of SCON register. Explain different bits in it.
PART-C (10 marks)
21. Write an assembly language program to find Fibonacci Series of N given term.
22. Write an assembly language program for stepper motor control.
23. How is the microcontroller used for the traffic light control application?
24. Differentiate microprocessor from microcontroller in system design.
25. What are the advantages of 8051 microcontroller in motor control?
26. How is stepper motor interfaced with microcontroller?
27. Explain how microcontrollers can be used for the washing machine control
application. Use sketches.
28. Explain with a neat sketch how microcontrollers can be used for the stepper motor
control application.
29. Explain in the detail the process involved in the design of traffic light controller with
example.
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