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TDA 4862
Advanced Information
Bipolar IC
Features
IC for sinusoidal line-current consumption
Power factor approaching 1
Controls boost converter as an active
harmonics filter
Internal start-up with low current consumption
Zero current detector for discontinuous
operation mode
High current totem pole gate driver
Trimmed 1.4% internal reference
Undervoltage lock-out with hysteresis
Very low start-up current consumption
Pin compatible to world standard
Fast overvoltage regulator
Current sense input with internal low pass filter
P-DIP-8-1
P-DSO-8-1
P-DSO-8-1
Type
Ordering Code
Package
TDA 4862
Q67000-A8368
P-DIP-8-1
TDA 4862 G
Q67006-A8369
P-DSO-8-1
= New type
2003-12-01
TDA 4862
Description
The TDA 4862 is excellent convenient for designing a preconverter in ballasts and
switched mode power supplies with sinusoidal line current consumption and a power
factor approaching unity.
The TDA 4862 controls a boost converter as an active harmonics filter in a discontinuous
mode (free oscillating triangular shaped current mode).
The TDA 4862 comprises an internal start-up timer, a high gain voltage amplifier, an one
quadrant multiplier for approaching unity power factor, a zero current detector, PWM and
logic circuitry, and totem pole MOSFET gate driver.
Protective features are: input undervoltage lockout with hysteresis, VCC zener clamp,
cycle-by-cycle current limiting, output voltage limiting for fast and slow load changes up
to open circuit, and a sinking gate driver current activated whenever undervoltage mode
occurs.
The output voltage of this preconverter is regulated with high accuracy. Therefore the
device can be used for world-wide line voltages without switches.
The TDA 4862 is the improved version of the TDA 4817 with a pinout equivalent to world
standard.
TDA 4862 G
TDA 4862
V SENSE
V CC
V AOUT
GTDRV
MULTIN
GND
SENSE
DETIN
IEP01748
V SENSE
V CC
V AOUT
GTDRV
MULTIN
GND
SENSE
DETIN
IEP01749
Figure 1
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TDA 4862
VSENSE
VAOUT
ISENSE
DETIN
GND
Ground;
All voltages are measured with respect to GND. VCC should be
bypassed directly to GND with a 0.1 F or larger ceramic capacitor.
GTDRV
VCC
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TDA 4862
Functional Description
Introduction
Conventional electronic ballasts and switching power supplies are designed with a
bridge rectifier and bulk capacitor. Their disadvantage is that the circuit draws power
from the line when the instantaneous AC voltage exceeds the capacitors voltage. This
occurs near the line voltage peak and causes a high charge current spike with following
characteristics: the apparent power is higher than the real power that means low power
factor condition, the current spikes are non-sinusoidal with a high content of harmonics
causing line noise, the rectified voltage depends on load condition and requires a large
bulk capacitor, special efforts in noise suppression are necessary.
With the TDA 4862 preconverter a sinusoidal current is achieved which varies in direct
instantaneous proportion to the input voltage half sine wave and means a power factor
near 1. This is due to the appearance of almost any complex load like a resistive one at
the AC line. The harmonic distortions are reduced and comply with the IEC555 standard.
Operating Description
The TDA 4862 contains a wide bandwidth voltage amplifier used in a feedback loop, an
overvoltage regulator, an one quadrant multiplier with a wide linear operating range, a
current sense comparator, zero current detector, a PWM and logic circuitry, a totem-pole
MOSFET driver, an internal trimmed voltage reference, a restart timer and an
undervoltage lockout circuitry. These functional blocks are described below.
Voltage Amplifier
The voltage amplifier is internally compensated and yields a gain bandwidth of 0.8 MHz
and a phase margin of 80 degrees. The non-inverting input is biased at 2.5 V and is not
pinned out. The inverting input is sensing the output voltage via a resitive devider. The
voltage amplifier output VAOUT and the inverting input VSENSE are connected in a simplest
way via an external capacitor. It forms an integrator which monitors the average output
voltage over several line cycles. Typically the bandwidth is set below 20 Hz. ln order to
keep the output voltage constant the voltage amplifier output is connected to the
multiplier input for regulation.
Overvoltage Regulator
Fast changes of the output voltage cant be regulated by the integrator formed with the
voltage amplifier This occurs during initial start-up, sudden load removal, or output arcing
and leads to a current peak at the voltage amplifier input while the voltage amplifiers
differential input voltages remains zero. The peak current is flowing through the external
capacitor into VAOUT. Exceeding an internal defined margin causes a regulation circuitry
to reduce the multiplier output voltage.
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TDA 4862
2003-12-01
TDA 4862
2003-12-01
Figure 2
DETIN
SENSE
MULTIN
V AOUT
V SENSE
REF
Clamp
Filter
Clamp
Voltage
Amplifier
0.6 V
30 k
0.9 V
2.5 V / 1.9 V
5V
4V
Detector
10 pF
Multiplier
OverVoltage
Regulation
1.3 V
Clamp
Current
Comp
TDA 4862; G
11 V / 8.5 V
V CC
Undervoltage
Lockout
V CCZ-Clamp
Driver
and
Logic
Reference
Voltage
IEB01747
GND
GTDRV
V CC
TDA 4862
Block Diagram
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Figure 3
AC
90-270 V
V IN
RF-Filter
and
Rectifier
R2
12 k
C4
100 nF
R1
1.3 M
R3
100 k
GND
6
MULTIN 3
C3
100 F
C1
0.22 F
V AOUT
Voltage
OP
Multipler
+
PWM
Logic
Driver
C6
470 nF
TDA 4862 G
Current
OP
Detector
DETIN
5
R3
22 k
V Ref
V TH
D1
R8
1N4148
100
250 H
Tr1
1 V SENSE
4 SENSE
7 GTDRV
D2
Q1
BYP 101
R7
0.1
BUZ 334
C5
470 F
IES01750
R6
10 k
R5
1.6 M
400 V
V OUT
TDA 4862
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TDA 4862
VCC
Pin 8 VCC
VCC-GND Pin 8 ICCZ
Current into
GTDRV
Clamping current into GTDRV
Clamping current into GTDRV
max.
0.3
0
70
400 500
100
100
V
mA
observe Pmax
mA
mA
mA
observe Pmax
VGTDRV > VCC
VGTDRV < 0.3 V
0.3
0.3
0.3
10
10
17
6
17
17
50
V
V
V
V
mA
mA
VDETIN > 6 V
VDETIN < 0.9 V
40
150
Storage temperature
VVSENSE
VVAOUT
VMULTIN
VISENSE
IDETINH
IDETINL
Tj
Tstg
50
150
RthSA
RthSA
100
180
K/W
K/W
P-DIP-8-1
P-DSO-8-1
Voltage at
Voltage at
Voltage at
Voltage at
Current into
Current into
VSENSE
VAOUT
Pin 7 IGTDRV
Pin 7 IGTDCH
Pin 7 IGTDCL
min.
Notes
Pin 1
Pin 2
MULTIN Pin 3
ISENSE
Pin 4
DETIN
Pin 5
DETIN
Pin 5
Junction temperature
Operating Range
Parameter
Supply voltage
Z-current
Junction temperature
Voltage at ISENSE
1)
VCC
IZ
Tj
VISENSE
Notes
max.
VCCON VZ
1)
50
mA
observe Pmax
40
150
VZ
VCCON means VCCH has been exceeded but the supply voltage is still above VCCL. The device has switched from
standby to active. For VCCH and VCCL values see Electrical Characteristics. If 0 V < VCC < VCCON, the device
is in standby and output GTDRV is active low.
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TDA 4862
Electrical Characteristics
Unless otherwise stated, VCC = 12 V, 40 C < Tj < 150 C.
Parameter
Symbol
Limit Values
min.
typ.
max.
ICCL
Supply current, ON
ICCH
Supply current, dynamic ICCDY
75
200
mA
Output low
4.2
mA
fDETIN = 50 kHz,
CGTDRV = 1 nF
VCCH
VCCL
VCCHY
11
11.5
8.0
8.5
1.8
2.3
3.0
VZ
15
17
19
ICCZ = 50 mA
Voltage feedback
threshold
VFB
2.465
2.5
2.53
5
Tj = 25 C,
Pin 1 to Pin 2
Voltage feedback
threshold
VFB
2.45
2.55
Pin 1 to Pin 2
Line regulation
VFBL
mV
VCC = 10 V to 15 V
80
dB
IBVSENSE
GV
BW
0.8
MHz
Phase margin1)
80
Degr
2.2
IVAOUTH
12
mA
IVAOUTL
mA
VVAOUT = 0 V,
VVSENSE = 2.3 V
VVAOUT = 4 V,
VVSENSE = 2.8 V
Overall
Supply current, OFF
hysteresis
VCC clamp
Voltage Amplifier
1not
10
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TDA 4862
Symbol
Limit Values
min.
typ.
max.
VVAOUTH
3.8
4.3
5.0
VVAOUTL
0.9
IRVAOUT
20
30
45
IVAOUT = 0.2 mA
VVSENSE = 2.3 V
IVAOUT = 0.5 A
VVSENSE = 2.8 V
Overvoltage Regulator
Regulation current
VVAOUT = VMULTIN
= 4 V,
VISENSE = 0.5 V
Current Comparator
Input bias current
Input offset voltage
Max threshold voltage
Delay to output1)
IBISENSE 1
VISENSEO
25
mV
VMULTIN = 0 V,
VVAOUT = 2.4 V
VISENSEM 1.05
tPHL
1.25
1.5
250
ns
Detector
Upper threshold voltage VDETINU
(VDETIN increasing)
2.5
2.75
1.5
1.9
0.6
Input current
VDETINHY
IBDETIN
1
VDETINHC 4
VDETINLC
5
0.6
V
V
IDETIN = 5 mA
IDETIN = 5 mA
Hysteresis
1)not
11
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TDA 4862
Symbol
Limit Values
min.
typ.
max.
IBMULTIN
VAOUT
VMULTIN
VVAOUT
Multiplier gain 1)
Multiplier
A
0 to 3 0 to 4
VFB to VFB to
VFB + 1 VFB + 1.5
V
V
VVAOUT = 2.75 V
VMULTIN = 1.0 V
0.45
0.65
0.85
1/V
VMULTIN = 2 V
VVAOUT = VFB + 1 V
tDLY
75
190
400
0.8
1.8
V
V
VGTDRVH
9.4
8.7
VGTDRVU
2.0
2.6
Rise time 2)
tr
tf
100
40
IGTDRV = 20 mA
IGTDRV = 200 mA
IGTDRV = 20 mA
IGTDRV = 200 mA
IGTDRV = 50 mA
VCC increasing:
0 < VCC < VCCH,
VCC decreasing:
0 < VCC < VCCL
CGTDRV = 1 nF
CGTDRV = 1 nF
Restart Timer
Restart time delay
Gate Driver
Fall time
2)
1)
2)
12
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TDA 4862
CC
mA
CC
=3V
=3V
=1V
= 0.5 V
=2V
= 25 C
=3V
=3V
=1V
= 0.5 V
=2V
0
-50
0
0
V VSENSE
V VAOUT
V MULTIN
V ISENSE
V DETIN
10
15 V
V CC
20
IED01753
12
50
100 C 150
Tj
V CC
mA
V VSENSE
V VAOUT
V MULTIN
V ISENSE
V DETIN
Tj
IED01752
IED01754
100
V
V CCH
GV
11
dB
V CC = 12 V
3.0 < V VAOUT < 3.5 V
deg
80
T j = 25 C
30
A0
10
60
40
60
V CCL
20
7
-50
50
Semiconductor Group
0
10 -2 10 -1 10 0 10 1 10 2
100 C 150
Tj
13
90
120
150
kHz 10
f
2000-01-21
TDA 4862
V FB
IED01755
10
mV
IED01756
1.4
V CC =12 V
V ISENSE
V CC = 12 V
Pin 1 connected to Pin 2
1.0
0
-40 C
0.8
25 C
0.6
-5
150 C
0.4
-10
0.2
-15
-50
50
0
29
100 C 150
Tj
30
31
32
33 A 34
RVAOUT
IED01757
3.00
IED01758
1.4
4.0 V
V ISENSE
1/V
V DETIN
V CC
= 12 V
V MULTIN = 1 V
V VSENSE = GND
V ISENSE = GND
2.75
V
3.5 V
1.0
2.50
3.0 V
V DETINupper
0.8
2.25
0.6
2.75 V
2.00
0.4
V DETINlow
1.75
0.2
V VAOUT = 2.5 V
0
-50
Semiconductor Group
50
100 C 150
Tj
V 5
V MULTIN
14
2000-01-21
TDA 4862
IED01759
1.4
V MULTIN = 3 V
V ISENSE
IED01760
1.2
K
V
2V
= 12 V
=2V
= VFB + 1 V
V CC
V MULTIN
V VAOUT
1/V
0.9
1.0
1V
0.8
0.6
0.6
0.5 V
0.4
0.3
0.2
0
2.5
3.0
4.0
3.5
0
-50
4.5 V 5.0
V VAOUT
50
100 C 150
Tj
IED01761
240
s
IED01762
t DLY
V SAT
VCC = 12 V
T = 10 ms
t p = 200 s
220
VCC VGTDRVH
4 VGTDRVL at VCC = 7 V
200
3
180
2
VGTDRVL
160
140
-50
0
0
Semiconductor Group
50
100 C 150
Tj
100
200
300 mA 400
GTDRV
15
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TDA 4862
Package Outlines
GPD05025
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book Package Information.
Dimensions in mm
16
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TDA 4862
GPS05121
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book Package Information.
SMD = Surface Mounted Device
17
Dimensions in mm
2003-12-01
TDA 4862
Revision History:
Previous Version:1998-02-16
Page
Page
(in previous (in current
Version)
Version)
Ordering Code
Edition 1999-11-08
Published by Infineon Technologies AG
St.-Martin-Strasse 53
D-81541 Mnchen
18
2003-12-01