Assignment Number:

1
(data-flow modelling)
1. Design and simulate a 4 input NOR Gate program using
dataflow modeling in VHDL.
entity four_input is
port (a,b,c,d :in bit; x :out bit);
end four_input;
architecture nor1 of four_input is
begin
x<= not(a or b or c or d);
end nor1;

2. Design and simulate a 4 input NAND Gate program using

dataflow modeling in VHDL.
entity four_input is
port (a,b,c,d :in bit;
x :out bit);
end four_input;
architecture nand1 of four_input is
begin
x<= not(a and b and c and d);
end nand1;

3. Design and simulate a 3 input AND Gate program using

dataflow modeling in VHDL.
entity three_input is
port (a,b,d :in bit;
c :out bit);
end three_input;
architecture and1 of three_input is
begin
c<= a and b and d;
end and1;

4. Design and simulate a 3 input XOR Gate program using

dataflow modeling in VHDL.
entity three_input is
port (a,b,d :in bit;
c :out bit);
end three_input;
architecture xor1 of three_input is
begin

c<= a xor b xor d;

end xor1;

5. Design and simulate a 2 input EX-NOR Gate program using

dataflow modeling in VHDL.
entity two_input is
port (a,b :in bit;
c :out bit);
end two_input;
architecture xor1 of two_input is
begin
c<= a xor b;
end xor1;

6. Design and simulate a 3 input OR Gate program using dataflow

modeling in VHDL.
entity three_input is
port (a,b,d :in bit;

c :out bit);
end three_input;
architecture or1 of three_input is
begin
c<= a or b or d;
end or1;

7. Design and simulate a 3 input NAND Gate program using

dataflow modeling in VHDL.
entity three_input is
port (a,b,d :in bit;
c :out bit);
end three_input;
architecture nand1 of three_input
is begin
c<= not((a and b)and d);
end nand1;

8. Design and simulate a 3 input NOR Gate program using

dataflow modeling in VHDL.
entity three_input is

port (a,b,d :in bit;

c :out bit);
end three_input;
architecture nor1 of three_input is
begin
c<= not((a or b)or d);
end nor1;

9. Design and simulate a half adder in VHDL using dataflowmodeling style.

entity ha_1 is
port (a,b:in bit;s,c:out bit);
end ha_1;
architecture half_adder of ha_1 is
begin
c<=a and b;
s<= a xor b;
end half_adder;

10.
Design and simulate a full adder in VHDL using dataflowmodeling style.
entity fa2_df_model is
port(a,b,c: in bit; s,cout:out bit);
end fa2_df_model;
architecture arc_fa2_df_model of fa2_df_model is
signal x,y,w: bit;
begin
x<= a xor b;
y<= x and c;
w<= a and b;
s<= x xor c;
cout<= y or w;
end arc_fa2_df_model;

11.
Design and simulate a 2-1 Mux in VHDL using dataflowmodeling style.
entity mux2_1new is
port(a,b,c,d,in1,in2:in bit;out1:out bit);
end mux2_1new;
architecture mux1 of mux2_1new is
begin
out1<= ((not in1) and (not in2) and a) or
(not in1) and in2 and b)
or
(in1 and (not in2) and c)
or
(in1 and in2 and d);
end mux1;

12. Design and simulate a 4-1 Mux in VHDL using dataflowmodeling style.
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity multiplexer_4_1 is
port( a,b,c,d,x,y: in STD_LOGIC; dout : out STD_LOGIC );
end multiplexer_4_1;
architecture multiplexer_4_1_arc of multiplexer_4_1 is
begin
dout <= ((not x) and (not y) and a) or
((not x) and y and b) or
(x and (not y) and c) or
(x and y and d);
end multiplexer_4_1_arc;

13. Design and simulate an 8-1 Mux in VHDL using dataflowmodeling style.
entity mux_8_1 is

port(i:in bit_vector (7 downto 0);

s:in bit_vector (2 downto 0);
y:out bit);
end mux_8_1;
architecture arc_mux_8_1 of mux_8_1 is
begin
y<=
i(0) when(s="000") else
i(1) when(s="001") else
i(2) when(s="010") else
i(3) when(s="011") else
i(4) when(s="100") else
i(5) when(s="101") else
i(6) when(s="110") else
i(7) ;
end arc_mux_8_1;

14. Design and simulate a 16-1 Mux in VHDL using dataflowmodeling style.
entity mux_16_1 is
port(i:in bit_vector (15 downto 0);
s:in bit_vector (3 downto 0);
y:out bit);
end mux_16_1;
architecture arc_mux_16_1 of mux_16_1 is
begin
y<=
i(0) when(s="0000") else
i(1) when(s="0001") else
i(2) when(s="0010") else
i(3) when(s="0011") else
i(4) when(s="0100") else
i(5) when(s="0101") else
i(6) when(s="0110") else
i(7) when(s="0111") else

i(8) when(s="1000") else

i(10) when(s="1010") else
i(12) when(s="1100") else
i(14) when(s="1110") else
end arc_mux_16_1;

i(9) when(s="1001") else

i(11) when(s="1011") else
i(13) when(s="1101") else
i(15) ;

15. Design and simulate a l to 2 De- Mux in VHDL using dataflow

modeling style.
library ieee;
use ieee.std_logic_1164.all;
entity dmux_1t2 is
port (
input : in std_logic;
sel : in std_logic;
output0 : out std_logic;
output1 : out std_logic);
end dmux_1t2;
architecture dmux_1t2_ar of dmux_1t2 is
begin -- dmux_1t2_ar
output0 <=input and(not sel);
output1 <=input and sel;
end dmux_1t2_ar;

16. Design and simulate a 2-to-4-line decoder/de-multiplexer in

VHDL using dataflow- modeling style.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decoder2_4 is
port( a,b : in STD_LOGIC;
z : out STD_LOGIC_VECTOR(3 downto 0)
end decoder2_4;
architecture decoder_data of decoder2_4 is
signal a_bar, b_bar :std_logic;
begin
a_bar<= not a;
b_bar<= not b;
z(3)<= a_bar and b_bar ;
z(2)<= a and b_bar;
z(1)<= a_bar and b;
z(0)<= a and b;
end decoder_data;

);

17. Design and simulate a 3-to-8-line decoder/de-multiplexer in

VHDL using dataflow- modeling style.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decoder3_8 is
port(
din : in STD_LOGIC_VECTOR(2 downto 0);
dout : out STD_LOGIC_VECTOR(7 downto 0)
end decoder3_8;
architecture decoder3_8_arc of decoder3_8 is
begin
dout <=
("10000000") when (din="000") else
("01000000") when (din="001") else
("00100000") when (din="010") else
("00010000") when (din="011") else
("00001000") when (din="100") else
("00000100") when (din="101") else
("00000010") when (din="110") else
("00000001") ;
end decoder3_8_arc;

);

18. Design and simulate a Master Slave J-K Flip Flop in VHDL
using dataflow-modeling style.
library ieee;
use ieee.std_logic_1164.all;
entity master_slave_jk is
port(j,k,clk:in std_logic; q1,q1x,z1x:inout std_logic;
--master
q2,q2x,z2x: inout std_logic); --salve
end master_slave_jk;
architecture master_slave_jk_arc of master_slave_jk is
begin
process(clk)
begin
if clk='1' then
z1x<=(j and (not q2)) or ((not k)and q2);
q1<=z1x after 5 ns;
q1x<=not z1x after 5 ns;

else
z2x<=(q1 and (not q2)) or ((not q1x)and q2);
q2<=z2x after 5 ns;
q2x<=not z2x after 5 ns;
end if;
end process;
end master_slave_jk_arc;

19. Realize a circuit for the following function in VHDL using

data flow modeling.
Fl=m (0, 3, 5, 6, 9, 10, 12, 15)
00
00

01
11

01

11

10

1
1

10

1
1

F1 =0000+0011+0101+0110+1100+1111+1001+1010
+ A B C D+ A
BC D+
ABCD + A BC
D +A BC
D
= A B C D
VHDL Code:
entity qws19 is
port (a,b,c,d :in bit;
end qws19;

z :out bit);

architecture qws19_a of qws19 is

begin
z<=((not a) and (not b) and (not c) and (not d)) or
((not a)and(not b)and(c)and(d)) or
((not a) and (b) and ( not c) and (d)) or
((not a) and (b) and (c) and (not d)) or

--0000
--0011
--0101
--0110

((a) and (b) and (not c) and (not d)) or

((a) and (b) and (c) and(d)) or
((a)and (not b) and (not c)and (d))
or
(a and (not b) and (c) and (not d));
end qws19_a;

--1100
--1111
--1001
--1010

20. Design a circuit with two outputs has to implement the

following functions.
F(A,B,C,D)= )m (0, 2,4,6,7,9)+D(10,11)
G (A,B,C,D)= )m (2,4,9,10,15)+D(0,13,14)
K-Map:
00
00

01

01

11
1

10
1

00

01

11
10

F1=0_ _0 + 011_ +10_1

D
+ A BC + A B D
F1= A

00

01

11

10
1

11

10

x
1

G1=_010+0_00+11_1+1_01

CD
+ A C
D
+ABD+A
G1= B
D
C

entity qws20 is
port (a,b,c,d :in bit;
f,g :out bit);
end qws20;
architecture qws20_a of qws20 is
begin
--=0_ _0 + 011_ +1001
f<= ((not a)and(not d)) or ((not a)and(b)and(c)) or ((a)and(not
b)and(d));
--=_010+0_00+11_1+1_01

g<=((not b)and (c)and(not d)) or ((not a)and (not c)and(not d))or

((a)and(b)and(d)) or ((a)and (not c)and (not d));
end qws20_a;

21. Design and simulate a half -Subtractor in VHDL using

dataflow-modeling style.
entity hs_1 is
port (a,b:in bit;d,br:out bit);
end hs_1;
architecture half_sub of hs_1 is
begin
br<=a and (not b);
d<= a xor b ;
end half_sub;

22. Design and simulate a Full -Subtractor in VHDL using

dataflow-modeling style.
entity fs_1 is
port (a,b,c1 :in bit;
d,br :out bit);

end fs_1;
architecture full_sub of fs_1 is
begin
d<=(a xor b) xor c1;
br<= ((not a) and b) or (b and c1) or ((not a) and c1);
end full_sub;

23. Design a BCD to 7-Segment Decoder in VHDL using dataflowmodeling style.

entity bcd_7 is
port(b0,b1,b2,b3:in bit; a,b,c,d,e,f,g,h:out bit);
end bcdto7;
architecture bcd_7_a of bcd_7 is
begin
a<=b3 or b1 or (b2 and b0) or ((not b2) and (not b0));
b<=(not b2) or ((not b1) and (not b0)) or (b1 and b0);
c<=( not b1) or b0 or b2;
d<= b3 or (b1 and (not b0)) or (( not b2 )and b1) or ((not b2) and
(not b0)) or( b2 and (not b1) and b0);
e<= (b1 and (not b0)) or(( not b2 )and (not b0));
f<= b3 or ((not b1) and (not b0)) or ((not b2) and (not b0)) or (b2
and (not b1));
g<= b3 or (b2 and (not b1)) or (b1 and (not b0)) or ((not b2) and
b1);
end bcd_7_a;

24. Realize a circuit for the following function in VHDL using

data flow modeling. F1= m (0, 3, 5, 6, 9, 10, 12, 15)+ D (2,14)
K-Map:
00
00

01
11
10

01

11

10

1
1

1
1

X
1

F1=10_ _+001_+ 0101+111_+0101+1001+11_0+00_0

entity fun_24 is
port(a,b,c,d:in bit;y:out bit);
end fun_24;
architecture fun242 of fun_24 is
signal a1,a2,a3,a4,a5,a6,a7,a8:bit;
begin
--10_ _++++
a1<=((not a)and (not b)and c);
--001_
a2<= ((not a)and (not b)and(not d));
--00_0
a3<= ((not a)and (b)and(not c)and(d)); --0101
a4<= ( a and b and c);
--111_
a5<= ( a and b and (not d));
--11_0
a6<= ( a and(not b) and (not c) and d); --1001
a7<= ((not a) and b and (not c) and d); -- 0101
a8<=( c and (not d));
--_ _10
y<= a1 or a2 or a3 or a4 or a5 or a6 or a7 or a8;

end fun242;

25. Realize a circuit for the following function in VHDL using

data flow modeling. F1= m (0, 1, 2, 3, 11, 12, 14, 15)

00

00

01

11

10

01
11

10

F1=00_ _ +11_0 + 111_+1_11

ABC + ACD
= A B + AB D+
entity qstn_25 is
port(a, b, c, d:in bit; y:out bit);
end qstn_25;
architecture qs_25 of qstn_25 is
signal a1,a2,a3:bit;
begin
a1<= (not a) and (not b);
a2<= a and b and (not d);
a3<= a and b and c;
a4<= a and d and c;
y<= a1 or a2 or a3;
end qs_25;

26. Realize a BCD to Excess 3 code converter using minimum

number of NAND gates in VHDL using Dataflow Modeling.
entity bcd_7_ex3 is
port(a,b,c,d:in bit;w,x,y,z:out bit);
end bcd_7_ex3;
architecture bcd_7_ex3_a of bcd_7_ex3 is
signal
signal
signal
signal

h1,h2,h3: bit;
w1,w2,w3: bit;
x1,x2,x3,x4,x5,x6: bit;
y1,y2: bit;

begin
w1<= a nand a;
w2<= b nand c;
w3<= b nand d;
h1<= ((w1 nand w2)nand w3);
w<=h1 nand h1;
x1<= b nand b;
x2<= x1 nand c;
x3<= x1 nand d;
x4<= c nand c;
x5<= d nand d;
x6<= ((x4 nand x5)nand b);
h2<= ((x2 nand x3)nand x6);
x<=h2 nand h2;
y1<=c nand d;

y2<=x4 nand x5;

y<=y1 nand y2;
z<=x5;
end bcd_7_ex3_a;

27. Realize a Excess 3 to BCD code converter using minimum

number of NAND gates in VHDL using Dataflow Modeling.
entity ex3_bcd_7 is
port(x1,x2,x3,x4:in bit;a,b,c,d:out bit);
end ex3_bcd_7;
architecture ex3_bcd_7_a of ex3_bcd_7 is
signal a1,a2,a3,a4,a5: bit;
signal f1,f2,f3,f4: bit;
signal k2,k3: bit;
begin
a1<=x3 nand x4; a2<=x2 nand x2;
a3<= a1 nand a2;
a4 <=a3 nand x1;
a<= a4 nand a4;
f1<=x3 nand x4; f2<=f1 nand x2;
f3<=f2 nand f1; f4<=f2 nand x2;
b<=f3 nand f4;
k2<=a1 nand x3; k3<=a1 nand x4;
c<=k2 nand k3;
d<=x4 nand x4;
end ex3_bcd_7_a;

28.

Realize 2-bit Comparator using gates in VHDL in Dataflow.

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY comparator IS
port(A0,A1,B0,B1: in std_logic;
X,Y,Z: out std_logic);
END comparator;
architecture behaviour of comparator is
begin
COMP:PROCESS(A0,A1,B0,B1)
begin
X<=((A1 and not B1)
or (A1 and A0 and not B0)
or (A0 and not B1 and not B0));
Y<=((not A1 and not A0 and not B1 and not B0)
or (not A1 and A0 and not B1 and B0)
or (A1 and not A0 and B1 and not B0) or (A1 and A0 and B1 and B0));
Z<=((not A1 and B1)
or (not A1 and not A0 and B0)
or (not A0 and B1 and B0));
end process COMP;
end behaviour;

29. Realize 4-bit Comparator using gates in VHDL using

Dataflow.
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY comparator IS
port(A0,A1,A2,A3,B0,B1,B2,B3: in std_logic;
X,Y,Z: out std_logic);
END comparator;
architecture behaviour_1 of comparator is
begin
COMP:PROCESS(A0,A1,A2,A3,B0,B1,B2,B3)
begin
X<=((A3 AND (NOT B3)) OR(A2 AND (NOT B2)) OR(A1 AND (NOT B1)) OR(A0
AND (NOT B0)));
Y<=(A3 XNOR B3) AND (A2 XNOR B2)

AND (A1 XNOR B1) AND (A0 XNOR B0);

Z<=((B3 AND (NOT A3)) OR(B2 AND (NOT A2)) OR(B1 AND (NOT A1)) OR(B0
AND (NOT A0)));
end process COMP;
end behaviour_1;

30.

Realize a 4 to 1 Mux using WITH SELECT Statement in VHDL.

entity mux4_1 is
port(a,b,c,d:in bit_vector(3 downto 0);
s: in bit_vector(0 to 1);
y: out bit_vector(3 downto 0));
end mux4_1;
architecture mux_arc4_1_4b of mux4_1 is
begin
y<= a when (s="00") else b when (s="01") else c when (s="10")
else d;
end mux_arc4_1_4b;

31.

Realize a 4- to 1 Mux using WHEN -ELSE Statement in VHDL.

entity mux4_1 is
port(a,b,c,d:in bit_vector(3 downto 0);
s: in bit_vector(0 to 1);
y: out bit_vector(3 downto 0));
end mux4_1;

architecture mux_arc4_1_4b of mux4_1 is

begin
y<= a when (s="00") else b when (s="01") else c when (s="10")
else d;
end mux_arc4_1_4b;

32. Realize a BCD to 7 Segment Converter using WITH SELECT

Statement in VHDL.
library ieee;
use ieee.std_logic_1164.all;
entity bcd_7_1 is
port(b:in std_logic_vector(0 to 3);y:out std_logic_vector(0 to 6));
end bcd_7_1;
architecture qstn of bcd_7_1 is
begin
with b select
y<= "1111110" when"0000",
"0110000" when"0001",
"1101101" when"0010",
"1111001" when"0011",
"0110011" when"0100",
"1011011" when"0101",
"1011111" when"0110",
"1110000" when"0111",

"1111111" when"1000",
"1111011" when"1001",
"0000000" when others;
end qstn;

33. Realize a BCD to 7 Segment Converter using WHEN -ELSE

Statement in VHDL.
library ieee;
use ieee.std_logic_1164.all;
entity bcd_7_1 is
port( s:in std_logic_vector(0 to 3);
y:out std_logic_vector(0 to 6));
end bcd_7_1;
architecture qstn33 of bcd_7_1 is
begin
y<= "1111110"
"0110000"
"1101101"
"1111001"
"0110011"
"1011011"
"1011111"
"1110000"
"1111111"
"1111011"
"0000000"
end qstn33;

when
when
when
when
when
when
when
when
when
when
;

(s="0000")
(s="0000")
(s="0010")
(s="0011")
(s="0100")
(s="0101")
(s="0110")
(s="0111")
(s="1000")
(s="1001")

else
else
else
else
else
else
else
else
else
else

34.

Realize a Toggle Flip Flop in VHDL using Dataflow Modeling.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tff is
port (T,Reset,CLK,CLK_enable: in std_logic;
Q: out std_logic);
end tff;
architecture tff_a of tff is
signal temp: std_logic:='0';
begin
process (Reset,CLK)
begin
if (rising_edge(CLK)) then
if Reset='1' then
temp <= '0';
elsif CLK_enable ='1' then
temp <= T xor temp;
end if;
end if;
end process;
Q <= temp;
end tff_a;

35.

Realize a Delay Flip flop in VHDL using Dataflow Modeling.

library ieee;
library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity D_FF is
PORT( D,CLOCK: in std_logic;
Q: out std_logic);
end D_FF;
architecture behavioral of D_FF is
begin
process(CLOCK)
begin
if(CLOCK='1' and CLOCK'EVENT) then
Q <= D;
end if;
end process;
end behavioral;

36.

Realize a Priority Encoder using Dataflow in VHDL.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;

entity priority_encoder_8_3 is
port(
din : in STD_LOGIC_VECTOR(7 downto 0);
dout : out STD_LOGIC_VECTOR(2 downto 0)
);
end priority_encoder_8_3;
architecture priority_enc_arc of priority_encoder_8_3 is
begin
dout <= "000" when din(7)='1' else
"001" when din(6)='1'else
"010" when din(5)='1' else
"011" when din(4)='1' else
"100" when din(3)='1' else
"101" when din(2)='1' else
"110" when din(1)='1' else
"111" when din(0)='1';
end priority_enc_arc;

37.

Realize a 4-bit binary Full adder with fast carry.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Partial_Full_Adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
P : out STD_LOGIC;
G : out STD_LOGIC);
end Partial_Full_Adder;
architecture Behavioral of Partial_Full_Adder is

begin
S <= A xor B xor Cin;
P <= A xor B;
G <= A and B;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Carry_Look_Ahead is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end Carry_Look_Ahead;
architecture Behavioral of Carry_Look_Ahead is
component Partial_Full_Adder
Port ( A : in STD_LOGIC;B : in STD_LOGIC;Cin : in STD_LOGIC;
S : out STD_LOGIC;P : out STD_LOGIC;G : out STD_LOGIC);
end component;
signal c1,c2,c3: STD_LOGIC;
signal P,G: STD_LOGIC_VECTOR(3 downto 0);
begin
PFA1:
PFA2:
PFA3:
PFA4:

Partial_Full_Adder
Partial_Full_Adder
Partial_Full_Adder
Partial_Full_Adder

port
port
port
port

map(
map(
map(
map(

A(0),
A(1),
A(2),
A(3),

B(0),
B(1),
B(2),
B(3),

Cin, S(0), P(0), G(0));

c1, S(1), P(1), G(1));
c2, S(2), P(2), G(2));
c3, S(3), P(3), G(3));

c1 <= G(0) OR (P(0) AND Cin);

c2 <= G(1) OR (P(1) AND G(0)) OR (P(1) AND P(0) AND Cin);
c3 <= G(2) OR (P(2) AND G(1)) OR (P(2) AND P(1) AND G(0)) OR
(P(2) AND P(1) AND P(0) AND Cin);
Cout <= G(3) OR (P(3) AND G(2)) OR (P(3) AND P(2) AND G(1)) OR
(P(3) AND P(2) AND P(1) AND G(0)) OR (P(3) AND P(2) AND P(1) AND
P(0) AND Cin);
end Behavioral;

38. Design and implement in VHDL a Four variable majority

function.
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

F
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
1

F=m(7,11,14,15) = 0111+1011+1110+1111
entity qstn_38 is
port(a,b,c,d:in bit;f:out bit);
end qstn_38;
architecture qs_38_a of qstn_38 is
begin
f<= (
(( not a) and b and c and d) or
(a and (not b) and c and d) or
(a and b and c and (not d)) or
(a and b and c and d) );

end qs_38_a;

39.

Design and Realize the below problem in VHDL.

From the given truth table we can infer that:

i

Red lights up when input A=0 and B=0 also when A=0 and B=1; which leads
to the conclusion, Red light glows when A=0 and B=Dont-care.

ii

Yellow light glows when A=0 and B=1; and also when A=1 and B=1; which
leads to the conclusion, Yellow light glows when B=1 and A=Dont-care.

iii

Green glows only when A=1 AND B =0;

Thus we can conclude that

a
b
c

For Red
<= A ;
For Yellow <= B;
For Green <= A and B

entity Traffic_light is
port (a,b :in bit;
Red,Yellow,Green :out bit);
end Traffic_light;
architecture Traffic_light_a of Traffic_light is
begin
Red
<= not a ;
Yellow <= b;
Green <= a and (not b);
end Traffic_light_a;