HT9170B/HT9170D

DTMF Receiver
Features
Tristate data output for MCU interface

Minimal external components

3.58MHz crystal or ceramic resonator

No external filter is required

1633Hz can be inhibited by the INH pin

Low standby current (on power down mode)

HT9170B: 18-pin DIP package

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Operating voltage: 2.5V~5.5V

HT9170D: 18-pin SOP package

Excellent performance

General Description
The HT9170B/D are Dual Tone Multi Frequency (DTMF)
receivers integrated with digital decoder and bandsplit
filter functions as well as power-down mode and inhibit
mode operations. Such devices use digital counting
techniques to detect and decode all the 16 DTMF tone
pairs into a 4-bit code output.

Highly accurate switched capacitor filters are implemented to divide tone signals into low and high group
signals. A built-in dial tone rejection circuit is provided to
eliminate the need for pre-filtering.

Selection Table
Function

OSC
Frequency

Tristate
Data Output

Power
Down

1633Hz
Inhibit

DVB

HT9170B

2.5V~5.5V

3.58MHz

18 DIP

HT9170D

2.5V~5.5V

3.58MHz

18 SOP

X 2

V N

V re f
G e n e ra to r

R T /G T

E S T

D V

Package

D V B

S te e r in g C o n tr o l C ir c u it

L o w G ro u p
F ilte r

F re q u e n c y

P r e - F ilte r

D e te c to r

H ig h G r o u p
F ilte r

C o d e
D e te c to r

L a tc h
&
O u tp u t
B u ffe r

D 0
D 1
D 2
D 3

IN H

O E

ww

w.

G S

O P A

B ia s
C ir c u it

em

V P

3 .5 8 M H z
C ry s ta l
O s c illa to r

el

X 1

V R E F

en

P W D N

tz

Block Diagram

on

Operating
Voltage

DV

Part No.

Rev. 1.11

February 23, 2009

HT9170B/HT9170D
Pin Assignment
1

1 8

V D D

V P
1

1 8

V D D

1 7

R T /G T

V N
2

1 7

R T /G T

G S
3

1 6

E S T

G S
3

1 6

E S T

V R E F
4

1 5

D V

V R E F

IN H
5

1 4

D 3

IN H

P W D N
6

1 3

D 2

P W D N

X 1
7

1 2

D 1

X 1

X 2
8

1 1

D 0

X 2

V S S
9

1 0

O E

V S S

H T 9 1 7 0 B
1 8 D IP -A

VP

I/O

Internal
Connection

Operational
Amplifier

1 5

D V

1 4

D 3

1 3

D 2

1 2

D 1

1 1

D 0

1 0

O E

H T 9 1 7 0 D
1 8 S O P -A

Pin Description
Pin Name

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V P
V N

Description
Operational amplifier non-inverting input

Operational amplifier inverting input

GS

Operational amplifier output terminal

VREEF

X1

X2

PWDN

VREF

on

VN

Reference voltage output, normally VDD/2

CMOS IN
Pull-low

Active high. This enables the device to go into power down mode and inhibits
the oscillator. This pin input is internally pulled down.

INH

CMOS IN
Pull-low

Logic high. This inhibits the detection of tones representing characters A, B, C

and D. This pin input is internally pulled down.

VSS

OE

CMOS IN
Pull-high

D0~D3

CMOS OUT
Tristate

EST

en

em

Receiving data output terminals

OE=H: Output enable
OE=L: High impedance
Data valid output
When the chip receives a valid tone (DTMF) signal, the DV goes high; otherwise it remains low.

CMOS OUT

Early steering output (see Functional Description)

I/O

CMOS IN/OUT

Tone acquisition time and release time can be set through connection with external resistor and capacitor.
Positive power supply, 2.5V~5.5V for normal operation

ww

VDD

D0~D3 output enable, high active

CMOS OUT

w.

RT/GT

Negative power supply, ground

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DV

tz

oscillator

The system oscillator consists of an inverter, a bias resistor and the necessary
load capacitor on chip.
A standard 3.579545MHz crystal connected to X1 and X2 terminals implements the oscillator function.

Rev. 1.11

February 23, 2009

HT9170B/HT9170D
Approximate internal connection circuits
V R E F

C M O S IN
P u ll- h ig h

O S C IL L A T O R
X 1

V O P A
V +

V N
V P

X 2
E N

O P A

G S

1 0 M

2 0 p F

1 0 p F

C M O S IN
P u ll- lo w

C M O S IN /O U T

C M O S O U T

C M O S O U T
T r is ta te

Absolute Maximum Ratings

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O P E R A T IO N A L
A M P L IF IE R

Storage Temperature ............................-50C to 125C

Input Voltage..............................VSS-0.3V to VDD+0.3V

Operating Temperature...........................-20C to 75C

on

Supply Voltage ............................................-0.3V to 6V

tz

Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

D.C. Characteristics
Parameter

VDD

Operating Voltage

IDD

Operating Current

Test Conditions

Min.

Typ.

Max.

Unit

2.5

5.5

5V

3.0

mA

5V

PWDN=5V

10

25

mA

1.0

4.0

0.1

mA
mA

en

Symbol

Ta=25C

VDD

Conditions

Standby Current

Low Input Voltage

5V

VIH

High Input Voltage

5V

IIL

Low Input Current

5V

VVP=VVN=0V

IIH

High Input Current

5V

VVP=VVN=5V

0.1

ROE

Pull-high Resistance (OE)

5V

VOE=0V

60

100

150

kW

RIN

Input Impedance (VN, VP)

5V

10

MW

-0.4

-0.8

mA

w.

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ISTB
VIL

Source Current (D0~D3, EST, DV)

5V

VOUT =4.5V

IOL

Sink Current (D0~D3, EST, DV)

5V

VOUT =0.5V

fOSC

System Frequency

5V

Crystal=3.5795MHz

1.0

2.5

mA

3.5759

3.5795

3.5831

MHz

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IOH

Rev. 1.11

February 23, 2009

HT9170B/HT9170D
A.C. Characteristics
Symbol

fOSC=3.5795MHz, Ta=25C
Test Conditions

Parameter

Min.

Typ.

Max.

-36

-6

-29

10

dB

10

dB

18

dB

-12

dB

-16

dB

1.5

3.5

30

ms

10

MW

0.1

mA

25

mV

60

dB

60

dB

65

dB

1.5

MHz

4.5

VPP

50

kW

100

pF

3.0

VPP

ms

Conditions

VDD

Unit

3V
Input Signal Level
5V

tPU

Twist Accept Limit (Positive)

5V

Twist Accept Limit (Negative)

5V

Dial Tone Tolerance

5V

Noise Tolerance

5V

Third Tone Tolerance

5V

Frequency Deviation Acceptance

5V

Frequency Deviation Rejection

5V

Power Up Time (See Figure 4.)

5V

Gain Setting Amplifier

Input Resistance

5V

IIN

Input Leakage Current

5V

VOS

Offset Voltage

5V

PSRR

Power Supply Rejection

5V

Common Mode Rejection

5V

AVO

Open Loop Gain

5V

fT

Gain Band Width

VOUT

Output Voltage Swing

RL

Load Resistance (GS)

CL

Load Capacitance (GS)

VCM

Common Mode Range

100 Hz
-3V<VIN<3V

5V
5V

en

5V

5V
5V

RL>100kW

No load

em

Steering Control

VSS<(VVP,VVN)<VDD

tz

CMRR

on

RIN

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DTMF Signal
dBm

Tone Present Detection Time

16

22

tDA

Tone Absent Detection Time

8.5

ms

tACC

Acceptable Tone Duration

42

ms

tREJ

Rejected Tone Duration

20

ms

tIA

Acceptable Inter-digit Pause

42

ms
ms

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tDP

Rejected Inter-digit Pause

20

Propagation Delay (RT/GT to DO)

11

ms

tPDV

Propagation Delay (RT/GT to DV)

12

ms

tDOV

Output Data Set Up (DO to DV)

4.5

ms

tDDO

Disable Delay (OE to DO)

300

ns

Enable Delay (OE to DO)

50

60

ns

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tIR
tPDO

tEDO

Note: DO=D0~D3

Rev. 1.11

February 23, 2009

HT9170B/HT9170D
V

0 .1 m F

2
3
4

1 0 0 k W
5
6

3 .5 7 9 5 4 5 M H z
8

2 0 p F

2 0 p F

V P

V D D

V N

R T /G T

G S

E S T

1 5

IN H

D 3

P W D N

D 2

X 1

D 1

X 2

D 0

V S S

O E

H T 9 1 7 0 B /D

Overview

i2

R 1

C 2

R 2

V P
V N

R 3

R 4

tz

em

C 1

When the voltage of RT/GT changes from 0 to VTRT

(2.35V for 5V supply), the input signal is effective, and
the correct code will be created by the code detector. After D0~D3 are completely latched, DV output becomes
high. When the voltage of RT/GT falls down from VDD to
VTRT (i.e.., when there is no input tone), DV output becomes low, and D0~D3 keeps data until a next valid
tone input is produced.

en

( a ) S ta n d a r d in p u t c ir c u it
i1

R 5

el

G S

H T 9 1 7 0 B /D

By selecting adequate external RC value, the minimum acceptable input tone duration (tACC) and the minimum acceptable inter-tone rejection (tIR) can be set. External
components (R, C) are chosen by the formula (refer to Figure 5.):

V R E F

( b ) D iffe r e n tia l in p u t c ir c u it
Figure 2. Input operation for amplifier application circuits

w.

tACC=tDP+tGTP;
tIR=tDA+tGTA;

The pre-filter is a band rejection filter which reduces the

dialing tone from 350Hz to 400Hz.

where tACC: Tone duration acceptable time

tDP: EST output delay time (LH)

The low group filter filters low group frequency signal

output whereas the high group filter filters high group
frequency signal output.

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tGTP: Tone present time

tIR: Inter-digit pause rejection time
tDA: EST output delay time (HL)

Each filter output is followed by a zero-crossing detector

with hysteresis. When each signal amplitude at the output exceeds the specified level, it is transferred to full
swing logic signal.

Rev. 1.11

1 0

The timing is shown in Figure 3. The EST pin is normally

low and draws the RT/GT pin to keep low through discharge of external RC. When a valid tone input is detected, EST goes high to charge RT/GT through RC.

H T 9 1 7 0 B /D

V R E F

1 1

on

V N

G S

1 2

The steering control circuit is used for measuring the effective signal duration and for protecting against drop
out of valid signals. It employs the analog delay by external RC time-constant controlled by EST.

V P

R F

1 3

Steering control circuit

An operational amplifier is built-in to adjust the input signal (refer to Figure 2).

3 0 0 k W

1 4

When input signals are recognized to be effective, DV

becomes high, and the correct tone code (DTMF) digit is
transferred.

The HT9170B/D tone decoders consist of three band

pass filters and two digital decode circuits to convert a
tone (DTMF) signal into digital code output.

1 6

V R E F

Functional Description

R 1

1 7

D V

Figure 1. Test circuit

0 .1 m F

1 8

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1 0 0 k W

T o n e

D D

tGTA: Tone absent time

February 23, 2009

HT9170B/HT9170D
Timing Diagrams
tR

E J

t IR

t IA

tD

tD
P

T o n e n + 1
tD

tD
A

E S T
tA

R T /G T

C C

T R T

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T o n e n

T o n e

tG

tP
T o n e C o d e n

D 0 ~ D 3

D O

tP

tG

O V

tP

D V

D V
tD

D O

D V

tE

D O

on

O E

T A

T o n e C o d e n + 1

T o n e C o d e n
tD

T P

tz

Figure 3. Steering timing

T o n e

en

T o n e

em

P W D N

tP
U

Figure 4. Power up timing

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E S T

Rev. 1.11

February 23, 2009

HT9170B/HT9170D
V

D D

D D

V D D

V D D

H T 9 1 7 0 B /D

H T 9 1 7 0 B /D
C

R T /G T
R

R 1

E S T

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E S T

R T /G T
D 1

(a) Fundamental circuit:

tGTP = R C Ln (VDD / (VDD - VTRT))
tGTA = R C Ln (VDD / VTRT)
V

(c) tGTP > tGTA :

tGTP = R1 C Ln (VDD / (VDD - VTRT))
tGTA = (R1 // R2) C Ln (VDD / VTRT)
D D

V D D

H T 9 1 7 0 B /D
C

R T /G T

R 1

E S T

D 1

R 2

R 2

on

(b) tGTP < tGTA :

tGTP = (R1 // R2) C Ln (VDD - VTRT))
tGTA = R1 C Ln (VDD / VTRT)

Figure 5. Steering time adjustment circuits

C O L 3

C O L 4

R O W 1

R O W 2

R O W 3

R O W 4

DTMF data output table

697
697
697

Digit

OE

D3

D2

D1

D0

1209

1336

1477

1209

770

1336

770

1477

852

1209

852

1336

852

1477

941

1336

941

1209

941

1477

697

1633

ww

w.

el

770

High Group (Hz)

em

Low Group (Hz)

770

1633

852

1633

941

1633

ANY

Note: Z High impedance;

Rev. 1.11

en

C O L 1 C O L 2

tz

DTMF dialing matrix

ANY Any digit

7

February 23, 2009

HT9170B/HT9170D
Data output
The data outputs (D0~D3) are tristate outputs. When OE input becomes low, the data outputs (D0~D3) are high impedance.

Application Circuit 1
V
1

1 0 0 k W

D T M F

2
3

0 .1 m F

1 0 0 k W
5

T o o th e r d e v ic e
6
7
8

X 't a l
9
C 2
V S S

C 1

Note:

V P

V D D

V N

R T /G T

G S

E S T

V R E F

D V

IN H

D 3

P W D N

D 2

X 1

D 1

X 2

D 0

V S S

O E

1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0

H T 9 1 7 0 B /D

Xtal = 3.579545MHz crystal

C1 = C2 @ 20pF

0 .1 m F

en
0 .1 m F

R 3 + R 5
=
R 2
R 1 + R 3
R 2 R 4
R 3 = R 2 + R 4

em

R 5

el

E x a m p le : A v
R 1
R 2
R 3
R 4
R 5

Note:

R 1

1 8 0 p F

D T M F

A v =

tz

Application Circuit 2

0 .1 m F

3 0 0 k W

T o o th e r d e v ic e

= 3
= 6
= 1
= 6
= 1
= 3

0 k W
0 0 k W
0 k W
5 0 k W
0 0 k W

R 2

2
3
4

V N

R T /G T

V R E F
5

D V

IN H

T o o th e r d e v ic e
6

P W D N

D 3
D 2

X 't a l
C 2

V D D

G S

R 4

C 1

V P

E S T

R 5

R 3

8
9
V S S

X 1

D 1

X 2

D 0

V S S

O E

1 8

D D

0 .1 m F

1 7
1 6
3 0 0 k W
1 5
1 4
1 3
1 2
1 1

T o o th e r d e v ic e

1 0

H T 9 1 7 0 B /D

Xtal = 3.579545MHz crystal

C1 = C2 @ 20pF
Xtal = 3.58MHz ceramic resonator
C1 = C2 @ 39pF

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w.

D D

on

Xtal = 3.58MHz ceramic resonator

C1 = C2 @ 39pF

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Application Circuits

Rev. 1.11

February 23, 2009

HT9170B/HT9170D
Package Information
18-pin DIP (300mil) Outline Dimensions
A
A
1 8

1 0

1 8

1 0
9

C
D

D
E

E
I

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Fig1. Full Lead Packages

Fig2. 1/2 Lead Packages

MS-001d (see fig1)

Dimensions in mil
Nom.

Max.

880

920

240

115

115

14
45

300

en

F
G

280

195

150

22

70

100

325

430

Dimensions in mil

em

MS-001d (see fig2)

Symbol

on

Min.

tz

Symbol

Min.

Nom.

Max.

845

880

240

280

115

195

115

150

14

22

45

70

100

300

325

430

A
B

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el

Rev. 1.11

February 23, 2009

HT9170B/HT9170D
MO-095a (see fig2)

Dimensions in mil

Symbol

Nom.

Max.

845

885

275

295

120

150

110

150

14

22

45

60

100

300

325

430

ww

w.

el

em

en

tz

on

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Min.

Rev. 1.11

10

February 23, 2009

HT9170B/HT9170D
18-pin SOP (300mil) Outline Dimensions

B
A
9
1

C
C '
G

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1 0

1 8

D
E

MS-013

Dimensions in mil

Symbol

Nom.

Max.

393

419

256

300

12
447

16

en

tz

C
C

on

Min.

20
463

104

50

12

50

13

ww

w.

el

em

Rev. 1.11

11

February 23, 2009

HT9170B/HT9170D
Product Tape and Reel Specifications
Reel Dimensions
D

on

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T 2

T 1

Symbol

Description
Reel Outer Diameter

Reel Inner Diameter

Spindle Hole Diameter

en

tz

SOP 18W

Key Slit Width

Space Between Flange

T2

Reel Thickness

330.01.0
100.01.5
13.0

+0.5/-0.2

2.00.5
24.8

+0.3/-0.2

30.20.2

ww

w.

el

em

D
T1

Dimensions in mm

Rev. 1.11

12

February 23, 2009

HT9170B/HT9170D
Carrier Tape Dimensions

P 0
D

P 1
t

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E
W

B 0

D 1

K 0

A 0

R e e l H o le

IC

p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .

Symbol

on

SOP 18W
Description

Dimensions in mm

Cavity Pitch

Perforation Position

Cavity to Perforation (Width Direction)

11.50.1

Perforation Diameter

1.50.1

D1

Cavity Hole Diameter

P0

Perforation Pitch

P1

Cavity to Perforation (Length Direction)

2.00.1

A0

Cavity Length

10.90.1

B0

Cavity Width

K0

Cavity Depth

en

16.00.1
1.750.1

1.50

+0.25/-0.00

em

4.00.1

12.00.1
2.80.1
0.300.05

Cover Tape Width

21.30.1

el

Carrier Tape Thickness

ww

w.

tz

Carrier Tape Width

24.0

+0.3/-0.1

Rev. 1.11

13

February 23, 2009

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw

on

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)

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HT9170B/HT9170D

tz

Holtek Semiconductor Inc. (Shanghai Sales Office)

G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103
Tel: 86-21-5422-4590
Fax: 86-21-5422-4705
http://www.holtek.com.cn

en

Holtek Semiconductor Inc. (Shenzhen Sales Office)

5F, Unit A, Productivity Building, Gaoxin M 2nd, Middle Zone Of High-Tech Industrial Park, ShenZhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722

em

Holtek Semiconductor Inc. (Beijing Sales Office)

Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125

el

Holtek Semiconductor Inc. (Chengdu Sales Office)

709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 86-28-6653-6590
Fax: 86-28-6653-6591

ww

w.

Holtek Semiconductor (USA), Inc. (North America Sales Office)

46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com

Copyright 2009 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.

Rev. 1.11

14

February 23, 2009