MOS Cap

MOS Equivalent resistor

Ref
1. Weste
2. Baker
3. Kang

MOS Capacitance Models

The MOS gate sits above the channel and may partially overlap the source and drain
diffusion areas. Therefore, the gate capacitance has two components: the intrinsic
capacitance
Cgc : over the channel
Cgovl: overlap capacitances (to the source and drain).
The intrinsic capacitance was approximated as a simple parallel plate with capacitance
Co = WLCox.
However, the bottom plate of the capacitor depends on the mode of operation of the
transistor.

 Cgb (gate-to-body)
Cgs(gate-to-source)
Cgd (gate-to-drain)

overlap capacitances Cgovl (to the source and drain)

Typical values are Cgsovl = Cgdovl = 0.2 0.4 fF/m. They
should be added to the intrinsic gate capacitance to find the
total capacitance.

For the purpose of delay calculation of digital circuits, we

usually approximate
Cg = Cgs + Cgd + Cgb C0 + 2CgovlW
or use an effective capacitance extracted
Taken from reference (may not be applicable at each technology node):
the effective gate capacitance varies with the switching activity of the
source and drain. Figure 2.11 shows the effective gate capacitance in a 0.35 m
process for seven different combinations of source and drain behavior [Bailey98].

MOS Diffusion Capacitance Model

the pn junction between the source diffusion and the body contributes parasitic
capacitance across the depletion region. The capacitance depends on both the area AS
and sidewall perimeter PS of the source diffusion region.
The geometry is illustrated in Figure. The area is AS = WD. The perimeter is PS = 2W +
2D. Of this perimeter, W covers the channel and the remaining W + 2D does not.

The total source parasitic capacitance is

 where Cjbs is the capacitance of the junction between the body

and the bottom of the source and has units of
capacitance/area
Cjbssw (the capacitance of the junction between the body and
the side walls of the source) has units of capacitance/length.

Because the depletion region thickness depends on the bias

conditions, these parasitics are nonlinear. The area junction
capacitance term is

 CJ is the junction capacitance at zero bias and is highly processdependent.

MJ is the junction grading coefficient, typically in the range of
0.5 to 0.33 depending on the abruptness of the diffusion junction.
is the built-in potential that depends on doping levels.

vT is the thermal voltage. It has a value equal to kT/q (26 mV at

room temperature), where k = 1.380 1023 J/K is Boltzmanns
constant, T is absolute temperature (300 K at room temperature),
and q = 1.602 1019 C is the charge of an electron.
NA and ND are the doping levels of the body and source diffusion
region. ni is the intrinsic carrier concentration in undoped silicon
and has a value of 1.45 1010 cm3 at 300 K.

In processes below about 0.35 m that employ shallow trench isolation surrounding
transistors with an SiO2 insulator the sidewall capacitance along the nonconductive
trench tends to be minimal, while the sidewall facing the channel is more
significant. In some SPICE models, the capacitance of this sidewall abutting the gate
and channel is specified with another set of parameters:

The drain diffusion has a similar parasitic capacitance dependent on AD, PD, and
Vdb. Equivalent relationships hold for pMOS transistors, but doping levels differ.
As the capacitances are voltage-dependent, the most useful information to digital
designers is the value averaged across a switching transition.

Example
Calculate the diffusion parasitic Cdb of the drain of a unit-sized contacted NMOS
transistor in a 65 nm process when the drain is at 0 V and again at VDD = 1.0 V.
Assume the substrate is grounded. The transistor characteristics are CJ = 1.2 fF/m2,
MJ = 0.33, CJSW = 0.1 fF/m, CJSWG = 0.36 fF/m, MJSW = MJSWG = 0.10, and
= 0.7 V at room temperature.
The area is 0.0125 m2 and perimeter is 0.35 m plus 0.1 m along the channel.

 Effective switching resistance of MOSFET

Point A in Fig. shows the operating point of the MOSFET prior to switching for
VDD = 5 V. After switching takes place, the operating point moves to point B
and follows the curve Vgs = VDD down to ID = 0 and VDS = 0, point C. At this
point, the NMOS switch is on.

 For an NMOS device with a specific width, W, or length, L, we can estimate

the effective switching resistance of the device in the long-channel CMOS
process (scale factor of 1 m) as

For the PMOS device, the transconductance parameter, KP, is three times
smaller than the NMOS's KP so we can write

 The effective resistance of the PMOS device is

three times as large as the NMOS's due to the
mobility of the electrons being larger than the
mobility of the holes.

Assignment 2_P2: Estimate the switching

resistance of NMOS and PMOS at 180 nm
node. Express the resistance in terms of scale
factor.

Scale Factor
we do layout to a generic scale factor. If, for example, the
minimum device dimensions are 50 nm (= 0.05 m =50 x 109m), then an n-well box drawn 10 by 10, see Fig, has an actual
size after it is fabricated of 10* 50 nm or half a micron (0.5 um
= 500 nm),

 Short-Channel MOSFET Effective Switching Resistance

scale factor of 50 nm and a VDD of 1 V.

Knowing, for the short-channel process, that the scale

factor is 50 nm, we can rewrite Eqs.

where W is the drawn width of the devices. Practically, to model the effects of
increasing switching resistance when L is greater than 1 (minimum), we can re-write Eq