Beruflich Dokumente
Kultur Dokumente
DMA
Memory
AHB
Parallel
APB bus
Bridge
APB
UART
UART
Serial UART
protocol
5
UART
Serial
APB
Core
USB
Ethernet
UVM Testbench
Scoreboard
Imitates external
device by
generating frames
Programs the
UART and
transfers traffic
APB
Tx FIFO
txd
Transmitter
APB
Interface
Mode
Switch
Rx FIFO
Receiver
Control/Status
Registers
UART
Serial
rxd
UART
Verification
Component
Control/Interrupt
Logic
Multi-channel controller
Test 2
Test 3
What is UVM?
UVM is the Universal Verification Methodology
A methodology and a library that codifies the best practices for
efficient and exhaustive verification.
A complete, proven solution
Proven solution, with a success record and large community of users
with methodology knowledge and commitment
Well-thought-out solution for a wide variety of verification challenges
Open
A key motivation for moving to SystemVerilog
An Accellera standard, supported by Cadence, Mentor and Synopsys
Jan
2006URM
2008 OVM
eVC
OVC
UVC
Configuration
DUT I/F
Configuration
DUT I/F
Configuration
DUT I/F
Passive Agent
Active Agent
Passive Agent
Active Agent
Passive Agent
Active Agent
Monitor
Sequence_driver
Monitor
BFM
Coverage
Checks
Architecture
Sequences
Messaging/logging
Reset/clocking
Common test interface
Packaging & code structure
SystemVerilog support
Architecture
Sequences
Factory
Configuration mechanism
Field automation
Message macros
Register pkg (contribution)
Integration of AVM base classes
TLM Communication Channel
Multi-language interoperability
OVM 2.1.1
Added:
Coverage
Driver
Included:
Sequencer
Seqs.
Checks
Added:
Monitor
Seqs.
Seqs.
Checks
Coverage
Sequencer
Driver
Added:
SV callback enhancements
Report catching callback
SV end of test enhancements
Closer to eRM capability
Register support
Enhanced phasing
Partial TLM2 support
Improved configuration and
command line support
Script for o to u migration for
OVM users
Why CDV?
Eliminate the effort and time to write hundreds of tests
Ensure thorough verification using upfront goal setting
Coverage
seed
23098432
38748932
23432239
17821961
10932893
20395483
18902904
23843298
23432432
24324322
55252255
09273822
13814791
4098e092
23432424
24242355
25262622
26452454
24524522
11
Monitor
Monitor
Random
Generation
Tests
Tests
Random
Stimulus
Sequence
Generator
Generator
Driver
DUT
UART
APB
Assertions,
Constraints
& Coverage
Simulation,
Acceleration,
Emulation
Refine Coverage
Model
Review Coverage
12
A1 A2 A3 A4
Features
B1 B2 B3 B4
C1 C2 C3 C4
D1 D2 D3 D4
Specification Blocks
Functional coverage
Assertions (Static Formal Verification and Simulation)
Directed tests
Code coverage
Assertions: 31%
We recommend:
Start with explicit coverage to represent
verification goals: Static and dynamic
assertions and functional coverage
Coverage
full
partial
none
Total Coverage: 68%
Advantages:
Saves test writing efforts
Reliable metrics to check your progress throughout the
verification cycle
Ensures efficient verification
Eventually determines completeness
15
Agenda
16
Structural Elements
Methodology
name
copy(),
clone()
print()
uvm_transaction
uvm_sequence_item
uvm_sequence
uvm_report_object
body()
uvm_report_*()
uvm_port_base #(IF)
uvm_report_handler
uvm_component
uvm_subscriber
uvm_env
uvm_*_export
parent
children
get/set_config_*(), create ()
build_phase(),
connect_phase(),
end_of_elaboration_phase();
start_of_simulation_phase();
run_phase(),
uvm_tlm_fifo
uvm_tlm_analysis_fifo
uvm_test
uvm_driver
uvm_monitor
uvm_agent
uvm_scoreboard
18
uvm_*_port
TLM
uvm_*_imp
uvm_tlm_req_rsp_channel
uvm_tlm_transport_channel
uvm_sequencer
19
Option 2
20
uvm/sv/cdns_additions
uvm/examples/
simple/
integ/
xbus/
examples/
sv/
codec/
apb/
22
Agenda
Data items
Represent the main transaction input to the DUT
Adhering to a protocol, consistent values are generated and sent
Examples include packets, transactions, instructions, and so on
UVM
Smart Testbench
24
Fields to be randomized
// utility functions
parity is calculated using a function
extern function bit calc_parity( );
extern function void print( );
extern function bit compare(uart_frame rhs);
endclass: uart_frame
25
endclass: uart_frame
26
Recommendation: Think of the desired scenarios and make sure you have the
needed control knobs to achieve them
endclass: uart_frame
27
class uart_frame;
endclass
New class
members
28
endclass
Use of inheritance
// Test code
class short_delay_frame extends uart_frame;
// This constraint further constrains the delay values
constraint test1_delay {delay < 10;}
endclass: short_delay_frame
29
Produces data
(transactions)
i/f
i/f
Bus Driver
Gets data and
sends to DUT
interface
DUT
30
Randomize in a loop a
transaction or create an
array of transactions to
send one-by-one
class simple_generator;
rand int count;
uart_frame frame;
task gen_and_push();
frame = new();
for (int i=0; i<count; i++) begin
assert(frame.randomize());
driver.send_tx_frame(frame);
end
endtask
endclass: simple_generator
class driver;
virtual interface dut_if if;
task send_tx_frame(input uart_frame frame);
. . . // implements protocol-specific code
if.txd = frame.start_bit; .
endtask
endclass
Gets a frame and drives it
// Utility functions
extern function bit calc_parity( );
extern function void print();
extern function bit compare(uart_frame rhs);
endclass: uart_frame
31
Cloning
Comparing
Copying
Packing
Transaction Recording
32
uart_frame fields
UVM_NOCOMPARE,
UVM_NOPRINT, etc.
`uvm_object_utils_begin (name)
`uvm_field_int (name, FLAGS)
`uvm_field_enum(etype, name, FLAGS)
`uvm_field_array_int (name, FLAGS)
`uvm_object_utils_end
--------------------------------------Name
Type
Size
Value
--------------------------------------my_frame
uart_frame @607
start_bit
integral
1
h1
payload
integral
8
hfc
parity
integral
1
h0
parity_type parity_e
32 BAD_PARITY
delay integral
32 d382
---------------------------------------
SimVision: Automatic
transaction recording.
36
37
FLAG
DESCRIPTION
DEFAULT
UVM_ALL_ON /
UVM_DEFAULT
UVM_DEFAULT
UVM_COPY /
UVM_NOCOPY
UVM_COPY
UVM_COMPARE/
UVM_NOCOMPARE
UVM_COMPARE
UVM_PRINT /
UVM_NOPRINT
UVM_PRINT
UVM_PACK/
UVM_NOPACK
UVM_PACK
UVM_PHYSICAL /
UVM_ABSTRACT
UVM_READONLY
Radix
(for printing)
ADD UVM_ to each
radix listed
UVM_HEX
Messages
Error reporting
The testbench must produce clear and descriptive error messages to
communicate a checker mismatch
Should affect simulation based on severity
Error stop
Warning record and proceed
Allow customization of above
38
Message Requirements
Simplicity of
Writing messages
Turning messages on and off
Uniformity of
Output format
Turning on and off
39
Output
id
time
message body
scope
Simple Messaging:
uvm_report_*(string id, string message);
% irun . +UVM_VERBOSITY=UVM_NONE
41
Objectives:
Transaction generation
and constraint layering
UVM automation
Use UVM message
facility
UVM
Testbench
Scoreboard
coverage
APB
UVC
UART
DUT
Multi-channel
controller
UART
UVC
Questions
What advantages do you see in using `uvm_info() over $display?
When we introduced a test1_frame, we had to modify the
frame_generator to create test1_frames
Can you think of a scenario in which this would be problematic?
Can you send a stream of transactions with incrementing
payload values using constraint layering?
46
48
Replace frame=new();
with create ()
delay_frame
to
uart_frame
...
delay_frame
...
Factory
Class Hierarchy
uart_frame
Create uart_frame
Factory allocates instance
of required type
from
+create
registered types
uart_frame
delay_frame
delay_frame
+create
Factory Overrides
Type override replaces ALL instances: For a specific test, replace all uart_frame
packets with delay_frame packets
A uart_frame
drv_c
B delay_frame
drv1_c
set_type_override_by_type(uart_frame::get_type(),
env1
delay_frame::get_type());
agent[0]
agent[1]
seqr
A
B
seqr
A
B
driver monitor
A
B
A
B
driver monitor
B
A
A
B
env1
agent[0]
agent[1]
seqr
A
B
seqr
A
set_inst_override_by_type("env1.agent[1]",
drv_c::get_type(), drv1_c::get_type());
driver monitor
A
A
driver monitor
A
A
A
uart_frame
new_frame
Example:
uart_frame::type_id::set_type_override
(delay_frame::get_type());
Example:
uart_frame::type_id::set_inst_override
(delay_frame::get_type(), A.B);
51
task gen_and_push();
// replace frame = new(); with the following:
module lab1_top;
frame = uart_frame::type_id::create(frame);
frame_generator generator;
endclass : frame_generator
initial begin
uart_frame::type_id::set_type_override (test1_frame::get_type());
generator = new();
endmodule : lab1_top
52
Agenda
Generator
Produces data
i/f
i/f
Bus Driver
Consumes and
send to DUT
54
class generator;
Randomize in a loop a
rand int count;
transaction or create an
uart_frame frame;
array of transactions
virtual task gen_and_push();
for (int i=0; i<count; i++) begin
frame = new();
assert(frame.randomize());
// send frame to bus driver interface
end
endtask
endclass: generator
Issues with generators:
Limited control
Not easy to define ordered transactions
Can not define timing without code override
Unable to react to the state of the DUT
Generator is not reusable at system-level
Does not support multi-channel control
55
Sequencer
Generator
Produces data
i/f
UVM sequencer
By default works exactly like a generator
Generates random transactions on request
We replace the generator
Addresses all randomization requirements:
with a sequencer
random by-default, reactive generation,
system-level ready, modeling timing, etc
sequences
i/f
Bus Driver
Consumes and
send to DUT
57
Translates into:
endtask : body
endclass
60
Nesting Sequences
// call retry sequence wrapped with random frames
class rand_retry_seq extends uvm_sequence #(uart_frame);
`uvm_object_utils(rand_retry_seq)
retry_seq retry_sequence;
Using a previously
defined sequence
61
Sequence Execution
Sequencer
// Sequence: rand_retry_seq
class rand_retry_seq extends
//uart_frame req; //built into seq
retry_seq retry;
virtual task body ();
`uvm_do(req)
`uvm_do_with(retry, {pload
inside {[0:31]};))
`uvm_do(req)
endtask
endclass
// Sequence: retry_seq
class retry_seq extends uvm_sequence #();
// uart_frame req; // built into base seq
rand bit[7:0] pload;
virtual task body ();
`uvm_do_with(req, {payload ==pload;
parity==BAD_PARITY;})
`uvm_do_with(req,{payload==pload;
parity==GOOD_PARITY;})
endtask
endclass
get_next_item()
get_next_item()
item_done()
Driver
62
63
2.
3.
Produces data
`uvm_component_utils(uart_tx_driver)
i/f
i/f
Driver
Consumes and
send to DUT
64
Interface to the
sequencer via TLM
66
Multi-channel sequences
Pre-run sequences (zero-time-generation)
Reactive sequences
Interrupt sequences
Protocol layering
And more
67
Design Browser
68
Methods Tab
69
70
// APB sequences
program_dut_csr_seq config_dut;
apb_to_uart_wr raw_seq;
// UART sequences
uart_transmit_seq uart_seq;
intrpt_seq rd_rx_fifo;
virtual task body();
endtask
endclass
`uvm_sequence_utils(do_something_seq,apb_uart_virtual_sequencer )
task body();
uvm_report_info("do_something_seq","Doing Nothing First", UVM_NONE);
#2000
uvm_report_info("do_something_seq",
"Doing concurrent_u2a_a2u_rand_trans sequence NOW", UVM_NONE);
`uvm_do(my_vseq);
endtask
endclass
71
72
Constraint Debugger
73
Constraint Debug
This portion
lists the
variables and
their values. All
variables are
listed in the
object since
state variables
can be used in a
constraint.
75
coverage
UVM Sequences:
Objectives:
Explore the driver and
sequencer interaction
Review the sequencer
default behavior
Execute a specific
sequence
Write a new sequence
APB
UVC
UART
DUT
UART
UVC
Multi-channel
controller
uart_tx
sequencer
sequence
seq_item_export
seq_item_port
uart_tx
driver
76
Scoreboard
Sequencer:
Creates and executes sequences of
transactions
Sends UART frames to the Driver
Sequence :
Creates randomized UART frames
Driver :
Gets UART frames from the Sequencer
Converts to signal-level details ( it just
prints the frame in this lab)
Indicates its ready for another frame
77
sequences
sequencer
Default_sequence
seq_item_export
uart frames
seq_item_port
driver
virtual i/f
uart signals
interface
UART DUT
simple_tx_seq
transmit_seq
repeat_seq
incr_payload
bad_parity
sequence_items
BAD_PARITY
GOOD_PARITY
uart_frames
Questions
What benefits do sequences provide?
What is the sequence body() task?
How to control a sequencer execution?
78
Agenda
Reusable Environments
80
BUS UVC
Mon
Mon
Module VC
BFM
BFM
SEQR
Scoreboard
Mon
coverage
DRV
VC3
Project1 DUT
Multi Channel Sequence Generator
CPU
Periph
Mon
Mon
Mon
BFM
BFM
DRV
SEQR
Protocol1
VC3 UVC
81
Mem
Periph
Mon
Mon
Mon
BFM
BFM
DRV
SEQR
VC3 UVC
Protocol2
Tasks to be done:
Issues:
How do we model complex environments?
Generation? Checking? Coverage?
How do we facilitate reuse?
Coverage
Scoreboard
Data Checking
Coverage
Monitor
Monitor
seed
23098432
38748932
23432239
17821961
10932893
20395483
18902904
23843298
23432432
24324322
55252255
09273822
82
Tests
Tests
Sequencer
Driver
DUT
UART
APB
Coverage
Scoreboard
Checking
Coverage
Passive
Coverage
Monitor
Random
AHB
to APB
Tests
Tests
Sequence
Bridge
Generator
Driver
Reusable Component
83
Monitor
DUT
APB
UART
84
Facilitating Reuse
Testbench
Mon
BFM
Mon
BFM
Mon DRV
SEQR
VC3
VC2
Multi Channel Sequence Generator
Project2 DUT
Periph
Periph
VC Repository
Mon
BFM
Mon
BFM
Mon DRV
Module VC
Mon
BFM
Mon
BFM
Mon DRV
Scoreboard
Mon
BFM
Mon
BFM
Mon DRV
BUS
VC
Mon
BFM
Mon
BFM
SEQR
SEQR
SEQR
SEQR
Mon DRV
SEQR
coverage
VC3
85
Mon
BFM
Mon
BFM
Mon BFM
VC3
VC3
eVC
VC3
VC2
VC3
Sequencer
Produces data
i/f
i/f
Driver
Consumes and
send to DUT
87
The Monitor
Monitor
A passive component that collects information on a monitored
interface
Builds abstract transactions
Contains events, status, checkers and coverage
Protocol specific
Passive entity
Monitor
88
Checking and
coverage
covergroup uart_trans_frame_cg;
NUM_STOP_BITS : coverpoint frame.nbstop {
bins ONE = {0};
Implement coverage
bins TWO = {1};
model based on your
}
verification plan
DATA_LENGTH : coverpoint frame.char_length { }
PARITY_MODE : coverpoint frame.parity_mode { }
endgroup
function new (string name = "", uvm_component parent = null);
super.new(name, parent);
new() covergroup in the constructor
uart_trans_frame_cg = new();
endfunction: new
Task to collect data items
task collect_frame ( );
// Collect uart data from interface
from the DUT interface
uart_trans_frame_cg.sample();
endtask: collect_frame
Sample coverage when
endclass: uart_monitor
frame is collected
89
Env
(UVC)
Immediate assertion
Agent
checks in the monitor
Agent
Agent
Config:
active_passive
91
sequences
tlm i/f
tlm i/f
Monitor
tlm i/f
Coverage
Checking
Driver
vif
vif
Concurrent assertions
reside in the SV interface
Ask us for information or T=training
on UVM and Assertions
Sequencer
I/F
DUT
Agenda
93
SDRAM
Bank 0
SDRAM
Bank 2
SDRAM
Bank 1
SDRAM
Bank 3
SRAM
ROM
Flash
LCD Display
PC Cards
ETM
MOVE
Static
Memory
Interface
SDRAM
Controller
ARM926
CPU
Vectored
Interrupt
Control
Color
LCD
DMA
M
PCMCIA
Host
ARM I AHB
ARM D AHB
LCD AHB
SRAM
Buffer
DMA APB
Core APB
WATCHDOG
AHB/
APB
TIMERS
AHB/
APB
MPEG-4
Engine
Colour
Convert
SSP
Camera
Interface
Camera
GPIO (x4)
GPIO
x4
SYSTEM
CONTROL
RTC
Clk/Reset
Generator
32 GPIO
lines
32KHz
CLK
Xtal Osc
UART
SIM Card
USB
Interface
Transceiver
PLL
Xtal Osc
USB Connection
to PC
94
Camera
Control
Our new
system
specs are
in the mail
Config:
sequences
seq_item_export
uvm_monitor
events,
status,
data
uvm_driver
vif
vif
interface
DUT
95
uvm_agent
uvm_
sequencer
Config:
is_active:
UVM_PASSIVE
UVM_ACTIVE
min_addr:
16h0100
sequences
seq_item_export
UVM_ACTIVE:
Actively drive an interface or device
Driver, Sequencer and Monitor are
allocated
passive
uvm_monitor
events,
status,
data
seq_item_port
uvm_driver
vi
vi
interface
DUT
96
UVM_PASSIVE:
Only the Monitor is allocated
Still able to do checking and collect
coverage
Configuration field
class master_agent extends uvm_agent;
uvm_active_passive_enum is_active = UVM_ACTIVE;
UVM field declaration for
library automation
`uvm_component_utils_begin(master_agent)
`uvm_field_enum(uvm_active_passive_enum, is_active, UVM_ALL_ON)
`uvm_component_utils_end
// agent sub component instances
Using the constructor to allocate the
master_driver
driver;
sub-instances is problematic
master_sequencer sequencer;
because new() is not polymorphic
master_monitor
monitor;
function new( input string name, input uvm_component parent);
agent
super.new( name, parent);
sequencer
// create the sequencer, driver and monitor
Config:
Is_active
sequences
monitor = new (monitor,this);
if (is_active == UVM_ACTIVE) begin
driver = new(driver,this);
monitor
events,
sequencer = new(sequencer, this);
status,
driver
end
data
Allocation using new() forces a
vi
vi
endfunction
re-write when modifications are
endclass
required
97
99
Verification Environments
Many protocols have a variable number of devices
Example: AHB has multiple masters and slaves
100
slave agent
slave agent
monitor
monitor
monitor
Config:
Config:
i/f
events,
events,
status,
events,driver
status,
driver
data
status,
driver
data
data
vi
vi
vi
vi
vi
vi
101
monitor
monitor
events,
events,
status,
status,
data
data
vi
vi
i/f
i/f
driver
driver
vi
vi
interface
Envs allow reuse at the interface
level!
DUT
num_masters=3
num_slaves=2
Virtual
interface
seq
i/f vi
i/f
vi
i/f
Sometimes common
sequencer
for all agents
Config:
seq
seq
i/f
i/f
arbiter agent
sequencer
sequencer
seq
seq
vi
i/f seq
i/f
Config:
i/f
monitor
monitor
i/f
events,
status,
data
vi
driver
events,
status,
data
vi
vi
build_phase
connect_phase
end_of_elaboration_phase
start_of_simulation_phase
run_phase
UVC1
DUT
UVC2
extract_phase
check_phase
report_phase
UVC3
103
build
build_phase
connect_phase
connect
end
of elaboration_phase
end
of elaboration Post-elaboration activity (e.g. print topology)
start_of_simulation_phase
start_of_simulation Configure verification components
104
run
run_phase
extract_phase
extract
check
check_phase
report
report_phase
pre-reset
reset
connect_phase
end of elaboration_phase
start of simulation_phase
post-reset
pre-configure
configure
post-configure
run_phase
pre-main
extract_phase
Allow components to
perform operations
related to reset
main
post-main
Perform operations
related to device
configuration (register
settings and more)
Defines the normal
operation of the
component for the
bulk of the test
check_phase
report_phase
finalize
105
pre-shutdown
shutdown
post-shutdown
Scoreboard
coverage
Reusable Environment
Topology:
UART
DUT
APB
UVC
Objectives:
Review the UVM
Verification Component
architecture: sequencer,
driver, monitor, agent, env
Understand how to make
an agent PASSIVE
Multi-channel
controller
UART UVC
tx_agent
Config:
Is_active
rx_agent
sequencer
sequenc
es i/f
monitor
events,
data
coverage
vi
106
UART
UVC
i/f
driver
vi
Config:
Is_active
sequencer
sequenc
es i/f
monitor
events,
data
coverage
vi
i/f
driver
vi
107
Agenda
Test Requirements
109
Mon
BFM
SEQR
Module VC
Scoreboard
Mon
DRV
VC3
coverage
Multi Channel Sequence Generator
CPU
Mem
Periph
Periph
Mon
BFM
Mon
BFM
Mon DRV
UVC1
VC3
Disadvantages
DUT
SEQR
110
BUS
Mon UVC
BFM
Mon
BFM
Mon
BFM
Mon DRV
SEQR
UVC
VC32
module top ( );
class test();
BUS
Mon UVC
BFM
Mon
SEQR
Module VC
Scoreboard
Mon
DRV
VC3
coverage
Multi Channel Sequence Generator
DUT
CPU
Mem
Periph
Periph
Mon
BFM
Mon
BFM
Mon DRV
SEQR
UVC1
VC3
111
BFM
Mon
BFM
Mon
BFM
Mon DRV
SEQR
UVC
VC32
Advantages
Allows reuse through inheritance
Can instantiate and modify
Can compile many tests and
elaborate once
Allows multi-language testbenches
Disadvantages
Test writer still needs to know how
to instantiate the verification env
Config change requires modifying
many tests
SEQR
Scoreboard
Mon
coverage
Multi Channel Sequence Generator
DUT
CPU
Mem
Periph
Periph
Mon
BFM
Mon
BFM
Mon DRV
SEQR
UVC1
VC3
112
DRV
VC3
Mon
BFM
Mon
BFM
Mon DRV
SEQR
UVC
VC32
Benefits
Tests are shorter, and descriptive
Less knowledge to create a test
Easier to maintain changes are done
in a central location
tb
Test1
Test2
- Use only
legal frames
Test3
Use zero frame
delay
- Do not Have
sendTest4
out-of-order
4 masters
Back-to-back
short
Send long
frame streams
frames frames
Change the clock speed
Send many illegal frames
113
If config needs to be
changed, no need to
visit all tests
env
tb
env
env
env
env
env
env
env
endtask
Multiple tests
module top
`include . // uvm lib, test, and components
IF
IF
IF
DUT
initial begin
run_test(test1);
end
rst
clks
endmodule : top
DUT snapshot
the entire
together
and use
Allows execution Compile
of multiple
teststest
on suite
the same
snapshot
command-line option to select a test:
% irun f run.f +UVM_TESTNAME=test3
114
Testbench Example
class uart_ctrl_tb extends uvm_env;
`uvm_component_utils(uart_ctrl_tb)
Extends from uvm_env
apb_env apb0; // APB UVC
uart_env uart0; // UART UVC
uart_ctrl_env uart_ctrl0; // Module UVC
Multi-Channel Sequences
117
Multi-Channel Sequences
uart_ctrl_env
virtual_sequencer
config_dut
u2a_incr_payload
uart_incr_seq
p_apb_seqr
p_uart_seqr
apb_rd_rx_fifo
uart_env
apb_env
apb_agent
uart_agent
uart_sequencer
apb_sequencer
seq
config_dut
uart_incr_seq
seq
rd_rx_fifo
Driver
118
Driver
Determining End-of-Test
Virtual Sequencer
coordinates traffic on
UVC1 and UVC2
virtual
sequences
Virtual
Sequencer
sequences
vseq2
UVC2
seqr
DUT
mon agent
sequences
ovc2_seq1
drvr seqr
drvr
How do we decide
when to end a test?
119
...
fork
`uvm_do_on(ovc2_seq1, ovc2)
`uvm_do_on(ovc1_seq3, ovc1)
Join
...
UVC1
agent mon
ovc1_seq3
UVC3
sequences
ovc3_seq1
agent mon
seqr
drvr
Ending Simulation
raise
drop
drain time
sequence
start
stop
called
stop
executed
120
120
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Drain Time
When all raised objections are dropped, simulation is stopped
A drain time allows propagation of outstanding items (e.g., DUT
response)
If no drain time is set, the test will stop immediately
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123
Objection Debug
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UVM
Testbench
Scoreboard
coverage
APB
UVC
UART
DUT
UART
UVC
Objectives:
Multi-channel
Examine test creation and
Controller
control using the UART tb
Examine an existing test and observe how it instantiates an
environment
Control environment behavior from the test
Show how to control test execution and execute multiple tests
without recompiling/re-elaborating the design
125
Scoreboard
Interface & white-box
coverage
APB
Verification
Component
txd
Transmitter
APB
Interface
Mode
Switch
Rx FIFO
Receiver
Control/Status
Registers
Control/Interrupt
Logic
Virtual Sequencer
(Multi-channel controller)
126
Test 1
Test 2
Test 3
rxd
UART
Verification
Component
Agenda
128
129
130
IVB - Summary
131
Agenda
Assertions: 31%
How do combine
the massive
regression
Remember
this slide?
results into a readable report?
Can all members of the team participate
and analyze the report?
133
partial
none
Total Coverage: 68%
Yes
Done
No
Plan
Signoff?
Enterprise Planner
metric-based plan
Successful Milestone
Missed Milestone
Measure
and analyze
VE Start
Module
Set One
Module
Set Two
UVM
VIP
portfolio
Chip
Integration
Prototype
Construct
Production
Metric
definitions
Failure and
metric analysis
Execute
coverage
checks
assertions
reuse
With a vPlan
135
Functional
and Design
Specs
Enterprise Planner
Spec
Annotator
Verification
Plan
Editor
Functional Coverage
mapping/building
HTML/RTF
136
vPlan
Export
System
vPlan
Test
Pass/Fail
metrics
Functional Specs
Specification
of features
Other vPlans
Coverage
1.1.1.1.4 Cross Length Parity Type
metrics
4 of 20
Project Team
Brainstorming
137
Other
contributing
vPlans
Done!
Plan
Verification
Plan
Yes
Verification
Closure?
Optimized Process
Automation Engine
No
Enterprise Manager
Sessions
React
Status
Test_name
# iterations
Cmd line args
Seed
Failure
Analysis
Progress
Analysis
Execute
Verification Environment
DUT
Measure
138
Specman Elite
Specman
Elite
+
+
Simulation
Incisive
Simulator
Simulation
139
Agenda
Introduction to UVM and Coverage Driven Verification
UVM Class-based Workshop:
The UVM Library
Stimulus Generation
Building Reusable Verification Components
Testbench Creation Using Reusable Components
Coverage Analysis and Regression
UVM Multi-Language and UVM Acceleration
Migration to UVM
Summary
140
AOP
VM
SystemC
System
Verilog
SV
SysC
Methodology includes TLM
communication between implementations
Cadence Confidential
VM
UVM
e
UVC
SV
UVC
UVC
SoC
SC
UVC
SC
UVC
C/C++
VIP
SV
VIP
Cadence provides
Hardware Accelerator
Simulator
SoftwareSoftware
Simulator
Agent
Agent
Sequencer
Sequencer
Monitor
Monitor
events,
Coverage
status,
Checking
data
sequences
sequences
Collector
Collector
UVM ACCEL mode
Driver
Driver
UVM ACCEL mode
VIF
SCE-MI
PROXY
VIF
SCE-MI
PROXY
I/F
(collector_bfm)
I/F
I/F
(driver_bfm)
DUT
DUT
143
Support SV and e
Enables verification re-use
between simulation and
acceleration
put
Transaction
goes in!
get
SCE-MI PIPE
PROXY
Byte-stream
comes out!
DUT
144
SCE-MI pipe
Simulator
Transactions
SCE-MI pipe C
interface
Host
Workstation
145
SCE-MI
2.0
Interface
Sce-mi modules
(RTL)
UVM
Pipes Proxy
Driver
(HVL)
UVM
Testbench
Accelerator
Clock
DUT
BFM
(HDL)
signal-level
interface
Cadence
PdXP
Tests
Architecture Verification
Verification
TLM Generic
payload
Simulation/formal
Verification
3
Micro-Architecture Verification
TLM Non-GP
Simulation
Environment
Verification
RTL
Simulation
3
Verification
vPlan
HW
Accel
Environment
Unified
Metrics
Environment
Coverage
&
Checking
Environment
Agenda
Introduction to UVM and Coverage Driven Verification
UVM Class-based Workshop:
The UVM Library
Stimulus Generation
Building Reusable Verification Components
Testbench Creation Using Reusable Components
Coverage Analysis and Regression
UVM Multi-Language and UVM Acceleration
Migration to UVM
Summary
147
148
Module UVM VC
Reg Model
Scoreboard
Sys_monitor
Input UVM VC
Channel UVM VC
sequencer
Agent
agent0
monitor
driver
DUT
Virtual
Sequence
agent1
VMM VIP
Gen
Driver
Monitor
agent2
150
151
Agenda
152
153
Beyond UVM
Inside the Incisive Platform
Unique Metrics Driven Methodology around UVM
Scalable register & memory modeling package
reg_mem downloadable from uvmworld.org/contributions.php
Useful Websites
UVM World Website:
http://uvmworld.org
Download latest version of UVM library, join the Community Forum to share
ideas and have discussions with other UVM users
155
Learning more
A Practical Guide to Adapting the Universal
Verification Methodology (UVM), by Sharon
Rosenberg and Kathleen A Meade
156
Thank You!
157