Chapter Seven

Programmable Logic Devices

1. Programmable Logic Devices(PLD):
Each PLD contains hundreds of different logic gates as well as some sequential logic
devices and circuits. The PLD is programmed by the user to get the required logic circuit.
PLDs are used for complex logic designs. Using PLDS in logic design gives the
following advantages:
1. Many logic circuits can be obtained using one PLD.
2. Designs can be changed without rewiring or replacing components.
3. PLD design can be implemented faster.
2. Major Types of PLDs:
a. SPLD ( Simple Programmable Logic Device).
Some categories of SPLD are:
-

PAL ( Programmable Array Logic).

PLA ( Programmable Logic Array).

GAL ( Generic Array Logic).

PROM ( Programmable Read-Only Memory).

b. CPLD ( Complex Programmable Logic Device).

c. FPGA ( Field-Programmable Gate Array).
3. Architecture of SPLD:
SPLD is the most basic and least expensive type of PLDs. Each SPLD contains several
logic gates and programmable interconnection points and may also have some flip-flops.
The most common categories of SPLD are PAL, PLA, GAL & PROM.
A PAL contains a set of NOT, AND and OR gates all interconnected with programmable
fusible links. The basic structure for a PAL with two input variables and one output is
shown below:

In a PAL the AND array is programmable, while the OR array is fixed.

Each fusible link between a row and a column is called a cell. This structure allows
any SOP logic expression to be implemented.
Ex: To implement the logical equation

F= AB + AB + AB using the PAL shown above,

we can use programming to open the fusible links where a variable or its complement are
not used in a given product term. The final output of the OR will be the given SOP
equation.

In a PLA both the AND and OR arrays are programmable. The following shows the basic
structure for a PLA with two input variables and two output variables. The PLA is
programmed to implement the logical equations F1= AB + AB + AB and F2= AB + AB
.

In a PROM the AND array is fixed and the OR array is programmable. The following
shows the basic structure for a PROM with two input variables and two output variables.
The PROM is programmed to implement the logical equations F1= AB + AB and
AB +AB+ AB

F2=

5. PLD Design:
Two methods are used to implement the logic circuits using PLDs:
1. Using the computer software CAD ( Computer Aided Design) to draw the circuit
then implement it.
2. Using a programming language called Hardware Description Language ( HDL).
The inputs, outputs and logic processes are defined in a program written using this
language. Then this program is compiled and used to program the PLD.