Less MMMC

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All rights reserved.
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* or any attempt to obtain a human-readable version of this
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* Cadence Design Systems, Inc., is strictly prohibited.
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@(#)CDS: Encounter v14.28-s033_1 (64bit) 03/21/2016 13:34 (Linux 2.6.18194.el5)
@(#)CDS: NanoRoute v14.28-s005 NR160313-1959/14_28-UB (database version

2.30, 267.6.1) {superthreading v1.25}
@(#)CDS: CeltIC v14.28-s006_1 (64bit) 03/08/2016 00:08:23 (Linux 2.6.18194.el5)
@(#)CDS: AAE 14.28-s002 (64bit) 03/21/2016 (Linux 2.6.18-194.el5)
@(#)CDS: CTE 14.28-s007_1 (64bit) Mar 7 2016 23:11:05 (Linux 2.6.18-194.el5)
@(#)CDS: CPE v14.28-s006
@(#)CDS: IQRC/TQRC 14.2.2-s217 (64bit) Wed Apr 15 23:10:24 PDT 2015 (Linux
2.6.18-194.el5)
@(#)CDS: OA 22.50-p011 Tue Nov 11 03:24:55 2014
@(#)CDS: SGN 10.10-p124 (19-Aug-2014) (64 bit executable)
@(#)CDS: RCDB 11.5
--- Starting "Encounter v14.28-s033_1" on Sun Apr 3 19:32:21 2016
(mem=99.0M) ----- Running on SRV01 (x86_64 w/Linux 2.6.18-308.el5) --This version was compiled on Mon Mar 21 13:34:48 PDT 2016.
Set DBUPerIGU to 1000.
Set net toggle Scale Factor to 1.00
Set Shrink Factor to 1.00000
**INFO: MMMC transition support version v31-84
<CMD> set_global _enable_mmmc_by_default_flow

<CMD> suppressMessage ENCEXT-2799
<CMD> win
<CMD> set conf_ioOri R0
<CMD> set conf_qxconf_file NULL
<CMD> set conf_qxlib_file NULL
<CMD> set dcgHonorSignalNetNDR 1
<CMD> set defHierChar /
$CTE::mmmc_default
<CMD> set delaycal_input_transition_delay 0.1ps

Set Input Pin Transition Delay as 0.1 ps.
<CMD> set distributed_client_message_echo 1
<CMD> set fpAllowShifterIn3rdPD 1
<CMD> set fpIsMaxIoHeight 0
<CMD> set fp_core_height 147.060000
<CMD> set fp_core_width 148.685000
<CMD> set gpsPrivate::dpgNewAddBufsDBUpdate 1
<CMD> set gpsPrivate::lsgEnableNewDbApiInRestruct 1
<CMD> set init_design_settop 0
<CMD> set init_gnd_net {VSS }
<CMD> set init_lef_file ../../LEF/gsclib045.lef
<CMD> set init_mmmc_file gopi/mmmc.view
<CMD> set init_oa_search_lib {}
<CMD> set init_pwr_net VDD
<CMD> set init_verilog ../../NETLIST/tdsp_core.v
<CMD> set lsgOCPGainMult 1.000000
<CMD> set pegDefaultResScaleFactor 1.000000
<CMD> set pegDetailResScaleFactor 1.000000
<CMD> set ptngPAMaxRouteLayer 9
<CMD> set spgDecolorGeom 1
<CMD> set timing_library_float_precision_tol 0.000010
<CMD> set timing_library_load_pin_cap_indices {}
<CMD> set timing_library_mark_cell_latch_construct_flag 0
<CMD> set tso_post_client_restore_command {update_timing ; write_eco_opt_db
;}
<CMD> set init_mmmc_file gopi/less_mmmc.view
<CMD> init_design
Loading LEF file ../../LEF/gsclib045.lef ...

Set DBUPerIGU to M2 pitch 200.
viaInitial starts at Sun Apr 3 19:41:11 2016

viaInitial ends at Sun Apr 3 19:41:11 2016
*** Begin netlist parsing (mem=374.3M) ***
Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.
Reading verilog netlist '../../NETLIST/tdsp_core.v'
*** Memory Usage v#1 (Current mem = 382.531M, initial mem = 98.977M) ***
*** End netlist parsing (cpu=0:00:00.1, real=0:00:00.0, mem=382.5M) ***
Top level cell is tdsp_core.
Loading view definition file from gopi/less_mmmc.view
Reading set_max_lib timing library
'/Projects/Training/user5/work/suraj/LIB/slow.lib' ...
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'CO' of cell
'ADDFHX2' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'S' of cell
'ADDFHXL' is not defined in the library.
'ADDFHXL' is not defined in the library.
'ADDFXL' is not defined in the library.
'ADDFXL' is not defined in the library.

'ADDHX2' is not defined in the library.
'ADDHX2' is not defined in the library.
'ADDHXL' is not defined in the library.
'ADDHXL' is not defined in the library.
**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'Y' of cell
'AND2X4' is not defined in the library.
'AND2XL' is not defined in the library.
'AND3XL' is not defined in the library.
Message <TECHLIB-436> has exceeded the message display limit of '20'.
setMessageLimit/set_message_limit sets the limit.
unsetMessageLimit/unset_message_limit can be used to reset this.
Read 477 cells in library 'gpdk045bc'
Reading set_min_lib timing library '/Projects/Training/user5/work/suraj/LIB/fast.lib'
...
Read 477 cells in library 'gpdk045wc'
*** End library_loading (cpu=0.00min, mem=0.0M, fe_cpu=0.28min,
fe_real=8.93min, fe_mem=428.6M) ***
Starting recursive module instantiation check.
No recursion found.
Building hierarchical netlist for Cell tdsp_core ...

*** Netlist is unique.
** info: there are 1523 modules.
** info: there are 3533 stdCell insts.
*** Memory Usage v#1 (Current mem = 439.117M, initial mem = 98.977M) ***
*info: set bottom ioPad orient R0
Horizontal Layer M1 offset = 95 (derived)
Vertical Layer M2 offset = 100 (derived)
Generated pitch 0.2 in Metal9 is different from 0.33 defined in technology file in
unpreferred direction.
preferred direction.
Set Default Net Delay as 1000 ps.
Set Default Net Load as 0.5 pF.
Set Input Pin Transition Delay as 0.1 ps.
Initializing multi-corner RC extraction with 2 active RC Corners ...

**WARN: (ENCEXT-6202): In addition to the technology file, capacitance table file
is specified for all RC corners. If the technology file for all RC corners is already
specified, the capacitance table file is not required for preRoute and postRoute
extraction. In a new session, the capacitance table files can be removed from the
create_rc_corner command. In this case, the technology file will be used for
preRoute extraction and effort level medium/high/signoff of postRoute extraction.
Type 'man ENCEXT-6202' for more detail.
Reading Capacitance Table File ../../DATA/captable_cmax ...
Cap table was created using Encounter 09.10-p004_1.
Process name: GPDK45.
**WARN: (ENCEXT-2760): Layer M10 specified in the cap table is ignored because
it is greater than the maximum number of layers, 9, specified in the technology
LEF file. Check the cap table for the invalid layer specification.
**WARN: (ENCEXT-2776): The via resistance between layers M1 and M2 is not
defined in the capacitance table file. The via resistance of 6.7 Ohms defined in
the LEF technology file will be used as via resistance between these layers.

**WARN: (ENCEXT-2710): Basic Cap table for layer M10 is ignored because the
layer is not specified in the technology LEF file.
Reading Capacitance Table File ../../DATA/captable_cmin ...
Cap table was created using Encounter 09.10-p004_1.
Process name: GPDK45.

**WARN: (ENCEXT-2710): Basic Cap table for layer M10 is ignored because the
layer is not specified in the technology LEF file.
Importing multi-corner RC tables ...
Summary of Active RC-Corners :
Analysis View: my_analysisi_func_max_cmin

RC-Corner Name
RC-Corner Index
: set_rc_cmax
:0
RC-Corner Temperature : 0 Celsius

RC-Corner Cap Table : '../../DATA/captable_cmax'
RC-Corner PreRoute Res Factor
:1
RC-Corner PreRoute Cap Factor
:1
RC-Corner PostRoute Res Factor
:1
RC-Corner PostRoute Cap Factor
:1
RC-Corner PostRoute XCap Factor
:1
RC-Corner PreRoute Clock Res Factor : 1

(effortLevel low)]
[Derived from postRoute_res
RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

(effortLevel low)]
RC-Corner PostRoute Clock Cap Factor : 1
(effortLevel low)]
[Derived from postRoute_cap
RC-Corner PostRoute Clock Res Factor : 1

(effortLevel low)]
RC-Corner Technology file: '../../DATA/qrcTechFile'
Analysis View: my_analysis_view_test_max_cmax

RC-Corner Name
RC-Corner Index
: set_rc_cmax
:0

:1
:1
:1
:1
:1

(effortLevel low)]

(effortLevel low)]
(effortLevel low)]

(effortLevel low)]
Analysis View: my_analysis_view_func_max_cmin

RC-Corner Name
RC-Corner Index
: set_rc_cmin
:1

RC-Corner Cap Table : '../../DATA/captable_cmin'
:1
:1
:1
:1
:1

(effortLevel low)]

(effortLevel low)]
(effortLevel low)]

(effortLevel low)]
Analysis View: my_analysis_view_test_max_cmin

RC-Corner Name
RC-Corner Index
: set_rc_cmin
:1

:1
:1
:1
:1
:1

(effortLevel low)]

(effortLevel low)]
(effortLevel low)]

(effortLevel low)]
Analysis View: my_analysis_view_func_min_cmax

RC-Corner Name
RC-Corner Index
: set_rc_cmax
:0

:1
:1
:1
:1
:1

(effortLevel low)]

(effortLevel low)]
(effortLevel low)]

(effortLevel low)]
Analysis View: my_analysis_view_test_min_cmax

RC-Corner Name
RC-Corner Index
: set_rc_cmax
:0

:1
:1
:1
:1
:1

(effortLevel low)]

(effortLevel low)]
(effortLevel low)]

(effortLevel low)]
Analysis View: my_analysis_view_func_min_cmin

RC-Corner Name
RC-Corner Index
: set_rc_cmin
:1

:1
:1
:1
:1
:1

(effortLevel low)]

(effortLevel low)]
(effortLevel low)]

(effortLevel low)]
Analysis View: my_analysis_view_test_min_cmin

RC-Corner Name
RC-Corner Index
: set_rc_cmin
:1

:1
:1
:1
:1
:1

(effortLevel low)]

(effortLevel low)]
(effortLevel low)]

(effortLevel low)]

Technology file '../../DATA/qrcTechFile' associated with first view
'my_analysisi_func_max_cmin' specified to command 'set_analysis_view' will be
used as the primary corner for the multi-corner extraction. TQRC/IQRC extraction
leverages a single primary corner extraction, then derives the other corners
based on their technology files and operating conditions from the primary corner.
*Info: initialize multi-corner CTS.
CTE reading timing constraint file '../../SDC/test.sdc' ...
Current (total cpu=0:00:17.2, real=0:08:57, peak res=423.5M, current
mem=549.4M)
**WARN: (TCLNL-330):
set_input_delay on clock root 'clk' is not supported. You
should use the -source option to set_clock_latency to provide this offset. You can
also use the global timing_allow_input_delay_on_clock_source to allow
set_input_delay assertion to have an effect on clock source paths beginning at
this clock root. (File ../../SDC/test.sdc, Line 188).
Number of path exceptions in the constraint file = 47

Number of paths exceptions after getting compressed = 5
INFO (CTE): read_dc_script finished with 1 WARNING.
Ending "Constraint file reading stats" (total cpu=0:00:00.1, real=0:00:00.0, peak
res=441.4M, current mem=566.7M)
mem=566.7M)
CTE reading timing constraint file '../../SDC/func.sdc' ...
mem=568.1M)
**WARN: (TCLNL-330):
set_input_delay on clock root 'clk' is not supported. You
should use the -source option to set_clock_latency to provide this offset. You can
also use the global timing_allow_input_delay_on_clock_source to allow
set_input_delay assertion to have an effect on clock source paths beginning at
this clock root. (File ../../SDC/func.sdc, Line 188).
Number of path exceptions in the constraint file = 47

Number of paths exceptions after getting compressed = 5
INFO (CTE): read_dc_script finished with 1 WARNING.
Ending "Constraint file reading stats" (total cpu=0:00:00.0, real=0:00:00.0, peak
res=441.8M, current mem=569.6M)

mem=569.6M)
Total number of combinational cells: 317
Total number of sequential cells: 150
Total number of tristate cells: 10
Total number of level shifter cells: 0
Total number of power gating cells: 0
Total number of isolation cells: 0
Total number of power switch cells: 0
Total number of pulse generator cells: 0
Total number of always on buffers: 0

Total number of retention cells: 0
List of usable buffers: BUFX2 BUFX12 BUFX16 BUFX20 CLKBUFX2 BUFX3 BUFX4
CLKBUFX12 CLKBUFX16 CLKBUFX20 CLKBUFX4 CLKBUFX6 CLKBUFX8 BUFX8
CLKBUFX3 BUFX6
Total number of usable buffers: 16
List of unusable buffers:
Total number of unusable buffers: 0
List of usable inverters: CLKINVX1 CLKINVX2 CLKINVX12 CLKINVX16 CLKINVX20
INVX1 CLKINVX3 CLKINVX4 CLKINVX6 INVX12 INVX2 INVX3 CLKINVX8 INVX20
INVX4 INVX6 INVX16 INVXL INVX8
Total number of usable inverters: 19
List of unusable inverters:
Total number of unusable inverters: 0
List of identified usable delay cells: DLY1X4 DLY2X4 DLY3X4 DLY1X1 DLY4X1
DLY2X1 DLY3X1 DLY4X4
Total number of identified usable delay cells: 8
List of identified unusable delay cells:
Total number of identified unusable delay cells: 0
*** Summary of all messages that are not suppressed in this session:
Severity ID
Count Summary
WARNING ENCEXT-6202
1 In addition to the technology file, capa...
WARNING ENCEXT-2710
2 Basic Cap table for layer M%d is ignored...
WARNING ENCEXT-2760
4 Layer M%d specified in the cap table is ...
WARNING ENCEXT-2776
16 The via resistance between layers %s and...
*** Message Summary: 23 warning(s), 0 error(s)
<CMD> fit
<CMD> loadIoFile io/tdsp_core.save.io
Reading IO assignment file "io/tdsp_core.save.io" ...
<CMD> fit
<CMD> getLogFileName
<CMD> clearGlobalNets
<CMD> globalNetConnect VDD -type pgpin -pin VDD -inst *
<CMD> globalNetConnect VSS -type pgpin -pin VSS -inst *
<CMD> set sprCreateIeStripeNets {}
<CMD> set sprCreateIeStripeLayers {}
<CMD> set sprCreateIeStripeWidth 10.0
<CMD> set sprCreateIeStripeSpacing 2.0
<CMD> set sprCreateIeStripeThreshold 1.0
<CMD> addStripe -skip_via_on_wire_shape Noshape -block_ring_top_layer_limit
Metal7 -max_same_layer_jog_length 0.14 -padcore_ring_bottom_layer_limit
Metal5 -set_to_set_distance 25 -skip_via_on_pin Standardcell
-stacked_via_top_layer Metal9 -padcore_ring_top_layer_limit Metal7 -spacing 0.45
-xleft_offset 5 -xright_offset 5 -merge_stripes_value 0.165 -layer Metal6
-block_ring_bottom_layer_limit Metal5 -width 2.1 -nets {VDD VSS}
-stacked_via_bottom_layer Metal1
Starting stripe generation ...

Non-Default setAddStripeOption Settings :
NONE
The core ring for VDD is incomplete. The core ring will not be used as a boundary
for stripes. In this situation, the power planner will generate stripes only within
the core area.
The core ring for VSS is incomplete. The core ring will not be used as a boundary
the core area.
Stripe generation is complete; vias are now being generated.
The power planner created 12 wires.
*** Ending Stripe Generation (totcpu: 0:00:00.0,real: 0:00:00.0, mem: 576.1M)
***
Metal4 -set_to_set_distance 25 -ybottom_offset 5 -skip_via_on_pin Standardcell
-merge_stripes_value 0.165 -direction horizontal -layer Metal5
-block_ring_bottom_layer_limit Metal4 -ytop_offset 5 -width 2.1 -nets {VDD VSS}

NONE
the core area.
the core area.
***


NONE
the core area.
the core area.
***

NONE
the core area.
the core area.
**WARN: (ENCPP-170):
The power planner failed to create a wire at (16.05,
0.00) (16.05, 147.06) because same wire already exists.
***
<CMD> setPlaceMode -fp false
<CMD> placeDesign
*** Starting placeDesign default flow ***
**INFO: Enable pre-place timing setting for timing analysis
Set Using Default Delay Limit as 101.
**WARN: (ENCDC-1629): The default delay limit was set to 101. This is less than
the default of 1000 and may result in inaccurate delay calculation for nets with a
fanout higher than the setting. If needed, the default delay limit may be
adjusted by running the command 'set delaycal_use_default_delay_limit'.
Set Default Net Load as 0 pF.
**INFO: Analyzing IO path groups for slack adjustment
Effort level <high> specified for reg2reg_tmp.30748 path_group

################################################
#################################
# Design Stage: PreRoute
# Design Mode: 90nm
# Analysis Mode: MMMC non-OCV
# Extraction Mode: default
# Delay Calculation Options: engine=aae SIAware=false(opt_signoff)
# Switching Delay Calculation Engine to AAE
################################################
#################################
Calculate delays in BcWc mode...
Topological Sorting (CPU = 0:00:00.0, MEM = 602.0M, InitMEM = 601.0M)
AAE_MTTC: End Timing Check Calculation. (CPU Time=0:00:00.0, Real
Time=0:00:00.0)
AAE_MTTC: End Timing Check Calculation. (CPU Time=0:00:00.0, Real
Time=0:00:00.0)
AAE_THRD: End delay calculation. (MEM=746.086 CPU=0:00:01.3
REAL=0:00:02.0)
*** CDM Built up (cpu=0:00:01.9 real=0:00:02.0 mem= 746.1M) ***
*** Start deleteBufferTree ***
Info: Detect buffers to remove automatically.
Analyzing netlist ...
All-RC-Corners-Per-Net-In-Memory is turned ON...
Updating netlist
*summary: 49 instances (buffers/inverters) removed
*** Finish deleteBufferTree (0:00:00.1) ***

**INFO: Disable pre-place timing setting for timing analysis
Set Using Default Delay Limit as 1000.
Set Default Net Load as 0.5 pF.
Extracting standard cell pins and blockage ......
Pin and blockage extraction finished
Extracting macro/IO cell pins and blockage ......
Pin and blockage extraction finished
*** Starting "NanoPlace(TM) placement v#1 (mem=714.0M)" ...
**WARN: (ENCTS-403):
Delay calculation was forced to extrapolate table data
outside of the characterized range. In some cases, extrapolation can reduce the
accuracy of the delay calculation. You can enable more detailed reporting of
these cases by enabling the command 'setDelayCalMode -reportOutBound true'.
Type 'man ENCTS-403' for more detail.
*** Build Buffered Sizing Timing Model
(cpu=0:00:03.2 mem=714.0M) ***
*** Build Virtual Sizing Timing Model
(cpu=0:00:03.5 mem=714.2M) ***
Options: timingDriven clkGateAware ignoreScan pinGuide congEffort=auto
gpeffort=medium
**WARN: (ENCSP-9042):
be ignored.
Scan chains were not defined, -ignoreScan option will
Define the scan chains before using this option.

Type 'man ENCSP-9042' for more detail.
#std cell=3505 (0 fixed + 3505 movable) #block=0 (0 floating + 0 preplaced)
#ioInst=0 #net=3562 #term=13004 #term/net=3.65, #fixedIo=144,
#floatIo=0, #fixedPin=117, #floatPin=0
stdCell: 3505 single + 0 double + 0 multi
Total standard cell length = 8.9324 (mm), area = 0.0153 (mm^2)
**Info: (ENCSP-307): Design contains fractional 34 cells.
Average module density = 0.699.

Density for the design = 0.699.
= stdcell_area 44662 sites (15274 um^2) / alloc_area 63898 sites (21853
um^2).
Pin Density = 0.291.
= total # of pins 13004 / total Instance area 44662.
=== lastAutoLevel = 8
Clock gating cells determined by native netlist tracing.
Iteration 1: Total net bbox = 1.748e+04 (8.19e+03 9.29e+03)
Est. stn bbox = 1.984e+04 (9.25e+03 1.06e+04)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 757.0M
Est. stn bbox = 1.984e+04 (9.25e+03 1.06e+04)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 757.0M
Est. stn bbox = 2.340e+04 (1.06e+04 1.28e+04)
cpu = 0:00:01.0 real = 0:00:01.0 mem = 757.0M
Est. stn bbox = 5.562e+04 (2.65e+04 2.91e+04)
cpu = 0:00:02.4 real = 0:00:02.0 mem = 759.0M
Est. stn bbox = 6.078e+04 (3.07e+04 3.00e+04)
cpu = 0:00:01.9 real = 0:00:02.0 mem = 759.0M
Est. stn bbox = 6.242e+04 (3.09e+04 3.15e+04)
cpu = 0:00:01.4 real = 0:00:02.0 mem = 760.0M
Est. stn bbox = 6.425e+04 (3.24e+04 3.18e+04)
cpu = 0:00:00.2 real = 0:00:00.0 mem = 762.0M

Est. stn bbox = 6.476e+04 (3.26e+04 3.21e+04)
cpu = 0:00:01.4 real = 0:00:02.0 mem = 766.0M
Est. stn bbox = 6.498e+04 (3.21e+04 3.29e+04)
cpu = 0:00:01.3 real = 0:00:01.0 mem = 766.0M
Est. stn bbox = 6.520e+04 (3.22e+04 3.30e+04)
cpu = 0:00:00.5 real = 0:00:01.0 mem = 766.0M
Est. stn bbox = 6.670e+04 (3.34e+04 3.33e+04)
cpu = 0:00:05.1 real = 0:00:05.0 mem = 766.0M
Est. stn bbox = 6.670e+04 (3.34e+04 3.33e+04)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 766.0M
Est. stn bbox = 6.670e+04 (3.34e+04 3.33e+04)
cpu = 0:00:00.0 real = 0:00:00.0 mem = 766.0M
*** cost = 5.491e+04 (2.78e+04 2.71e+04) (cpu for global=0:00:13.9)
real=0:00:15.0***
Info: 12 clock gating cells identified, 12 (on average) moved
Core Placement runtime cpu: 0:00:12.1 real: 0:00:13.0
**WARN: (ENCSP-9025):
No scan chain specified/traced.
Type 'man ENCSP-9025' for more detail.

*** Starting refinePlace (0:00:45.0 mem=701.6M) ***
Total net length = 5.491e+04 (2.777e+04 2.715e+04) (ext = 7.567e+03)
Move report: Detail placement moves 3505 insts, mean move: 1.08 um, max
move: 20.90 um
Max move on inst

(EXECUTE_INST/RC_CG_HIER_INST26/RC_CGIC_INST/LATCH): (65.81, 47.57) -->
(86.40, 47.88)
Runtime: CPU: 0:00:01.0 REAL: 0:00:01.0 MEM: 704.0MB
Summary Report:
Instances move: 3505 (out of 3505 movable)
Mean displacement: 1.08 um
Max displacement: 20.90 um (Instance:
EXECUTE_INST/RC_CG_HIER_INST26/RC_CGIC_INST/LATCH) (65.806, 47.572) ->
(86.4, 47.88)
Length: 38 sites, height: 1 rows, site name: CoreSite, cell type:
TLATNTSCAX16
Runtime: CPU: 0:00:01.0 REAL: 0:00:01.0 MEM: 704.0MB
*** Finished refinePlace (0:00:46.0 mem=704.0M) ***
*** End of Placement (cpu=0:00:20.9, real=0:00:22.0, mem=704.0M) ***
default core: bins with density > 0.75 = 34.6 % ( 28 / 81 )
Density distribution unevenness ratio = 5.731%
*** Free Virtual Timing Model ...(mem=704.0M)
Starting IO pin assignment...
Starting congestion repair ...
*** Starting trialRoute (mem=704.0M) ***
There are 0 guide points passed to trialRoute for fixed pins.

There are 0 guide points passed to trialRoute for pinGroup/netGroup/pinGuide
pins.
Options: -noPinGuide
Phase 1a-1d Overflow: 0.00% H + 0.00% V (0:00:00.1 704.0M)
Overflow: 0.00% H + 0.00% V (0:00:00.0 704.0M)
Phase 1l Overflow: 0.00% H + 0.00% V (0:00:00.2 712.0M)
Congestion distribution:
Remain
cntH
cntV
--------------------------------------------------------------------------5:
12728100.00%
12728100.00%
Total length: 6.305e+04um, number of vias: 25847

M1(H) length: 2.641e+01um, number of vias: 12887
M2(V) length: 2.550e+04um, number of vias: 12133
M9(H) length: 0.000e+00um
Peak Memory Usage was 712.0M

*** Finished trialRoute (cpu=0:00:00.6 mem=712.0M) ***
Local HotSpot Analysis: normalized max congestion hotspot area = 0.00,

normalized total congestion hotspot area = 0.00 (area is in unit of 4 std-cell row
bins)
describeCongestion: hCong = 0.00 vCong = 0.00
Trial Route Overflow 0.000000(H) 0.000000(V).
Start repairing congestion with level 1.
Skipped repairing congestion.
End of congRepair (cpu=0:00:00.6, real=0:00:01.0)
*** Finishing placeDesign default flow ***
**placeDesign ... cpu = 0: 0:24, real = 0: 0:26, mem = 695.2M **
Active setup views: my_analysisi_func_max_cmin
my_analysis_view_test_max_cmax my_analysis_view_func_max_cmin
my_analysis_view_test_max_cmin
Active hold views: my_analysis_view_func_min_cmax
my_analysis_view_test_min_cmax my_analysis_view_func_min_cmin
my_analysis_view_test_min_cmin
*** Summary of all messages that are not suppressed in this session:
Severity ID
Count Summary
WARNING ENCTS-403
1 Delay calculation was forced to extrapol...
WARNING ENCDC-1629
1 The default delay limit was set to %d. T...
WARNING ENCSP-9025
1 No scan chain specified/traced.
WARNING ENCSP-9042
1 Scan chains were not defined, -ignoreSca...
<CMD> setNanoRouteMode -quiet -timingEngine {}

<CMD> setNanoRouteMode -quiet -routeWithSiPostRouteFix 0
<CMD> setNanoRouteMode -quiet -drouteStartIteration default
<CMD> setNanoRouteMode -quiet -routeTopRoutingLayer 3
<CMD> setNanoRouteMode -quiet -routeBottomRoutingLayer 1
<CMD> setNanoRouteMode -quiet -drouteEndIteration default

<CMD> setNanoRouteMode -quiet -routeWithTimingDriven false
<CMD> setNanoRouteMode -quiet -routeWithSiDriven false
Running Native NanoRoute ...
<CMD> routeDesign -globalDetail
#routeDesign: cpu time = 00:00:00, elapsed time = 00:00:00, memory = 606.50
(MB), peak = 764.09 (MB)
#WARNING (NRIG-96) Selected single pass global detail route "-globalDetail".
Clock eco and post optimizations will not be run. See "man NRIG-96" for more
details.
Begin checking placement ... (start mem=699.7M, init mem=699.7M)
*info: Placed = 3505
*info: Unplaced = 0
Placement Density:69.90%(15274/21853)
Finished checkPlace (cpu: total=0:00:00.0, vio checks=0:00:00.0; mem=699.7M)
#**INFO: honoring user setting for routeWithTimingDriven set to false
#**INFO: honoring user setting for routeWithSiDriven set to false
changeUseClockNetStatus Option : -noFixedNetWires

*** Changed status on (0) nets in Clock.
*** End changeUseClockNetStatus (cpu=0:00:00.0, real=0:00:00.0,
mem=699.7M) ***
globalDetailRoute
#setNanoRouteMode -routeBottomRoutingLayer 1
#setNanoRouteMode -routeTopRoutingLayer 3
#setNanoRouteMode -routeWithSiDriven false
#setNanoRouteMode -routeWithTimingDriven false
#Start globalDetailRoute on Sun Apr 3 19:43:52 2016

#
#WARNING (NRDB-976) The TRACK STEP 0.1900 for preferred direction tracks is
smaller than the PITCH 0.2000 for LAYER Metal3. This will cause routability
problems for NanoRoute.
#WARNING (NRDB-976) The TRACK STEP 0.1900 for preferred direction tracks is
smaller than the PITCH 0.2000 for LAYER Metal5. This will cause routability
problems for NanoRoute.
#NanoRoute Version v14.28-s005 NR160313-1959/14_28-UB
#Bottom routing layer is M1, bottom routing layer for shielding is M1, bottom
shield layer is M1
#Start routing data preparation.
#WARNING (NRDB-2077) The below via enclosure for LAYER Metal1 is not
specified for width 0.060.
#WARNING (NRDB-2078) The above via enclosure for LAYER Metal2 is not
#WARNING (EMS-27) Message (NRDB-2077) has exceeded the current message
display limit of 20.
#To increase the message display limit, refer to the product command reference
manual.
#WARNING (EMS-27) Message (NRDB-2078) has exceeded the current message
display limit of 20.
#To increase the message display limit, refer to the product command reference
manual.
#WARNING (NRDB-812) Cuts within VIA VIA12_4C violate adjacent cut spacing
rule.
rule.
rule.
rule.
#Minimum voltage of a net in the design = 0.000.
#Maximum voltage of a net in the design = 1.320.
#Voltage range [0.000 - 0.000] has 1 net.
#Voltage range [1.320 - 1.320] has 1 net.
#Voltage range [0.000 - 1.320] has 3884 nets.
# Metal1
H Track-Pitch = 0.190
Line-2-Via Pitch = 0.125
# Metal2
V Track-Pitch = 0.200
# Metal3
# Metal4
# Metal5
# Metal6
# Metal7
#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch.
# Metal8
# Metal9
#Regenerating Ggrids automatically.
#Auto generating G-grids with size=20 tracks, using layer Metal2's pitch =
0.200.
#Using automatically generated G-grids.
#Done routing data preparation.
#cpu time = 00:00:03, elapsed time = 00:00:03, memory = 678.16 (MB), peak =
764.09 (MB)
#Merging special wires...
#Number of eco nets is 0
#
#Start data preparation...

#
#Data preparation is done on Sun Apr 3 19:43:56 2016
#
#Analyzing routing resource...
#Routing resource analysis is done on Sun Apr 3 19:43:56 2016
#
# Resource Analysis:
#
#
# Layer
Routing #Avail
Direction Track
#Track
#Total
Blocked
%Gcell
Gcell
Blocked
# -------------------------------------------------------------# Metal 1
774
1369
1.68%
# Metal 2
743
1369
0.00%
# Metal 3
774
1369
0.00%
# Metal 4
598
145
1369
8.11%
# Metal 5
596
178
1369
5.41%
# Metal 6
569
174
1369
5.41%
# -------------------------------------------------------------# Total
4054
10.99% 8214
3.43%
#
#
#
764.09 (MB)
#
#start global routing iteration 1...
764.09 (MB)
#
764.09 (MB)
#
764.09 (MB)
#
764.09 (MB)
#
#
#Total number of trivial nets (e.g. < 2 pins) = 324 (skipped).
#Total number of routable nets = 3562.
#Total number of nets in the design = 3886.
#
#3562 routable nets have only global wires.
#
#Routed nets constraints summary:
#----------------------------#
Rules Unconstrained
#----------------------------#
Default
3562
#----------------------------#
Total
3562
#----------------------------#
#Routing constraints summary of the whole design:

#----------------------------#
Rules Unconstrained
#----------------------------#
Default
3562
#----------------------------#
Total
3562
#----------------------------#
#
# Congestion Analysis: (blocked Gcells are excluded)
#
#
OverCon
#Gcell
Layer
%Gcell
(1) OverCon
# -------------------------------# Metal 1
0(0.00%) (0.00%)
# Metal 2
0(0.00%) (0.00%)
# Metal 3
0(0.00%) (0.00%)
# Metal 4
0(0.00%) (0.00%)
# Metal 5
0(0.00%) (0.00%)
# Metal 6
0(0.00%) (0.00%)
# -------------------------------#
Total
0(0.00%) (0.00%)
#
# The worst congested Gcell overcon (routing demand over resource in number
of tracks) = 1
#
#Complete Global Routing.
#Total wire length = 60311 um.

#Total half perimeter of net bounding box = 59121 um.
#Total wire length on LAYER Metal1 = 56 um.
#Total number of vias = 19573
#Up-Via Summary (total 19573):
#
#----------------------# Metal 1
12390
# Metal 2
7183
#----------------------#
19573
#
#Max overcon = 0 track.
#Total overcon = 0.00%.
#Worst layer Gcell overcon rate = 0.00%.
764.09 (MB)
#
#
#Start data preparation for track assignment...
#

#
764.09 (MB)
#Start Track Assignment.
#Done with 5080 horizontal wires in 1 hboxes and 5136 vertical wires in 1
hboxes.
hboxes.
#Complete Track Assignment.
#
#----------------------# Metal 1
12390
# Metal 2
7183
#----------------------#
19573
#
764.09 (MB)
#
#Cpu time = 00:00:06
#Elapsed time = 00:00:06
#Increased memory = 18.53 (MB)
#Total memory = 653.62 (MB)
#Peak memory = 764.09 (MB)
#
#Start Detail Routing..
#start initial detail routing ...
#
number of violations = 9
#
#
#
By Layer and Type :

MetSpc Totals
Metal1
Metal2
Totals
764.09 (MB)
#start 1st optimization iteration ...
#
764.09 (MB)
#Complete Detail Routing.

#Total number of multi-cut vias = 412 ( 1.8%)
#Total number of single cut vias = 22885 ( 98.2%)
#
single-cut
multi-cut
Total
#----------------------------------------------------------# Metal 1
14037 ( 97.1%)
412 ( 2.9%)
# Metal 2
8848 (100.0%)
0 ( 0.0%)
14449
8848
#----------------------------------------------------------#
22885 ( 98.2%)
412 ( 1.8%)
23297
#
#Total number of DRC violations = 0
#Cpu time = 00:00:22
#
#start routing for process antenna violation fix ...
764.09 (MB)
#
#
single-cut
multi-cut
Total
#----------------------------------------------------------# Metal 1
14037 ( 97.1%)
412 ( 2.9%)
# Metal 2
8848 (100.0%)
0 ( 0.0%)
14449
8848
#----------------------------------------------------------#
22885 ( 98.2%)
412 ( 1.8%)
23297
#
#Total number of net violated process antenna rule = 0
#
#
#Start Post Route wire spreading..
#
#Start data preparation for wire spreading...
#
#
764.09 (MB)
#
#Spread distance (# of tracks): min = 0.500000; max = 2.000000
#
#Start Post Route Wire Spread.
hboxes.
#Complete Post Route Wire Spread.
#

#
single-cut
multi-cut
Total
#----------------------------------------------------------# Metal 1
14037 ( 97.1%)
412 ( 2.9%)
# Metal 2
8848 (100.0%)
0 ( 0.0%)
14449
8848
#----------------------------------------------------------#
22885 ( 98.2%)
412 ( 1.8%)
23297
#
764.09 (MB)
#
#Post Route wire spread is done.
#
single-cut
multi-cut
Total
#-----------------------------------------------------------
# Metal 1
14037 ( 97.1%)
412 ( 2.9%)
# Metal 2
8848 (100.0%)
0 ( 0.0%)
14449
8848
#----------------------------------------------------------#
22885 ( 98.2%)
412 ( 1.8%)
23297
#
#
#Start DRC checking..
#
764.09 (MB)
#
764.09 (MB)
#CELL_VIEW tdsp_core,init has no DRC violation.
#Total number of net violated process antenna rule = 0
#detailRoute Statistics:
#Cpu time = 00:00:27
#
#globalDetailRoute statistics:
#Cpu time = 00:00:34
#Number of warnings = 51
#Total number of warnings = 52
#Number of fails = 0
#Total number of fails = 0
#Complete globalDetailRoute on Sun Apr 3 19:44:26 2016
#
#routeDesign: cpu time = 00:00:34, elapsed time = 00:00:34, memory = 715.65
(MB), peak = 764.09 (MB)

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Checking out Encounter license ...

Encounter_Digital_Impl_Sys_XL 14.2 license checkout succeeded.

All rights reserved.

* This program contains confidential and trade secret information *

* distribution or disclosure of this program or any portion of it,*

* program, without the express, prior written consent of

2655 Seely Avenue

San Jose, CA 95134, USA

@(#)CDS: Encounter v14.28-s033_1 (64bit) 03/21/2016 13:34 (Linux 2.6.18194.el5)

@(#)CDS: NanoRoute v14.28-s005 NR160313-1959/14_28-UB (database version

**INFO: MMMC transition support version v31-84

<CMD> set_global _enable_mmmc_by_default_flow

<CMD> set delaycal_input_transition_delay 0.1ps

Loading LEF file ../../LEF/gsclib045.lef ...

viaInitial starts at Sun Apr 3 19:41:11 2016

**WARN: (TECHLIB-436): Attribute 'max_fanout' on 'output/inout' pin 'CO' of cell

Building hierarchical netlist for Cell tdsp_core ...

Initializing multi-corner RC extraction with 2 active RC Corners ...

Type 'man ENCEXT-2776' for more detail.

Type 'man ENCEXT-2776' for more detail.

Analysis View: my_analysisi_func_max_cmin

RC-Corner Temperature : 0 Celsius

RC-Corner PreRoute Cap Factor

RC-Corner PostRoute Res Factor

RC-Corner PostRoute Cap Factor

RC-Corner PostRoute XCap Factor

RC-Corner PreRoute Clock Res Factor : 1

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_max_cmax

RC-Corner Temperature : 0 Celsius

RC-Corner PreRoute Cap Factor

RC-Corner PostRoute Res Factor

RC-Corner PostRoute Cap Factor

RC-Corner PostRoute XCap Factor

RC-Corner PreRoute Clock Res Factor : 1

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_func_max_cmin

RC-Corner Temperature : 125 Celsius

RC-Corner PreRoute Cap Factor

RC-Corner PostRoute Res Factor

RC-Corner PostRoute Cap Factor

RC-Corner PostRoute XCap Factor

RC-Corner PreRoute Clock Res Factor : 1

[Derived from postRoute_res

RC-Corner PreRoute Clock Cap Factor : 1 [Derived from postRoute_cap

[Derived from postRoute_cap

RC-Corner PostRoute Clock Res Factor : 1

[Derived from postRoute_res

RC-Corner Technology file: '../../DATA/qrcTechFile'

Analysis View: my_analysis_view_test_max_cmin

RC-Corner Temperature : 125 Celsius

RC-Corner PreRoute Cap Factor

RC-Corner PostRoute Res Factor