Samples of Exercise Solutions From Part II Chapters 19-25

Digital Electronics and Design with VHDL, Volnei A.
Pedroni, ElsevierMorgan Kaufmann, 2008
Digital Electronics and Design with VHDL

Volnei A. Pedroni
ElsevierMorgan Kaufmann, 2008
Samples of Exercise Solutions for Part II (Chapters 19-25)

Below are solutions for some of the 545 exercises contained in the book.
Chapter 19: VHDL Summary
Exercise 19.9: Generic shift register
As seen in Section 14.1, a shift register (SR) is simply a string of serially connected D-type flip-flops
commanded by a common clock signal and, optionally, also by a reset signal. Design the SR of Figure
14.2(a) using the COMPONENT construct to instantiate N = 4 DFFs. Can you make your code generic (arbitrary
N)?
Solution
The generic solution is presented here, which consists of having the number of stages (N) specified by means
of the GENERIC attribute (hence any size SR can be obtained by simply changing this parameter). The
corresponding circuit is shown below.
q1
q2
d
rst
q
rst
q3
d
q
rst
qN
d
q
rst
clk
rst
Two generic solutions are presented next. In the first, a regular behavioral code is used, while a structural
code (using the COMPONENT construct) is presented in the second.
Solution 1: With a regular behavioral code.
------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.all;
------------------------------------------------ENTITY shift_register IS
GENERIC (N: INTEGER := 4); --number of stages
PORT (d, clk, rst: IN STD_LOGIC;
q: BUFFER STD_LOGIC_VECTOR(1 TO N));
END shift_register;
------------------------------------------------ARCHITECTURE shift_register OF shift_register IS
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN
q <= (OTHERS => '0');
Digital Electronics and Design with VHDL, Volnei A. Pedroni, ElsevierMorgan Kaufmann, 2008
ELSIF (clk'EVENT AND clk='1') THEN
q <= d & q(1 TO N-1);
END IF;
END PROCESS;
END shift_register;
-------------------------------------------------
Solution 2: With a structural code (with COMPONENT)

------ The component (flip-flop): ------------LIBRARY ieee;
----------------------------------------------ENTITY flipflop IS
PORT (d, clock, reset: IN STD_LOGIC;
q: OUT STD_LOGIC);
END flipflop;
----------------------------------------------ARCHITECTURE flipflop OF flipflop IS
BEGIN
PROCESS (clock, reset)
BEGIN
IF (reset='1') THEN
q <= '0';
ELSIF (clock'EVENT AND clock='1') THEN
q <= d;
END IF;
END PROCESS;
END flipflop;
----------------------------------------------------- The main code: --------------------------------------LIBRARY ieee;
-------------------------------------------------------------ENTITY shift_register IS
GENERIC (N: INTEGER := 4); --number of stages
PORT (d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR(1 TO N));
END shift_register;
-------------------------------------------------------------ARCHITECTURE shift_register OF shift_register IS
SIGNAL temp: STD_LOGIC_VECTOR(0 TO N);
COMPONENT flipflop IS
PORT (d, clock, reset: IN STD_LOGIC;
q: OUT STD_LOGIC);
END COMPONENT;
BEGIN
temp(0) <= d;
generate_SR: FOR i IN q'RANGE GENERATE
DFF: flipflop PORT MAP (temp(i-1), clk, rst, temp(i));
END GENERATE generate_SR;
q <= temp(1 TO N);
END shift_register;
--------------------------------------------------------------
Simulation results (from the circuit synthesized with either code above) are shown next. Observe that after
every positive clock edge the input data train advances one position. Observe also the operation of the reset
signal, which is asynchronous.
Chapter 20: VHDL Design of Combinational Logic Circuits

Exercise 20.7: Parity generator
Parity detectors were studied in Section 11.7. In continuation to that, the figure below shows the top-level
diagram of a parity generator. The circuit has a 7-bit input, a, and an 8-bit output, b. It has also a single-bit
parity-selection input, called parity. The circuit must detect the parity of a, then add an extra bit to it (on its
left) to produce b, whose parity (number of '1's) must be odd if parity = '0' or even if parity = '1'. Design this
circuit using VHDL.
a(6:0)
Parity
generator
b(7:0)
parity
Solution
A VHDL code for this problem is shown below. As before, the industry-standard data type (STD_LOGIC) was
employed to specify all input and output signals.
---------------------------------------------------LIBRARY ieee;
---------------------------------------------------ENTITY parity_generator IS
PORT (a: IN STD_LOGIC_VECTOR(6 DOWNTO 0);
parity: IN STD_LOGIC;
b: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END parity_generator;
---------------------------------------------------ARCHITECTURE parity_generator OF parity_generator IS
BEGIN
PROCESS (a, parity)
VARIABLE temp: STD_LOGIC;
BEGIN
temp := '0';
FOR i IN a'RANGE LOOP
temp := temp XOR a(i);
END LOOP;
b(7) <= parity XNOR temp;
b(6 DOWNTO 0) <= a(6 DOWNTO 0);
END PROCESS;
END parity_generator;
----------------------------------------------------
Simulation results, obtained from the circuit synthesized with the code above, are shown next. The first graph
is for odd parity (parity='0'), while the second is for even parity (parity='1')
Chapter 21: VHDL Design of Combinational Arithmetic Circuits

Exercise 21.7: Signed and unsigned adders/subtracters #1
In the adder/subtracter design of Section 21.3, two solutions were presented, one for INTEGER I/Os and the
other for STD_LOGIC_VECTOR I/Os. Present another solution, this time with STD_LOGIC_VECTOR inputs and
INTEGER outputs.
Solution
a) Discussion
The first thing to remember is that in all four main VHDL packages related to STD_LOGIC (numeric_std,
std_logic_arith, std_logic_unsigned, and std_logic_signed) addition and subtraction functions are defined
with the output having the same number of bits as the largest input (there is no provision for the carry-out bit,
implying that overflow can always occur; for instance, that is the way it is done in typical CPUs, that is, all
registers have the same length and only one register is used to store additions and subtractions). However, if
carry-out is needed, a good practice is to use only operands of type INTEGER (the inputs can be converted to
INTEGER before entering the + or functions, with the result then converted to whatever type is desired
afterward).
Another thing to remember is that the hardware in this case (with N-bit inputs and output) does not depend on
the system being signed or unsigned (only the interpretation of the results changes see details in Section
3.2).
Finally, it is important to also have in mind that some type-conversion functions are allowed to produce
outputs with more bits than the inputs. An example is the function CONV_INTEGER(arg), available in the
packages std_logic_arith, std_logic_unsigned, and std_logic_signed (see book appendices). For example, say
that arg is N bits wide, and that the resulting integer is M bits wide, where M>N. If the package
std_logic_unsigned is used, then the MN most significant bits of the result are filled with 0s; however, if
std_logic_signed is used instead, then those bits are filled with the sign bit (that is, with copies of args
MSB).
b) Code for STD_LOGIC_VECTOR inputs and INTEGER output
Two VHDL codes that solve this problem are shown below. In both, the inputs and the output are N bits
wide. Note that, in order to be able to add signals of type STD_LOGIC_VECTOR, the std_logic_(un)signed
package was included in the library declarations.
In Solution 1, an unsigned system was considered. Hence std_logic_unsigned was chosen and the output
range was specified to be non-negative (from 0 to 2**N1). In Solution 2, the system was considered to be
signed, so std_logic_signed was chosen and the output range was specified to be from 2**(N1) to
2**(N1)1. However, as explained in Section 3.2 (and mentioned in the discussion above), this does not
affect the hardware. This fact can be observed in the simulation results from the two codes below, which are
exactly alike (only the interpretation of the results changes, because bitwise the plots are exactly the same).
Solution 1: For an unsigned system
--------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_unsigned.all;
--------------------------------------------------------------ENTITY adder_sub IS
GENERIC (N: INTEGER := 8); --number of input bits
PORT (a, b: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
sum, sub: OUT INTEGER RANGE 0 TO 2**N-1);
END adder_sub;
--------------------------------------------------------------ARCHITECTURE adder_sub OF adder_sub IS
BEGIN
sum <= CONV_INTEGER (a + b);
sub <= CONV_INTEGER (a - b);
END adder_sub;
---------------------------------------------------------------
Simulation results from Solution 1 are shown below. Note that, as expected, overflow can occur (for example,
120+150=270 27028=14).
Solution 2: For a signed system

--------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_signed.all;
--------------------------------------------------------------ENTITY adder_sub IS
GENERIC (N: INTEGER := 8); --number of input bits
PORT (a, b: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
sum, sub: OUT INTEGER RANGE -2**(N-1) TO 2**(N-1)-1);
END adder_sub;
--------------------------------------------------------------ARCHITECTURE adder_sub OF adder_sub IS
BEGIN
sum <= CONV_INTEGER (a + b);
sub <= CONV_INTEGER (a - b);
END adder_sub;
---------------------------------------------------------------
Simulation results from Solution 2 are presented next. Note that these results are exactly the same as those
obtained in Solution 1.
Chapter 22: VHDL Design of Sequential Circuits

Exercise 22.5: Digital PWM
A digital PWM (Pulse Width Modulator) takes a clock waveform as input and delivers a pulse train with
variable (programmable) duty cycle at the output. In the illustration below, the duty cycle is 2/7 (or 28.6%),
because the output stays high during 2 out of every 7 clock periods. Besides the clock, the circuit must have a
control input, called duty, which determines the duty cycle (see table below). Design this circuit using VHDL.
clk
PWM
duty
clk
y
duty
0
1
2
3
4
5
6
7
Duty cycle
0/7 (0%)
1/7 (14,3%)
2/7 (28,6%)
3/7 (42.9%)
4/7 (57.1%)
5/7 (71.4%)
6/7 (85.7%)
7/7 (100%)
Solution
A VHDL code for this problem is shown below. Note that to make it work for any PWM size, the number of
control bits (N) was entered using the GENERIC attribute.
--------------------------------------------------ENTITY pwm IS
GENERIC (N: INTEGER := 3); -- # of control bits
PORT (clk: IN STD_LOGIC;
duty: IN INTEGER RANGE 0 TO 2**N-1;
y: OUT STD_LOGIC);
END pwm;
--------------------------------------------------ARCHITECTURE pwm OF pwm IS
BEGIN
PROCESS (clk)
VARIABLE count: INTEGER RANGE 0 TO 2**N;
BEGIN
IF (clk'EVENT AND clk='1') THEN
count := count + 1;
IF (count=duty) THEN
y <= '1';
ELSIF (count=2**N) THEN
y <= '0';
count := 0;
END IF;
END IF;
END PROCESS;
END pwm;
---------------------------------------------------
Simulation results from the circuit inferred from the code above are shown next. In this simulation, N=3 bits
were used to represent duty, so it resembles exactly the case depicted in the previous figure. Waveforms for
duty=2 and duty=6 are depicted in the plots.
Chapter 23: VHDL Design of State Machines

Exercise 23.11: Signal generator
A new approach for the construction of arbitrary binary waveforms was introduced in Section 15.7, which
consists of using two multiplexers controlled by two finite state machines (FSMs) that operate at different
clock edges. The first FSM-MUX pair is responsible for generating the desired waveform, while the second
FSM-MUX pair is responsible for eliminating any glitches.
Since such a structure employs more than one FSM, it can be designed using either the multi-machine
approach or the quasi-single-machine approach (see Section 15.6). The former was employed in the design of
a signal generator in Section 23.3. Repeat that design employing now the latter approach. The desired signal
generator is depicted (again) in the figure below.
clk
Signal
generator
clk
clk
y
T
Solution
As in Section 23.2, the circuit can be divided into two sections, one producing the intermediate signal x (with
glitches) in the figure below, and the other the final signal, y (without glitches). Hence both FSMs can be
modeled with three states (A, B, C). The first circuit must produce x=1 when in state A, x=clk when in state
B, and again x=1 when in state C, while the second circuit must produce y=x when in A, y=1 when in B
(to eliminate the glitch), and again y=x when in C. The corresponding quasi-single-machine is depicted on
the right of the figure below.
Waveform
generator
B
clk
C
1
MUX2
A
1
clk
MUX1
clk
Glitch
remover
sel1
sel2
T
A
x
B
1
C
x
Comb.
logic
DFFs
FSM1
A VHDL code for this circuit is shown next.

---------------------------------------------ENTITY sig_generator IS
PORT (clk: IN BIT;
y: OUT BIT);
END sig_generator;
---------------------------------------------ARCHITECTURE sig_generator OF sig_generator IS
SIGNAL x: BIT;
SIGNAL sel1, sel2: INTEGER RANGE 0 TO 1;
TYPE state IS (A, B, C);
SIGNAL pr_state1, nx_state1: state;
BEGIN
----- Lower section of FSM1: ----PROCESS (clk)
BEGIN
Comb.
logic
(FSM2)
DFFs
pr_state1 <= nx_state1;
END IF;
END PROCESS;
----- Upper section of FSM1: ----PROCESS (pr_state1, clk)
BEGIN
CASE pr_state1 IS
WHEN A =>
sel1 <= 1;
nx_state1 <= B;
WHEN B =>
sel1 <= 0;
nx_state1 <= C;
WHEN C =>
sel1 <= 1;
nx_state1 <= A;
END CASE;
END PROCESS;
----- MUX1: ---------------------x <= clk WHEN sel1=0 ELSE '1';
----- Quasi-FSM2: ---------------PROCESS (clk)
BEGIN
CASE pr_state1 IS
WHEN A =>
sel2 <= 0;
WHEN B =>
sel2 <= 1;
WHEN C =>
sel2 <= 0;
END CASE;
END IF;
END PROCESS;
----- MUX2: ---------------------y <= x WHEN sel2=0 ELSE '1';
END sig_generator;
----------------------------------------------
Simulation results are presented below. Note that, as expected, glitches do occur in x, but are eliminated in y.
Chapter 24: VHDL Design of State Machines

Exercise 24.7: Type IV simulation of a parity detector
The parity detector of Example 19.3 was simulated, using VHDL and ModelSim, in Exercises 24.5 and 24.6
above, where type I and type II testbenches were employed, respectively. In continuation to those exercises,
perform now a type IV simulation for that circuit. To do so, introduce in the test file information about
expected values for y (can be a waveform, like Example 24.6), then create a process that compares those
values to the actual values of y using the ASSERT statement. Recall that for type II and type IV simulations an
SDF file (Appendix C) is required (the study of appendices A and C is recommended before trying to solve
this exercise).
Solution
The same input signal used in example 19.3 (see Figure 19.7) will be employed here (with the obvious
difference that now VHDL will be used to create it instead of a graphical tool). Such a signal (x) is shown in
the figure below, which also exhibits the expected outputs, y and y, where y represents the functionalanalysis output (no propagation delays types I and III testbenches), while y represents the timing-analysis
output (with propagation delays types II and IV testbenches).
x
00000000
00000001
160ns
00000010
320ns
11111100
480ns
01111111
640ns
11111111
800ns
00011000
960ns
y
y
Both files (design and test) needed for this simulation are presented below. Note that the design file is simply
a copy of that in Example 19.3. The test file, on the other hand, contains a stimulus-generation process
(responsible for creating x), plus two processes responsible for the automated analysis of the results (one
process creates the template, which is similar to the waveform y shown above, with a fixed propagation
delay of 10ns, while the other is responsible for comparing the template to the actual output, performed at
every 20ns).
------ Design file: ------------------------------LIBRARY ieee;
--------------------------------------------------ENTITY parity_detector IS
GENERIC (N: INTEGER := 8); --number of bits
PORT (x: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
y: OUT STD_LOGIC);
END parity_detector;
--------------------------------------------------ARCHITECTURE structural OF parity_detector IS
SIGNAL internal: STD_LOGIC_VECTOR(N-1 DOWNTO 0);
BEGIN
internal(0) <= x(0);
gen: FOR i IN 1 TO N-1 GENERATE
internal(i) <= internal(i-1) XOR x(i);
END GENERATE;
y <= internal(N-1);
END structural;
-------------------------------------------------------- Test file: --------------------------------LIBRARY ieee;
--------------------------------------------------ENTITY test_parity_detector IS
GENERIC (N: INTEGER := 8); -- # of input bits
END test_parity_detector;
--------------------------------------------------ARCHITECTURE test OF test_parity_detector IS
COMPONENT parity_detector IS
PORT (x: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
y: OUT STD_LOGIC);
END COMPONENT;
-----------------------------SIGNAL x: STD_LOGIC_VECTOR(N-1 DOWNTO 0) := "00000000";
SIGNAL y: STD_LOGIC;
SIGNAL template: STD_LOGIC := '0';
CONSTANT delay: TIME := 10 ns; --estimated propag. delay
------------------------------
BEGIN
dut: parity_detector PORT MAP (x=>x, y=>y);
----- Generation of x: ------PROCESS
BEGIN
WAIT FOR 160 ns;
x <= "00000001";
WAIT FOR 160 ns;
x <= "00000010";
WAIT FOR 160 ns;
x <= "11111100";
WAIT FOR 160 ns;
x <= "01111111";
WAIT FOR 160 ns;
x <= "11111111";
WAIT FOR 160 ns;
x <= "00011000";
WAIT;
END PROCESS;
----- generate template: ----PROCESS
BEGIN
WAIT FOR delay; --estimated propag. delay
WAIT FOR 160 ns;
template <= '1';
WAIT FOR 320 ns;
template <= '0';
WAIT FOR 160 ns;
template <= '1';
WAIT FOR 160 ns;
template <= '0';
WAIT;
END PROCESS;
----- verify output: --------PROCESS
BEGIN
WAIT FOR 20 ns;
ASSERT (y=template)
REPORT "Output differs from template!"
SEVERITY FAILURE;
END PROCESS;
END test;
---------------------------------------------------
In our design, the files above were saved with the names parity_detector.vhd (design file) and
test_parity_detector.vhd (test file). Therefore, the files created by the compiler (Quartus II in this example),
following the procedure of Appendix C, were parity_detector.vho (new design file) and
parity_detector_vhd.sdo (SDF file). These two files, along with test_parity_detector.vhd, are needed by
ModelSim to perform the type IV simulation.
Continuing with the procedure of Appendix C, combined with Appendix A, and using the EP2C35F672C6
Cyclone II device (DE2 board), an actual propagation delay around 8ns results. The resulting ModelSim plots
for this type IV simulation are shown below.
Chapter 25: Simulation with SPICE
Exercise 25.3: SPICE simulation of a multiplexer

A TG-based 2x1 multiplexer was described in Example 11.6, and then used in Example11.7 to construct a
larger (4x1) multiplexer. (The corresponding circuits are repeated in figures (a) and (b) below, respectively.)
(2)
(3)
M4
(2)
M3
M6
(4) sel
M2
(10)
(4)
(5)
X2
M1
(a)
0
(9)
y (5)
(6)
M5
(3)
X1
(b)
X3
y (8)
sel 1
(7)
sel 0
(6)
a. Write a SPICE code to simulate the TG-based 2x1 multiplexer of figure (a). Assume that =0.2um and
adopt minimum size for the nMOS transistors and twice that for the pMOS ones (that is, (W/L)n=3/2 and
(W/L)p=6/2). Use either Level3 or BSIM3v3 models for the transistors (consult the MOSIS site at
www.mosis.org). Generate suitable signals to verify the multiplexers functionality.
b. Using .SUBCKT to instantiate the multiplexer of part (a) above, construct a SPICE code and test the
transient response and operation of the 4x1 multiplexer of figure (b).
Solution
A SPICE code for part (b) of this exercise is presented below (which indeed includes part (a)). The circuit
node numbers and transistor names are included in figure (a) and (b) above. As requested, the nMOS and
pMOS transistors sizes are (W/L)n=3/2 and (W/L)p=6/2), respectively, with =0.2um. The BSIM3v3
model (see pages 628-630) was employed to represent the MOSFET characteristics.
*----File containing the BSIM3v3 MOSFET model:-----.INC C:\ORCAD\MY_CIRCUITS\MOSFET_MODELS.CIR
*-----Defaults:------------------------------------.OPTIONS DEFL=0.4U DEFW=0.6U DEFAD=2P DEFAS=2P
*-----Subcircuit (2x1_multiplexer):----------------.SUBCKT multiplexer_2x1 1 2 3 4 5
M1 5 4 3 0 N
M2 5 6 3 1 P W=1.2U
M3 5 6 2 0 N
M4 5 4 2 1 P W=1.2U
M5 6 4 0 0 N
M6 6 4 1 1 P W=1.2U
.ENDS
*-----Final circuit (4x1_multiplexer):-------------X1 1 2 3 6 9 multiplexer_2x1
X2 1 4 5 6 10 multiplexer_2x1
X3 1 9 10 7 8 multiplexer_2x1
VDD 1 0 DC 3.3V
*-----Transient response:--------------------------Va 2 0 PULSE (0V 3.3V 25NS 0NS 0NS 25NS 275NS)
Vb 3 0 PULSE (0V 3.3V 100NS 0NS 0NS 25NS 200NS)
Vc 4 0 PULSE (0V 3.3V 175NS 0NS 0NS 25NS 125NS)
Vd 5 0 PULSE (0V 3.3V 250NS 0NS 0NS 25NS 50NS)
Vsel0 6 0 PULSE (0V 3.3V 75NS 0NS 0NS 75NS 150NS)
.TRAN 0.22NS 300NS
.PROBE V(2) V(3) V(4) V(5) V(6) V(7) V(8) V(9) V(10)
.END
*-------------------------------------------------
Simulation results obtained with PSpice 15.7 (see Appendix B) are presented below, where the following
signals are depicted:
V(2): Input voltage at node 2 (input a of the multiplexer);
V(3): Input voltage at node 3 (input b of the multiplexer);
V(4): Input voltage at node 4 (input c of the multiplexer);
V(5): Input voltage at node 5 (input d of the multiplexer);
V(6): Input voltage at node 6 (selection port sel0 of the multiplexer);
V(7): Input voltage at node 7 (selection port sel1 of the multiplexer);
V(9): Output voltage at node 9 (output of the first multiplexer);
V(10): Output voltage at node 10 (output of the second multiplexer);
V(8): Output voltage at node 8 (output of the last multiplexer).
Observe in the last plot, V(8), that the values obtained for the low-to-high (LH) and high-to-low (HL) inputto-output (IO) propagation delays are tpIO_LH 5ns and tpIO_HL 3ns.
5ns
3ns
Propagation delays from select-to-output (SO) are illustrated in the next set of plots. In this case, the final part
of the code was replaced with the following:
*-----Transient response:--------------------------Va 2 0 DC 0V
Vb 3 0 DC 3.3V
Vc 4 0 DC 0V
Vd 5 0 DC 0V
Vsel1 7 0 DC 0V
.TRAN 0.1NS 150NS
.PROBE V(2) V(3) V(4) V(5) V(6) V(7) V(8) V(9) V(10)
Consequently, all input signals are kept at fixed values, with a=c=d=0 and b=1. By switching sel0
between 0 and 1, the following propagation delays are observed: tpSO_LH 13ns and tpSO_HL 13ns.
13ns
13ns

Samples of Exercise Solutions From Part II Chapters 19-25

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Samples of Exercise Solutions From Part II Chapters 19-25

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Digital Electronics and Design with VHDL, Volnei A.

Pedroni, ElsevierMorgan Kaufmann, 2008

Digital Electronics and Design with VHDL

Samples of Exercise Solutions for Part II (Chapters 19-25)

Solution 2: With a structural code (with COMPONENT)

Chapter 20: VHDL Design of Combinational Logic Circuits

Chapter 21: VHDL Design of Combinational Arithmetic Circuits

Solution 2: For a signed system

Chapter 22: VHDL Design of Sequential Circuits

Chapter 23: VHDL Design of State Machines

A VHDL code for this circuit is shown next.

Chapter 24: VHDL Design of State Machines

Chapter 25: Simulation with SPICE

Exercise 25.3: SPICE simulation of a multiplexer

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