Migration of traditional 2-D CMOS to 3-D has been elusive, since inherent customization requirements

of CMOS circuits are not compatible for fine-grained 3-D. Partial attempts for 3-D CMOS with die-die and
layer-layer stacking show incremental density benefits, but retain same CMOS scaling challenges, and add
new constraints. In contrast to CMOS that evolved focusing on device centric mindset, where devices are
scaled first, and circuit and layouts are optimized as afterthoughts, we propose a nanoscale fine-grained 3-D
integrated circuit fabric (Skybridge) that provides an integrated solution for all nanoscale technology
aspects. Key to this mindset is the design of core fabric components that synergistically help to address
device, circuit, connectivity, thermal and manufacturing issues in an integrated 3-D compatible manner.
Uniformly doped and shaped vertical nanowires are fundamental building blocks, and serve as template
(Fig. 1A); realization of all fabric features is through functionalizing this template using material deposition
techniques. Vertical-Gate-All-Around (V-GAA) Junctionless transistors (Fig. 1B) with uniform doping are
active devices. These devices are stacked in vertical nanowires, and interconnected for functional circuits.
Bridges (Fig. 1C) and Coaxial structures (Fig. 1D) allow signal routing in 3-D, and also help in noise
mitigation. Heat extraction features (Heat Extraction Pillars (Fig. 1E) and Heat Junction (Fig. 1F)) are other
intrinsic fabric components; these are used for thermal management. Due to the unique 3-D integration
approach with uniform vertical nanowires, lithographic precision (required only for nanowire pattern
definition) and doping requirements (performed apriori during wafer preparation) are significantly less.
Circuits are designed in Skybridge to be compatible with underlying fabric; only single type uniformly
sized transistors are used for all logic and memory. Supported circuit styles include cascaded vs. compound,
and dual-rail vs. single-rail with high fan-in options. A full-adder design is shown in Fig. 1G as example.
Volatile memory requirements are met through a novel circuit that uses synchronous clock and data signals
for memory operation (Fig. 1H), and follows Skybridge circuit style.
The benchmarking of Skybridge circuits shows tremendous benefits. Our bottom up evaluation method
using TCAD Process, Device and HSPICE circuit simulators accounting for process parameters, material
properties, nanoscale transport, 3-D circuit style, layout and parasitics reveals 24.6x density and 13.25x
performance/watt benefits compared to CMOS for a 4-bit CLA, and 4.6x density, 4.2x active power and
51.2x leakage power benefits with comparable performance for Skybridge RAM in comparison to CMOS
SRAM at 16nm (Fig. 1I).
Experimental validation of the core Junctionless device concept and demonstration of key manufacturing
steps mitigate technology risks. Characterization results of a p-type junctionless transistor in 2-D with 30nm
width, 15nm thickness, and 200nm channel length is shown in Fig. 1J; the device characteristics show
expected device behavior with 103 ION/IOFF and -0.3V VTH. Figs. 1K-L show key manufacturing steps
required for Skybridge fabric assembly, starting with high aspect ratio nanowire patterning to planarization
of materials and anisotropic material depositions. Formation of all active components will follow similar
material deposition steps. The full paper will contain further details of all aspects of the fabric.