Beruflich Dokumente
Kultur Dokumente
Aim:
To Simulate Monostable multivibrator using PSPICE and implement using
hardware
To study the waveform at collector of transistors.
Apparatus Required:
PC with PSPICE software, BC107,Resistors, Capacitors,CRO,Function
generators.
Circuit Diagram:
MONOSTABLE MULTI WITH EMITTER BIAS
V1
10Vdc
2
C 1
0 .0 1 u
2
R 1
780
C 2
R 2
2
0 .5 u
10k
1
C 3
0 .0 1 u
1
R 3
1
R 4
1
2
1k
V1 = 0
V 2 = -5 V
TD = 0
TR = 0
TF = 0
PW = 20m s
PER = 30m s
650
V2
V
Q 1
Q 2
BC 107A
BC 107A
2
R 5
2
R 6
3 .3 k
1
330
1
Simulated Output:
Result:
Thus the Monostable multivibrator is simulated(using pspice) and its output
waveform is observed
Bistable Multivibrator
Aim:
Apparatus Required:
PC with PSPICE software
Circuit Diagram:
Simulated Output:
Result:
Thus the Bistable multivibrator is simulated(using pspice) and its output waveform
is observed
Apparatus Required:
S.No
Apparatus Name
Range
BC 107
Qty
Transistor
Resistor
Capacitor
CRO
(0 30)MHZ
RPS
(0-30) V
ORCAD suite
VB= VE + VBE=1.5+0.7=2.2V
VB= [VCC /( R1+R2 ) ]* R2
2.2= [15 /( R1+R2 ) ]* R2
R2/( R1+R2 ) =2.2/15=0.146
R1* R2 /( R1+R2 ) = RB
Let R1=128 K, then R2=21.882=22 K
Oscillator Design
Frequency fT = _1000 Hz
fT = 1/ 2 RC
Assume C = 0.1F
R = 1/2 f TC=1.59K
Circuit Diagram:
V2
15Vdc
R 1
C 7
128k
R 3
6k
C 2
Q 1
R 2
22k
R 6
C 4
6k
Q 2
22uf
10u
R 4
128k
R 5
BC 107A
2 .2 u f
R 7
1 .5 k
R 8
R 10
0 .1 u f
1 .5 9 k
3k
BC 107A
22k
C 5
R 11
1 .5 9 k
C 3
10uf
R 9
1 .5 k
C 6
0 .1 u f
Procedure:
1. The circuit is constructed as per the given circuit diagram.
2. Observe the sine wave output.
3. Note down the practical frequency and compare it with the theoretical
frequency.
Result:
Thus the Wien Bridge Oscillator designed, constructed, tested, Simulated
using Pspice and the output sine waveform is drawn
Theoretical frequency
=
Practical frequency
=
Aim :
To simulate tuned collector oscillator using Pspice and to obtain its output
waveform for the given frequency .
V1
12V dc
2
2
L2
C1
2
1
0.0 2 H
R1
0.0 1 u
C2
68k
1
Q2
0.0 1 u
B C 107A
2
R3
2
1k
R2
10k
C3
1
1n
R4
1k
RV 5
100k
1
T i t le
S iz e
A
D ate :
< T i t le >
D ocum ent N um ber
<D oc>
M o n d a y , J a n u a ry 0 1 , 2 0 0 7
R ev
<R ev C ode>
S heet
of
Procedure:
1. The circuit is drawn as per the given circuit diagram on the schematic page of
Capture CIS.
2. Create and edit simulation profile.
3. Observe the sine wave output.
Result:
Thus the tuned collector Oscillator simulation was done using Pspice and the
output sine waveform was observed.
circuit. The operation of the circuit to this point has generated a very steep leading edge for the
output pulse.
CIRCUIT DIAGRAM:
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Supply voltage is kept at 12V.
3. CRO connected at the output is adjusted and a sharp narrow intense wave output is
obtained.
4. The amplitude and time period of the output is noted.
5. The output waveform is plotted in a graph.
6. Then the practical value of the frequency is calculated.
TABULATION:
Amplitude (in volts)
MODEL GRAPH:
RESULT:
Thus a free running blocking Oscillator is constructed and the output waveform is plotted.