Lab & Course Exam 2

ECE 3EJ4

27 Nov 2013

Name:____________________________ Stud. # and Signature:___________________________________

Answer all 4 questions. Circle the letters e.g. (A) corresponding to your answers. Time 120 minutes.
If you cannot find a choice close to your answer, add a letter, e.g. (I) for 1(a), circle it and then write yours.

1. A n-bit R-2R DAC is shown. Given that VREF = -15V.

(1a) What is the output if n = 6, R = 100k, and digital
input code is 110001?
(A) -11.48 (B) 11.48
(C) -11.25 (D) 11.25
(E) -5.77
(F) 5.77
(G) -5.625 (H) 5.625

(1b-1e) A 4-bit weighted-R DAC is shown.

Given that VREF = -5V and R = 10k.
(1b) What is the full scale voltage?
(A) 5V
(B) -5V
(C) 4.7V
(D) -4.7V
(E) 4.5V
(F) -4.5V

(1c) What is the resolution?

(A) 0.3125V
(B) 0.6250V

(C) 0.9375V

(D) 1.2500V

(1d) What is the output voltage if the input code is 1110?

(A) -2.813V
(B) -1.875V
(C) -2.5V
(E) 2.813V
(F) 1.875V
(G) 2.5V

(E) 1.5625V

(F) 1.8750V

(D) -4.392V
(H) 4.392V

(1e) What is the output voltage if the input code is 1111, if the 2R (on the top) is changed to 1.8R?
(A) 4.6875V
(B) -4.6875V
(C) 4.98V
(D) -4.98V
(E) 1.25V
(F) -1.25V
(G) 3.75V
(H) -3.75V

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Lab & Course Exam 2

ECE 3EJ4

27 Nov 2013

Name:____________________________ Stud. # and Signature:___________________________________

(1f-1i) An analog multiplication system is shown above. The reference voltages are all -5V.
(1f) What is the output of the ADC, if the input to R-2R DAC is 1010, and the input to Weighted-R
DAC is 1010?
(A) 01100100
B) 1000111
(C) 11100001
(D) 10101111
(E) 11100011

(1g) What is the required output from the R-2R and Weighted-R DAC to make the ADC get the correct
digital output in the previous question (1f)?
(A) 4.22V
(B) 4.41V
(C) 3.125V
(D) 6.64V
(E) 5.41V

(1h) If the 8-bit ADC is realized by the parallel (flash) algorithm, how many comparators and resistors
are required to complete an AD conversion?
(A) 7, 8
(B) 15, 16
(C) 31, 32
(D) 63, 64
(E) 127, 128
(F) 255, 256
(G) 511, 512
(H) 1023, 1025

(1i) How many resistors (in total) are required in the full DAC circuits to implement each of the two
DACs, that is, the R-2R and Weighted-R DACs, respectively?
(A) 9, 5
(B) 5, 9
(C) 4, 5
(D) 5, 4
(E) 4, 4
(F) 5, 5
(G) 8, 4
(H) 4, 8

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Lab & Course Exam 2

ECE 3EJ4

27 Nov 2013

Name:____________________________ Stud. # and Signature:___________________________________

2. The multistage amplifier circuit shown has
VCC = |VEE| = 10V, I1 = 100A, I2 = 1mA,
I3 = 10mA, VA1=VA2=VA4=very large,
VA3 = 75V, VT = 25mV, R1 = 500k,
RL = 10k, VO(DC) = 0V, all |VBE's| = 0.7V,
all 's = 100 , and assume that all BJTs are
in the active region of operation.
(2a) What is the amplifiers configuration?
(A) Differential-input, single-ended-output
(B) Differential-input, differential-output
(C) Single-ended-input, single-ended-output
(D) Single-ended-input, differential-output
(E) Common emitter
(F) Common base
(G) Common collector
3
(2b) Find gm1, gm2, and gm3 (all answers in mS).
(A) 1.98, 1.98, 1.98
(B) 3.96, 3.96, 3.96
(E) 1.98, 43.96, 43.96
(F) 3.96, 43.96, 43.96
(I) 43.96, 43.96, 1.98
(J) 43.96, 43.96, 3.96

(2c) Find r1, r2, and r3 (all answers in k).

(A) 50.5, 50.5, 50.5
(B) 101, 101, 101
(E) 50.5, 2.3, 2.3
(F) 101, 2.3, 2.3
(I) 2.3, 2.3, 50.5
(J) 2.3, 2.3, 101

(2d) Find RC (all answers in k).

(A) 0.182
(B) 0.36
(C) 1.8
(G) 36.36
(H) 50
(I) 100

(C) 1.98, 1.98, 43.96

(G) 1.98, 3.96, 43.96

(D) 3.96, 3.96, 43.96

(H) 3.96, 1.98, 43.96

(C) 50.5, 50.5, 2.3

(G) 50.5, 101, 2.3

(D) 101, 101, 2.3

(H) 101, 50.5, 2.3

(D) 3.62
(J) 181.8

(E) 10
(K) 363.6

(F) 18.2

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Lab & Course Exam 2

ECE 3EJ4

27 Nov 2013

Name:____________________________ Stud. # and Signature:___________________________________

(2e) Find ro3 (answer in k).
(A) 8.45
(B) 9.3

(C) 68.19

(D) 75

(E) 76.64

(2f) Find Adm1 (vc2/(v1-v2))

(A) 0.01
(B) 0.9997
(G) 3130
(H) 6260
(M) -46
(N) -199

(C) 2
(I) -0.01
(O) -3130

(D) 32
(J) -0.9997
(P) -6260

(E) 466
(K) -2

(F) 199
(L) -32

(2g) Calculate the gain of the second stage

(A) 0.01
(B) 0.9997
(C) 2
(G) 3130
(H) 6260
(I) -0.01
(M) -46
(N) -199
(O) -3130

(D) 32
(J) -0.9997
(P) -6260

(E) 466
(K) -2

(F) 199
(L) -32

(2h) Calculate the gain of the last stage

(A) 0.01
(B) 0.9997
(C) 2
(G) 3130
(H) 6260
(I) -0.01
(M) -46
(N) -199
(O) -3130

(D) 32
(J) -0.9997
(P) -6260

(E) 466
(K) -2

(F) 199
(L) -32

(F) 84.3

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Lab & Course Exam 2

ECE 3EJ4

27 Nov 2013

Name:____________________________ Stud. # and Signature:___________________________________

(2i) Calculate the differential mode input resistance in k.
(A) 0.25
(B) 0.76
(C) 2.3
(D) 18.2 (E) 77

(F) 101

(G) 10130

(H) 50530

(2j) Calculate the common mode input resistance in k.

(A) 0.25
(B) 0.76
(C) 2.3
(D) 18.2 (E) 77

(F) 101

(G) 10130

(H) 50530

(2k) Calculate the output resistance of the circuit in k.

(A) 0.25
(B) 0.76
(C) 2.3
(D) 18.2 (E) 77

(F) 101

(G) 10130

(H) 50530

(2l) Find the differential mode gain of the entire circuit (vo/(v1-v2))? This is the same as Av1Av2Av3.
(A) 0.01
(B) 0.9997 (C) 2
(D) 32
(E) 45.96
(F) 198.5
(G) 3130
(H) 6260
(I) -0.01
(J) -0.9997
(K) -2
(L) -32
(M) -45.96
(N) -198.5
(O) -3130
(P) -6260
(Q) 12510
(R) -12510

(2m) Calculate the common mode gain of the circuit

(A) 0.01
(B) 0.9997 (C) 2
(D) 32
(H) 6260
(I) -0.01
(J) -0.9997
(K) -2
(O) -3130
(P) -6260
(Q) 12510
(R) -12510

(E) 45.96
(L) -32
(S) 6.3

(F) 198.5
(M) -45.96
(T) -6.3

(G) 3130
(N) -198.5

(2n) Calculate the CMRR of the circuit in dB

(A) 0.01
(B) 0.9997 (C) 1.998
(D) 30
(H) 70
(I) 76
(J) 199
(K) 990

(E) 32
(L) 3130

(F) 46
(M) 6250

(G) 6.32
(N) 60
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Lab & Course Exam 2

ECE 3EJ4

27 Nov 2013

Name:____________________________ Stud. # and Signature:___________________________________

3. The circuit shows a single-transistor
CS amplifier operating in the saturation
mode with ID = 1mA. The circuit uses 2
coupling capacitors C1, C2 and a bypass
capacitor C3. Assume that capacitors
Cgd and Cgs in the n-MOSETs smallsignal model can be neglected. Given
that VTn= 1V, kn= 2mA/V2, VA=100V
and VDD = 10V.
(3a) What is the input resistance Rin looking into the gate of the transistor (the right of C1)?
(A) R sig //R 1 //R 2

(B) R1 +R 2

(C)

(D) R sig +R 1 +R 2

(E) R sig +(R 1 //R 2 )

(F) R1 //R 2

(G) 0

(H) R 1 //R 2 //R s

(I) ro +R s

(J) R1 //R 2 //ro

(3b) Find the output resistance Rout looking to the left of C1 . (Assume that RS is shorted for this problem).
(A) 0
(F) R D +R L

(C)
(H) (R D //ro R S )//R L

(B) R D
(G) R D //ro

(D) R D //ro R S
(I) R D //R L //(ro R S )

(E) R D //R L //ro

(J) (R D +ro R S )//R L

(3c) What is the overall gain A = vo/vsig?. Hint: First find vo/vgs, then vgs/vsig. Gain A is then the product.
(A) 1

(B) -1

(D) g m (R D //R L //ro )

(E)

g m (R D //R L //ro )(R1 //R 2 )

R sig +(R1 //R 2 )

g m (R D //R L //ro )
(H) g m [R D //R L //(ro R s )]
(1+g m R s )
g m (R D //R L )(R1 //R 2 )
(J)
(1+g m R s )[R sig +(R1 //R 2 )]

(G)

(C)

g m (R D //R L //ro )(R1 //R 2 )

R sig +(R1 //R 2 )

(F) g m (R D //R L //ro )

(I)

g m (R D //R L )
(1+g m R s )

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Lab & Course Exam 2

ECE 3EJ4

27 Nov 2013

Name:____________________________ Stud. # and Signature:___________________________________

(3d) Find the time constant associated with capacitor C1? (Hint: Neglect ro).
(A) C1 (R sig //R 1 //R 2 )
(B) C1[R sig //(R 1 +R 2 )]
(C)
(D) (R sig +R 1 +R 2 )C1
(E) C1[R sig +(R 1 //R 2 )]

(F) C1 (R1 //R 2 )

(G) 0

(I) (ro +R s )C1

(J) C1 (R1 //R 2 //ro )

(H) C1 (R s //R 1 //R 2 )

(3e) Find the time constant associated with capacitor C2? (Hint: Neglect ro).
RD
(A) 0
(B)
(C) C 2
(1 g m R s )
(F) C2 (R D +R L )
(G) C2 [(R D R s )//R L ]
(E) C2 (R D //R L )(1 g m R s )
(I) (R D +R L R s )C2
(J) C 2 [R sig +(R 1 //R 2 )+(R D //R L )(1 g m R s )]

R D //R L
1 gmR s
(H) C2 (R D //R L )

(D) C 2

(3f) Find the time constant associated with capacitor C3? (Hint: Neglect ro).

1
1
(C) C3 g m //
(D) C3 g m +
(A) 0
(B)

RS
RS

1
(G) C3 R S //

gm

RD
1 gmRS

(E) [R sig +(R 1 //R 2 )+R D +R L +R S ]C3

(F) C3

(H) (R D //R L )(1 g m R S ) / C3

1
(I) C3 R S

gm

(3g) Find the numerical values of gm and ro.

(A) 4 mS, 100 k
(B) 2 mS, 100 k
(E) 2 S, 100
(F) 2 mS, 1 k
(I) 0.4 mS, 1 k
(J) 2 mS,

(J) [(R sig //R 1 //R 2 )+(R D //R L //R S )]C3

(C 4 mS, 100
(G) 4 mS, 1 k

(D) 0.2 mS, 100 k

(H) 4 mS, 1

7 of 10

Lab & Course Exam 2

ECE 3EJ4

27 Nov 2013

Name:____________________________ Stud. # and Signature:___________________________________

(4) The current source circuit is shown below. Assume that IREF = 100 A VDD =|VSS| = 3.3V, L = 1m,
VTH ,n 0.6 V , kn 0.4 mA/V 2 , W L 1 10

VTH ,p 0.7 V , k p 0.2 mA/V 2 , W L 3 10

W L 2 20
W L 4 50

(4a) Find the gate voltage of Q1 and Q2?

VDD

VDD

(A) 2.48 V
(B) 2.54 V

IREF

Q4

Q3

(C) 2.38 V

vo

(D) 1.89 V

IO

(E) 2.48 V

(F) 2.38 V

Q1

Q2

(G) 2.28 V
(H) 2.28 V
-VSS

-VSS

(4b) If the ideal current source IREF is replaced by a resistor R, find the value of R?
(A) 25.8 k
(B) 25.4 k
(C) 23.8 k
(D) 20 k

(E) 18.9 k

(F) 22.8 k

(G) 24.5 k

(4c) Find the gate voltage of Q3 and Q4

(A) 2.05 V
(B) 2.38 V
(C) 2.15 V

(E) 0.916 V

(F) 2.38 V

(G) 2.15 V

(H) 24.8 k

(D) 2.28 V
(H) 2.28 V

8 of 10

Lab & Course Exam 2

ECE 3EJ4

27 Nov 2013

Name:____________________________ Stud. # and Signature:___________________________________

(4d) Find the output current, Io.
(A) 100 A
(B) 200 A

(C) 500 A

(F) 400 A

(H) 8000 A

(G) 4000 A

(D) 1000 A

(E) 2000 A

(4e) Now consider the common-source amplifier with active load shown below. What is its voltage gain of
10V/m . Other parameters as before.
this circuit for a 75 k load? Assume vo = 2.15 V, W L 5 10 , VA,p
(4e)
(A) 42 V/V

(B) 9.03 V/V

(C) 25 V/V
(D) 22.3 V/V
(E) 9.03 V/V
(F) 25 V/V
(G) 17.3 V/V
(H) 17.3 V/V

(4f) Find the maximum voltage at the output (vo) for which transistor Q4 can operate in saturation.
(A) 3 V
(B) 2.85 V
(C) 2.85 V
(D) 2.3 V

(E) 0.6 V

(F) 3.3 V

(G) 2.7 V

(H) 2.7 V

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Lab & Course Exam 2

ECE 3EJ4

27 Nov 2013

Name:____________________________ Stud. # and Signature:___________________________________

Useful Information remove this page for easy reference.

LP Low-pass

HP High pass

BP Band pass

BS Band stop or Notch AP All pass

Z Z
1
1
Parallel Impedance

e.g. Z1 //Z 2 Z parallel 1 2

Z1 +/Z 2
Z parallel
n Zn

Series Impedance Z series Z k

k

Common-source single-stage FET amplifier with load resistance RL is shown

Voltage Gain Av g m RD //RL //ro . ro is the ss-resistance between D & S

Kirchoffs Current Law (KCL) i n =0 or iin = iout

n

Kirchoffs Voltage Law (KVL)

Vn =0

or

Vsources,m = in Z n
m

Transconductance gm with source resistor RS degeneration

g m,eff

FET and BJT respectively

gm
1 g m RS

ADC/DAC: Dynamic Range 20 log 2n 1 .

VLSB 2 n VREF .

g m RD //RL r
o

2 1
VREF n .
2

VFull Scale

Av g m RD //RL //ro
ro is the ss resis tan ce
between D & S

SNR 6.02 N 1.76, dB . 20 log( AV as Number ), dB .

The time constant of a capacitor Ci is CiRi where Ri is the resistance seen by Ci that is obtained by reducing
all other capacitances to zero (open circuited) and the input signal source to zero.
PMOS : VTp 0;

vOV vSG VTp

iD,lin k p vSG VTp SD vSD ; 0 vSD vSG VTp

2

2
kp
iD,sat
vSG VTp 1 vSD ; vSD vSG VTp 0
2
NMOS : VTn 0; vOV vGS VTn

Small - signal Models

of FET and BJT

iD,lin kn vGS VTn DS vDS ; 0 vDS vGS VTn

2

k
2
iD,sat n vGS VTn 1 vDS ; vDS vGS VTn 0
2

BJT : g m

IC
40 I C ; g m r ;
VT

V VCE
VT
; r0 A
IB
IC

W
FET : g m kn VOV 2kn I D 2kn'
L

2I D

;
ID
VOV

r0

VA VDS
ID
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