Beruflich Dokumente
Kultur Dokumente
In(t)
A
Tb
Tb
-A
Tb
Tb
Tb
Tb
Tb
Tb
Tb
InQ-Phase (t)
InI-Phase (t)
0
t
-A
Ts=2Tb
Ts=2Tb
Ts=2Tb
Ts=2Tb
0
t
-A
Ts=2Tb
Ts=2Tb
Ts=2Tb
Ts=2Tb
Ts=2Tb
Ts=2Tb
Ts=2Tb
Ts=2Tb
-A
-A
Ts=2Tb
Ts=2Tb
Ts=2Tb
Ts=2Tb
QPSK(t)
01=7/4
00=/4
01=7/4
10=3/4
Modulator QPSK
t
-A
I-Phase
10
Bit Data
S to P
converter
Cos t
Sin t
Tb
Tb
Ts
00
Tb
Tb
Ts
Tb
Tb
Tb
Ts
Tb
Tb
Ts
QPSK
output
Q-Phase
11
01
I n (t ) A
(n 1)Tb t nTb
(2.1)
(
0
QPSK
input
I phase
n
( n 1) 2Tb t n 2Tb
(t ) A
(2.2)
(
0
(
0
QPSK
input
g c1 cos( c t init )
g c2 sin( c t init )
(2.3)
01
) dt
) dt
Decision Device
threshold = 0
P to S
Converter
) dt
Data Bit
Output
Decision Device
threshold = 0
3 5 7
,
,
,
4 2 4
4
(t )
(2.6)
(2.4)
00
Q-Phase
11
)
Sin (t +
10
(t )
Data Bit
Output
)
Cos (t +
Symbol
Decision
Circuit
)
Cos (t +
)
Sin (t +
I nQ phase (t ) A
I-Phase
) dt
(2.5)
Pb Q
2 b
N0
1 1 Q
2
2 b
N0
(2.7)
The equation 2.7 is not taking into account the error
that might be occur if the carrier frequency and symbol
timing is not synchronized between modulator and
demodulator.
The synchronization of carrier frequency and symbol
timing is done separately in this design. The maximum
likelihood (ML) carrier recovery method [1] is favored
ML tan
r ( t ) sin 2f c tdt
T0
r ( t ) cos 2f c tdt
T0
(2.8)
k 1
k Re Q k ( k ) A
Q( t )
t
t kT k
(2.9)
I
n
_
d_
dt
In(t)
A
clock
VCC
Tb
Tb
-A
Tb
d_
dt
Tb
Tb
Tb
Tb
Tb
Tb
QPSK(t)
01=7/4
00=/4
01=7/4
10=3/4
yn
J n
t
-A
Tb
Tb
Tb
Ts
Tb
Tb
Ts
Tb
Tb
Tb
Ts
Ts
01=7/4
10=3/4
Tb
QPSK(n)
01=7/4
00=/4
n
-A
QPSK(t)
01=7/4
00=/4
01=7/4
Tb
10=3/4
Tb
Ts
Tb
Tb
Ts
Tb
Tb
Ts
Tb
Tb
Tb
Ts
t
-A
Tb
Tb
Ts
Tb
Tb
Tb
Ts
Tb
Ts
Tb
Tb
Tb
Ts
QPSK(n)
01=7/4
00=/4
01=7/4
10=3/4
n
-A
Tb
Tb
Ts
Tb
Tb
Ts
Tb
Tb
Ts
Tb
Tb
Tb
Ts
In(t)
A
0
1
Tb
Tb
-A
Tb
Tb
Tb
Tb
Tb
Tb
Tb
S to P
converter
DDFS
Cosinus
and Sinus
Discrete Time
Signals Combiner
(Adders)
QPSK
discrete time
output
DAC
QPSK
output
Discrete Time
Mixers
Sign Bit
Akumulator
4 bit
3 bit
Addressing
3 bit
Addressing
QPSK
input
ADC
QPSK
discrete
time
input
ROM
Contain
7 bit
Discrete
Cosinus
value
Discrete Time
Integrator
Discrete Time
Mixers
DDFS
Cosinus
and Sinus
P to S
converter
Discrete Time
Mixers
Discrete Time
Integrator
Discrete Time
Decision Circuit
arctan (y / x)
Symbol /
Timing Phase
Synchronizer
Discrete Time
Decision Circuit
Timing Tone
Extraction
Internal
Timing Tone
ROM
Contain
7 bit
Discrete
Sinus
value
8 bit frequency
synthesizer
sinus output
LSB
Sign Bit
Akumulator
4 bit
Sampling
Clock
clock input
40.960 MHz
MSB
8 bit frequency
synthesizer
Cosinus output
LSB
Bit Data
Frequency Synthesizer
Cos( )
(beda fasa)
S/N
Cos(t-)
ROM
Cosinus
Sinthesizer
ROM
Sinus
Sinthesizer
(beda fasa)
ROM
Cosinus
Sinthesizer
Sinus
Counter
Shifter
ROM
Sinus
Sinthesizer
Cos( )
(beda fasa)
0.833
230 symbol
0.104
1.055
1000 symbol
0.089
1.2
1135 symbol
0.075
1.597
1103 symbol
0.0507
1.875
4300 symbol
0.0304
2.23
1003 symbol
0.0139
5.067
1632 symbol
0.00306
Cos(t-)
Shifted ROM Sinthesizer
Sin(t-)
Cos(t-)
Numerical Sinthesizer
t counter
Sin( )
BER
Sin(t-)
Sin ( )
Cosinus
Counter
Shifter
Duration
Sin(t-)
0.45
0.3
BER
0.4
0.35
0.25
0.2
0.15
0.1
0.05
0
-2
-1
2
Eb/No