FPGA Implementation of an OFDM Baseband

Transmitter
Ahmed Hechri
Laboratory EE, FSM, Av Ibn ElJazzar, 5019
Monastir, Tunisia
Email: ahmed.hechri@enim.rnu.tn

AbstractThe main objective of this paper is to show the design

implementation of an OFDM (Orthogonal Frequency Division
Multiplexing) transmitter that will be part of a future DVB-T
demonstrator. After system modeling and simulation, we
proceeded with the design architecture synthesis which will be
mapped to the Virtex-II Pro devices. Thanks to the flexibility
of the proposed architecture, the transmitter can be updated to
modulate any other communication system with relatively little
effort.
Keywords-component;OFDM;DVB-T; simulation;architecture;
flexibility.

I.

Mtibaa Abdellatif
Laboratory EE, FSM, Av Ibn ElJazzar, 5019
Monastir, Tunisia
Email: abdellatif.mtibaa@enim.rnu.tn

Section 4 demonstrates the simulation and implementation

results. Finally, the paper is concluded in section 5.
II.

OFDM TRANSMITTER

Terrestrial Digital Video Broadcasting (DVB-T) is

currently being introduced in many European countries and
planned to replace current analogue broadcasting schemes in a
large part of the world [3]. This system transmits compressed
digital audio, video and other data in an MPEG transport
stream, using OFDM modulation. Figure 1 show the block
diagram of a DVB-T transmission system and we will focus
only on the OFDM modulator.

INTRODUCTION (HEADING 1)

The orthogonal frequency division multiplexing (OFDM)

modulation has recently received considerable interest for its
advantages in high-bit-rate transmission over frequency
selective fading channels. In OFDM systems, the input highrate data stream is divided into many low-rate streams that are
transmitted in parallel [1], thereby increasing the symbol
duration and reducing the intersymbol interference. These
features have motivated the adoption of OFDM as a standard
many transmissions systems such as Digital Audio
Broadcasting (DAB), IEEE802.11a/g wireless LAN standard
and especially in digital video broadcasting (DVB-T) [2]. In
parallel, Field Programmable Gate Arrays (FPGAs) are also
emerging as a fundamental paradigm in the implementation of
these standards. This is due to their increased capabilities in
term of speed and resources. Moreover, the FPGA provide a
good combination of high-speed implementation features with
the flexibility of a digital platform.
The aim of this work is to implement the digital baseband
part of the OFDM transmitter that conforms to the DVB-T
standard. For experimentation we have exploited the resources
of the XUP Virtex-II Pro platform. In this work, the developed
architecture could be extended to design other OFDM-based
system, for example fixed and mobile WiMAX.
Present work is divided as follows: Section 2 describes the
OFDM transmitter and presents the model of the designed
system. In section 3, the proposed architecture is presented.

Video

Encoder

Audio

Encoder

OFDM MODULATOR
M
U
X

Encoder

Interleaver

Mapper

IFFT

Prefix

Amplifier

Data

Figure 1. DVB-T transmitter design

A. System description
As shown in figure 1 the encoded data is sent to the
interleaver block that decorrelates and spreads adjacent data
over many subcarriers. The data is then passed to a modulation
mapper, which is commonly Phase Shift Keyed (PSK) or
Quadrature Amplitude Modulation (QAM) depending on the
type of communication system. The modulator thus
concurrently and separately modulates a set of tones in the
OFDM spectrum. The output of the modulator is then
converted from serial to parallel form and the complex
frequency domain data is thus transformed to time domain
using Inverse Fast Fourier Transform (IFFT). The time varying
data is then cyclically extended with a cyclic prefix to reduce
inter-symbol interference between successive OFDM symbols.

Finally, the output of the cyclic prefix block is fed to the

digital to analog converter, and then sent to the antenna for
transmission.

Pseudo-code for ROM declaration:

Type ROM_Array is array (0 to 187)

of integer range 0 to 187;
Constant Content : ROM_Array
:=(1,13,2,25,14,3,37,26
15,4,49,38,27,16,5,61,50,39,28,17,73,62,
51,40,29,18,7,85,74,63,52,41,30,19,8,97,
86,75,64,53,42,31,20,9,109,98,87,76,65,5
4,43,32,21,10,121,110,99,88,77,66,55,44,
33,22,11,133,122,111,100,89,78,67,56,45,
34,23,12,145,134,123,112,101,90,79,68,57
,46,35,24,157,146,135,124,113,102,91,80,
69,58,47,36,169,158,147,136,125,114,103,
92,81,70,59,48,181,170,159,148,137,126,1
15);

B. System Model
The OFDM system was modeled using Matlab Simulink to
allow various parameters of the system to be varied and tested,
including those established by the DVB-T standard. The aim of
doing the simulations was to measure the performance of
OFDM under different channel conditions, and to allow for
different OFDM configurations to be tested. The model can be
seen in figure 2.

B.

Mapper

The mapper converts input data into complexed valued

constellation points, according to a given constellation [5].
Typical constellations for wireless applications are, BPSK,
QAM, and 16 QAM, see figure 3.
This block is implemented with 4 ROMs containing the
constellation mapping for each of the specified modulation
schemes, and one multiplexer which selects the In Phase and
Quadrature data from the desired modulation scheme stored
on ROMs, see figure 4.
Figure 2. Simulink OFDM Model

III.

THE PROPOSED ARCHITECTURE

In this section a more detailed explanation and hardware

architecture of the basic blocks in the OFDM system (already
seen in the previous section) will be provided. The used
methodology is based on the divide-and-conquer approach.
Each block in the architecture was designed and tested
separately, and later those blocks were assembled to compose
the complete system.

I
QPSK

BPSK

I
16QAM

Figure 3. Typical constellations

A. Inerleaver
The interleaving block is used to provide robustness against
burst errors. These interleavers accept symbols in blocks and
perform identical permutations over each block of data based
on the equations described in [2]. Many proposed designs of
this block are based on a RAM where the data is written in
row order, and then read in column order [4]. However, this
technique will consume a lot of multiplexers, as well as the
need to have RAMs with different sizes according to the
interlever size. Therefore, in this work we have proposed a
new design based on utilizing lookup tables; those were
implemented as small read only memories (ROM). One ROM
was generated for each interleaver size required. The
following list shows an example of the permutation indexes
used to define a ROM in VHDL code.

BPSK ROM
(2*16bits)

1 bit

Input

16 bits

QAM-4 ROM
(4*16 bits)

2 bits
4 bits

QAM-16 ROM
(16*16 bits)

16 bits
16 bits

QAM-64 ROM
(64*16 bits)

I
Q

16 bits

6 bits

2 bits
Modulation index

Figure 4. Mapper internal architecture

The input grouped bits are used to index these ROMs and
obtain the corresponding I/Q pair. The representation of these I
and Q values is based on a fixed point representation with 16
bits width and a 12 bits as a fractional part.

C. IFFT
The Inverse Fast Fourier Transform (IFFT) transforms the
signals from the frequency domain to the time domain. The
discrete-time representation of the signal using N sub-carriers,
is given in equation 1:

1
x (n ) =
N

N 1

IV.

X ( k )W

nk
N

0 n N 1

(1)

k =0

Where

W N = e j 2 / N
Input

As showing in figure 6 this stage was implemented by

multiplexing two dual-port distributed RAMs. The first is used
to read the output of the IFFT samples. The other RAM reads
out the last n samples from the IFFT, followed by the entire
contents of the RAM.

R
A
M

(2)

Computing
Unit
(butterfly)

R
A
M

Ouput

The complete design was firstly modeled and simulated

using Matlab, which allows us to verify its functionality and
validate its performance by exploring design trade-offs
between different sets of parameters. Then individual blocks of
the transmitter were hand coded in VHDL and the entire
system was synthesized, using Xilinx ISE (Integrated Software
Environment) tools, according to the DVB-T specifications
standard (Table 1.).
TABLE I.

OFDM SYSTEM PARAMETERS.

Number of
subcarries

ROM
Control

IMPLEMENTATION RESULTS

256

Fast Fourrier
Transform

Cyclic prefix
lenght

Subcarrier
modulation

256

13 samples

QPSK

Figure 5. IFFT internal architecture

As showing in figure 4, this stage was implemented by

using two dual-port distributed RAMs, one for the inputs of the
butterfly, while the second RAM is used to store the output
from the butterfly operation. One Read Only Memory (ROM)
is also used to store the coefficient of the butterfly operation.
The third important part is the controller through which it is
confirmed that the right pair real and imaginary is going into
the input of the butterfly and also from the ROM as well.
D. Cyclic prefix
In order to combat the inter-symbol interference, OFDM
uses guard interval or a cyclic prefix before each symbol. The
cyclic prefix is a copy of the last n samples from the IFFT,
which are placed at the beginning of the OFDM frame.

A. Simulation result
Hardware architecture for the proposed design was
developed, realized in VHDL. The realized architectures was
tested and validated by comparing outputs generated by a
hardware simulation using Modelsim to the expected outputs
generated using MATLAB. Results show that VHDL design
and Matlab design perform exactly the same algorithm.
Examples of simulation result are given in figures 6 and 7.

Dual port
Memory
N symbols

(1)

(N +L ) symbols

Figure 7. Simulation results of interleaver block.

Dual port
Memory
(1)
Control Unit
Figure 8. Simulation results of mapper block.
Figure 6. Cyclic extension internal architecture

[4]

B. Synthesis result
The synthesis results for each block within the transmitter
are summarized in Table 2 with the required numbers of slices
and BRAMs. The model was targeted to a Virtex II Pro
XC2PV30, the synthesis results from Table I show that the
FPGAs have been adapted very well to the design of the
OFDM transmitter. Indeed all mentioned modules require
around 15% of the available slices and 4% of available blocks
RAMs.
TABLE II. FPGA RESOURCES USED IN THE IMPLEMENTATION OF THE
TRANSMITTER

Resources

Used
resources

Available
resource

Occupation
%

Slices

2056

13696

15%

BRAMs

136

4%

It was found that using ROM for interleaver and

modulation mapping reduces the complexity of computing at
the expense of increasing the memory requirement. The
hardware size is dominated by memory and the FFT block
because we have used a 16-bit fixed point format for the
modulation mapping and FFT blocks. Therefore, by using
smaller bit widths would improve the performance of the
transmitter architecture, as it reduces the computational
complexity.
V.

CONCLUSION

It has been presented the complete design, validation and

synthesis of an OFDM modulator according to the DVB-T
transmission system. This work showed that the actual device
could support the entire system. Many of the blocks could also
be used in other OFDM systems with only minor modification.
For example, the interleaver structures can be applied to other
rectangular interleaving operations by modifying the RAM
sizes and the control unit. Similarly, the constellation mapper
and FFT blocks can be adjusted to handle different maps and
transform sizes, respectively.
Our future work will address the implementation issues and
design structures of the encoding block.

REFERENCES
[1]

[2]

[3]

A. Jeremic, T. A. Thomas, and A. Nehorai, "OFDM channel estimation

in the presence of interference," IEEE Trans. Signal Processing, vol. 52,
pp. 3429-3439, Dec. 2004.
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Video Broadcasting (DVB); Framing Structure, Channel Coding and
Modulation for Digital Terrestrial Television, Jan. 2001, EN 300 744
V1.4.1.
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for terrestrial digital video broadcasting in software on an applicationspecific DSP, in Proceedings of IEEE Workshop on Signal Processing
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[5]

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