Sie sind auf Seite 1von 12

Introduction to Programmable Logic Device

A programmable logic device or PLD is an electronic component used to build digital circuits.
Unlike a logic gate, which has a fixed function, a PLD has an undefined function at the time of
manufacture. Before the PLD can be used in a circuit it must be programmed.
I.

CPLD

CPLD stands for Complex Programmable Logic Device. It is a programmable logic device with
complexity between that of PALs and FPGAs, and architectural features from both. The building
block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form
expressions and more specialized logic operations. PALs and GALs are available only in small
sizes, equivalent to a few hundred logic gates. For bigger logic circuits, complex PLDs or
CPLDs can be used. These contain the equivalent of several PALs linked by programmable
interconnections, all in one integrated circuit. CPLDs can replace thousands, or even hundreds of
thousands, of logic gates.
Some CPLDs are programmed using a PAL programmer, but this method becomes inconvenient
for devices with hundreds of pins. A second method of programming is to solder the device to its
printed circuit board, then feed it with a serial data stream from a personal computer. The CPLD
contains a circuit that decodes the data stream and configures the CPLD to perform its specified
logic function.
Features in common with PALs:
Non-volatile configuration memory. Unlike many FPGAs, an external configuration ROM isn't
required, and the CPLD can function immediately on system start-up. For all but the largest
devices, routing constrains most logic blocks to have input and output signals connected to
external pins (little opportunity for internal state storage or deeply layered logic).
Features in common with FPGAs:
Large number of gates available. CPLDs typically have the equivalent of thousands to tens of
thousands of logic gates, allowing implementation of moderately complicated data processing
devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically
range from tens of thousands to several million. Some provisions for logic more flexible than
sum-of-product expressions, including complicated feedback paths between macro cells, and
specialized logic for implementing various commonly-used functions (such as integer
arithmetic).
II.

History of CPLD

1984 Altera Corporation was an American manufacturer of programmable logic devices (PLDs),
reconfigurable complex digital circuits. The company released its first PLD in 1984.Altera's
main products are the Stratix, Arria and Cyclone series FPGAs, the MAX series CPLDs ,
Quartus II design software and Enpirion PowerSoC DC-DC power solutions.
First re-programmable logic device. Previous devices could only be programmed once. EP 300
by Altera. The first product. An erasable programmable logic device (EPLD) was manufactured
using a 3-micron CMOS EPROM technology and required ultraviolet light to erase the device
prior to reprogramming. The EP300 device had 300 gates and 8 macrocells. Followed by larger
parts such as EP 1200, with 1,200 gates and 28 macrocells.
1987 First PLD to include a dedicated I/O bus interface greatly simplifies creation of devices to
be attached to a standard bus. Altera
1988 First high-density complex programmable logic device: programmable logic begins the
evolution from executing a simple logic function to implementing a subsystem. : MAX 5000
High-density complex programmable logic device (CPLD). Patented redundancy technology
delivers reduction of defects and increased yields (first introduced in 650-nm, this key
technology continues to deliver increased yields in Altera 65-nm devices today).
1989 First integrated, graphical design environment combines schematic input, compilation,
design simulation, and device programming software into a single environment.
1992: Flex 8000. Altera's first field programmable gate array (FPGA).
2000 CPLD & FPGA architectures became similar
Other manufacturers of CPLD:

Atmel Corporation was founded in 1984, by George Perlegos. Atmel was an acronym for
advanced technology for memory and logic. Perlegos had worked in the memory group
of Intel in the 1970s and had co-founded Seeq Technology to manufacture EPROM
memory.

Cypress Semiconductor Corporation is an American semiconductor design and


manufacturing company. It offers NOR flash memories, F-RAM and SRAM Traveo
microcontrollers, the industrys only PSoC programmable system-on-chip solutions,
analog and PMIC Power Management ICs, CapSense capacitive touch-sensing
controllers, Wireless BLE Bluetooth Low-Energy and USB connectivity solutions. It was
founded by T. J. Rodgers and others from Advanced Micro Devices. It was formed in
1982 with backing by Sevin Rosen and went public in 1986. The company initially
focused on the design and development of high speed CMOS SRAMs, EEPROMs, PAL
devices, and TTL logic devices.

Lattice Semiconductor Corporation is a United States based manufacturer of highperformance programmable logic devices (FPGAs, CPLDs, & SPLDs). Lattice was
founded on April 3, 1983, by C. Norman Winningstad, Rahul Sud and Ray Capece
Xilinx, Inc. is an American technology company, primarily a supplier of programmable
logic devices. It is known for inventing the field-programmable gate array (FPGA) and as
the first semiconductor company with a fabless manufacturing model. Ross Freeman,
Bernard Vonderschmitt, and James V Barnett II, who all had worked for integrated circuit
and solid-state device manufacturer Zilog Corp, founded Xilinx in 1984.
III.
Internal Diagram

The internal structure of a typical CPLD is shown in the figure. Each of the four logic blocks is
equivalent to a PLD such as a PAL device. The number of logic blocks in a CPLD could be more
less than four. Each of the logic blocks has programmable interconnections. A switch matrix is
used for logic block to logic block interconnections. The complexity of a typical PAL device may
be of the order of a few hundred logic gates, a CPLD may have a complexity equivalent to tens
of thousands of logic gates. Typically, CPLDs may offer a logic capacity equivalent to that of
about 50 SPLDs.

IV.

Advantages and Disadvantages


The advantageof CPLDs is that more complex designs can be implemented.
Propagation time is only slightly worsethan an equivalent-process PAL due to one
extra set of programmable interconnections. As with PALs, CPLDs have an internal
conguration memory (typically EEPROM) and are also programmed with device
programmers.
2
Smaller CPLDs can be designed with logic languages such as ABEL or CUPL but
larger CPLDs are typically designed using schematic capture (using a CAD program
to prepare schematics) or even through synthesis from HDLs such as VHDL.
A typical CPLD is the Cypress CYC372. This device, as shown above, contains 64
macrocells and 32 I/O pins in a 44-pin package with an overall propagation delay of
10 ns.
Typical CPLDs cost between $5 - $50 depending on the number of macrocells, the
speed and the package.

CPLDs, with their PAL-derived, easy-to-understand AND-OR structure, offer a single-chip


solution with fast pin-to-pin delays, even for wide input functions. Once programmed, the design
can be locked and thus made secure. Most CPLD architectures are very similar, so it is important
to evaluate the subtle nuances. In-system-programmability is a must for today's designs, and the
ability to maintain pin-outs during design modifications ("pin-locking") is crucial. The limited
complexity (<500 flip-flops) means that most CPLDs are used for "glue logic" functions. In
older families, the high static (idle) power consumption prohibits their use in battery-operated
equipment. CoolRunner devices are the notable exception, as they offer the lowest static power
consumption (<50 microamps) of any programmable device.
FPGAs offer much higher complexity, up to 150,000 flip-flops, and their idle power
consumption is reasonably low, although it is sharply increasing in the newest families. Since the
configuration bitstream must be reloaded every time power is re-applied, design security is an
issue, but the benefits and opportunities of dynamic reconfiguration, even in the end-user system,
are an important advantage. FPGAs offer more logic flexibility and more sophisticated system
features than CPLDs: clock management, on-chip RAM, DSP functions, (multipliers), and even
on-chip microprocessors and Multi-Gigabit Transceivers.

Architecture

Granularity is the biggest difference between CPLD and FPGA.

FPGA are "fine-grain" devices. That means that they contain hundreds of (up to
100000) of tiny blocks (called as LUT or CLBs etc) of logic with flip-flops,
combinational logic and memories.FPGAs offer much higher complexity, up to
150,000 flip-flops and large number of gates available.

CPLDs typically have the equivalent of thousands of logic gates, allowing


implementation of moderately complicated data processing devices. PALs typically
have a few hundred gate equivalents at most, while FPGAs typically range from tens
of thousands to several million.

CPLD are "coarse-grain" devices. They contain relatively few (a few 100's max) large
blocks of logic with flip-flops and combinational logic. CPLDs based on AND-OR
structure.

CPLD's have a register with associated logic (AND/OR matrix). CPLD's are mostly
implemented in control applications and FPGA's in datapath applications. Because
of this course grained architecture, the timing is very fixed in CPLDs.

FPGA are RAM based. They need to be "downloaded" (configured) at each powerup. CPLD are EEPROM based. They are active at power-up i.e. as long as they've
been programmed at least once.

FPGA needs boot ROM but CPLD does not. In some systems you might not have
enough time to boot up FPGA then you need CPLD+FPGA.

Generally, the CPLD devices are not volatile, because they contain flash or erasable
ROM memory in all the cases. The FPGA are volatile in many cases and hence they
need a configuration memory for working. There are some FPGAs now which are
nonvolatile. This distinction is rapidly becoming less relevant, as several of the latest
FPGA products also offer models with embedded configuration memory.

The characteristic of non-volatility makes the CPLD the device of choice in modern
digital designs to perform 'boot loader' functions before handing over control to other
devices not having this capability. A good example is where a CPLD is used to load
configuration data for an FPGA from non-volatile memory.

Because of coarse-grain architecture, one block of logic can hold a big equation and
hence CPLD have a faster input-to-output timings than FPGA.

Features

FPGA have special routing resources to implement binary counters,arithmetic


functions like adders, comparators and RAM. CPLD don't have special features like
this.

FPGA can contain very large digital designs, while CPLD can contain small designs
only.The limited complexity (<500>

Speed: CPLDs offer a single-chip solution with fast pin-to-pin delays, even for wide
input functions. Use CPLDs for small designs, where "instant-on", fast and wide
decoding, ultra-low idle power consumption, and design security are important (e.g.,
in battery-operated equipment).

Security: In CPLD once programmed, the design can be locked and thus made
secure. Since the configuration bitstream must be reloaded every time power is reapplied, design security in FPGA is an issue.

Power: The high static (idle) power consumption prohibits use of CPLD in batteryoperated equipment. FPGA idle power consumption is reasonably low, although it is
sharply increasing in the newest families.

Design flexibility: FPGAs offer more logic flexibility and more sophisticated system
features than CPLDs: clock management, on-chip RAM, DSP functions, (multipliers),
and even on-chip microprocessors and Multi-Gigabit Transceivers.These benefits
and opportunities of dynamic reconfiguration, even in the end-user system, are an
important advantage.

Use FPGAs for larger and more complex designs.

FPGA is suited for timing circuit becauce they have more registers , but CPLD is
suited for control circuit because they have more combinational circuit. At the same
time, If you synthesis the same code for FPGA for many times, you will find out that
each timing report is different. But it is different in CPLD synthesis, you can get the
same result.

As CPLDs and FPGAs become more advanced the differences between the two device
types will continue to blur. While this trend may appear to make the two types more difficult
to keep apart, the architectural advantage of CPLDs combining low cost, non-volatile
configuration, and macro cells with predictable timing characteristics will likely be sufficient
to maintain a product differentiation for the foreseeable future.

1. FPGA contains up to 100,000 of tiny logic blocks while CPLD contains only a few blocks of
logic that reaches up to a few thousands.
2. In terms of architecture, FPGAs are considered as fine-grain devices while CPLDs are
coarse-grain.
3. FPGAs are great for more complex applications while CPLDs are better for simpler ones.
4. FPGAs are made up of tiny logic blocks while CPLDs are made of larger blocks.
5. FPGA is a RAM-based digital logic chip while CPLD is EEPROM-based.
6. Normally, FPGAs are more expensive while CPLDs are much cheaper.
7. Delays are much more predictable in CPLDs than in FPGAs.

V.

Innovation
A field programmable gate array (FPGA) is a semiconductor device containing
programmable logic components and programmable interconnects. The
programmable logic components can be programmed to duplicate the functionality of
basic logic gates such as AND, OR, XOR, NOT or more complex combinational
functions such as decoders or simple math functions. In most FPGAs, these
programmable logic components (or logic blocks, in FPGA parlance) also include
memory elements, which may be simple flip-flops or more complete blocks of
memories.

A hierarchy of programmable interconnects allows the logic blocks of an FPGA to be


interconnected as needed by the system designer, somewhat like a one-chip
programmable breadboard. These logic blocks and interconnects can be programmed
after the manufacturing process by the customer/designer (hence the term "field
programmable", i.e. programmable in the field) so that the FPGA can perform
whatever logical function is needed.
FPGAs are generally slower than their application-specific integrated circuit (ASIC)
counterparts, can't handle as complex a design, and draw more power. However, they
have several advantages such as a shorter time to market, ability to re-program in the
field to fix bugs, and lower nonrecurring engineering costs. Vendors can sell cheaper,
less flexible versions of their FPGAs which cannot be modified after the design is
committed. The development of these designs is made on regular FPGAs and then
migrated into a fixed version that more resembles an ASIC. Complex programmable
logic devices, or CPLDs, are another alternative.
History
The historical roots of FPGAs are in complex programmable logic devices (CPLDs)
of the early to mid 1980s. Ross Freeman, Xilinx co-founder, invented the field
programmable gate array in 1984. CPLDs and FPGAs include a relatively large
number of programmable logic elements. CPLD logic gate densities range from the
equivalent of several thousand to tens of thousands of logic gates, while FPGAs
typically range from tens of thousands to several million.
The primary differences between CPLDs and FPGAs are architectural. A CPLD has a
somewhat restrictive structure consisting of one or more programmable sum-ofproducts logic arrays feeding a relatively small number of clocked registers. The
result of this is less flexibility, with the advantage of more predictable timing delays
and a higher logic-to-interconnect ratio. The FPGA architectures, on the other hand,
are dominated by interconnect. This makes them far more flexible (in terms of the
range of designs that are practical for implementation within them) but also far more
complex to design for.
Another notable difference between CPLDs and FPGAs is the presence in most
FPGAs of higher-level embedded functions (such as adders and multipliers) and
embedded memories. A related, important difference is that many modern FPGAs
support full or partial in-system reconfiguration, allowing their designs to be changed
"on the fly" either for system upgrades or for dynamic reconfiguration as a normal
part of system operation. Some FPGAs have the capability

12
of partial re-configuration that lets one portion of the device be re-programmed while
other portions continue running.
Modern Developments
A recent trend has been to take the coarse-grained architectural approach a step
further by combining the logic blocks and interconnects of traditional FPGAs with
embedded microprocessors and related peripherals to form a complete "system on a
programmable chip". Examples of such hybrid technologies can be found in the
Xilinx Virtex-II PRO and Virtex-4 devices, which include one or more PowerPC
processors embedded within the FPGA's logic fabric. The Atmel FPSLIC is another
such device, which uses an AVR processor in combination with Atmel's
programmable logic architecture. An alternate approach is to make use of "soft"
processor cores that are implemented within the FPGA logic. These cores include the
Xilinx MicroBlaze and PicoBlaze, the Altera Nios and Nios II processors, and the
open source LatticeMico32 and LatticeMico8, as well as third-party (either
commercial or free) processor cores. For a given CPU architecture, a hard
(embedded) CPU core will outperform a soft-core CPU (i.e., a programmable-logic
implementation of the CPU).
As previously mentioned, many modern FPGAs have the ability to be reprogrammed
at "run time," and this is leading to the idea of reconfigurable computing or
reconfigurable systems CPUs that reconfigure themselves to suit the task at hand.
Current FPGA tools, however, do not fully support this methodology.
Additionally, new, non-FPGA architectures are beginning to emerge. Softwareconfigurable microprocessors such as the Stretch S5000 adopt a hybrid approach by
providing an array of processor cores and FPGA-like programmable cores on the
same chip. Other devices (such as Mathstar's Field Programmable Object Array, or
FPOA) provide arrays of higher-level programmable objects that lie somewhere
between an FPGA's logic block and a more complex processor. Applications
Applications of FPGAs include DSP, software-defined radio, aerospace and defense
systems, ASIC prototyping, medical imaging, computer vision, speech recognition,
cryptography, bioinformatics, computer hardware emulation and a growing range of
other areas. FPGAs originally began as competitors to CPLDs and competed in a
similar space, that of glue logic for PCBs. As their size, capabilities, and speed
increased, they began to take over larger and larger functions to the state where some
are now marketed as full systems on chips (SOC).

FPGAs especially find applications in any area or algorithm that can make use of the
massive parallelism offered by their architecture. One such area is code breaking, in
particular brute-force attack, of cryptographic algorithms.
FPGA design and programming
To define the behavior of the FPGA the user provides a hardware description
language (HDL) or a schematic design. Common HDLs are VHDL and Verilog. Then,
using an electronic design automation tool, a technology-mapped netlist is generated.
The netlist can then be fitted to the actual FPGA architecture using a process called
place-and-route, usually performed by the FPGA company's proprietary place-androute software. The user will validate the map, place and route results via timing
analysis, simulation, and other verification methodologies. Once the design and
validation process is complete, the binary file generated (also using the FPGA
company's proprietary software) is used to (re)configure the FPGA .
In an attempt to reduce the complexity of designing in HDLs, which have been
compared to the equivalent of assembly languages, there are moves to raise the
abstraction level of the design. Companies such as Cadence, Synopsys and Celoxica
are promoting SystemC as a way to combine high level languages with concurrency
models to allow faster design cycles for FPGAs than is possible using traditional
HDLs. Approaches based on standard C or C++ (with libraries or other extensions
allowing parallel programming) are found in the Catapult C tools from Mentor
Graphics, and in the Impulse C tools from Impulse Accelerated Technologies.
Annapolis Micro Systems, Inc.'s CoreFire Design Suite and National Instruments
LabVIEW FPGA provide a graphical dataflow approach to high-level design entry.
Languages such as SystemVerilog, SystemVHDL, and Handel-C (from Celoxica)
seek to accomplish the same goal, but are aimed at making existing hardware
engineers more productive versus making FPGAs more accessible to
15
existing software engineers. There is more information on C to HDL and Flow to
HDL on their respective pages.
To simplify the design of complex systems in FPGAs, there exist libraries of
predefined complex functions and circuits that have been tested and optimized to
speed up the design process. These predefined circuits are commonly called IP cores,
and are available from FPGA vendors and third-party IP suppliers (rarely free, and
typically released under proprietary licenses). Other predefined circuits are available

from developer communities such as OpenCores (typically "free", and released under
the GPL, BSD or similar license), and other sources.
In a typical design flow, an FPGA application developer will simulate the design at
multiple stages throughout the design process. Initially the RTL description in VHDL
or Verilog is simulated by creating test benches to simulate the system and observe
results. Then, after the synthesis engine has mapped the design to a netlist, the netlist
is translated to a gate level description where simulation is repeated to confirm the
synthesis proceeded without errors. Finally the design is laid out in the FPGA at
which point propagation delays can be added and the simulation run again with these
values back-annotated onto the netlist.
Basic process technology types
SRAM
- based on static memory technology. In-system programmable and
reprogrammable. Requires external boot devices. CMOS. Antifuse - One-time
programmable. CMOS. EPROM - Erasable Programmable Read-Only Memory
technology. Usually one-time programmable in production because of plastic
packaging. Windowed devices can be erased with ultraviolet (UV) light. CMOS.
EEPROM - Electrically Erasable Programmable Read-Only Memory technology.
Can be erased, even in plastic packages. Some, but not all, EEPROM devices can be
in-system programmed. CMOS. Flash - Flash-erase EPROM technology. Can be
erased, even in plastic packages. Some, but not all, flash devices can be in-system
programmed. Usually, a flash cell is smaller than an equivalent EEPROM cell and is
therefore less expensive to manufacture. CMOS. Fuse - One-time programmable.
Bipolar. FPGA manufacturers and their specialties
As of late 2005, the FPGA market has mostly settled into a state where there are two
major "general-purpose" FPGA manufacturers and a number of other players who
differentiate themselves by offering unique capabilities.
Xilinx and Altera are the current FPGA market leaders. Lattice Semiconductor
provides both SRAM and non-volatile, flash-based FPGAs. Actel has antifuse and
reprogrammable flash-based FPGAs, and also offers mixed signal flash-based
FPGAs. Atmel provides fine-grain reconfigurable devices, as the Xilinx XC62xx
were. They focus on providing AVR Microcontrollers with FPGA fabric on the same
die.
16