Delay through resistive

Interconnect

In modern Chips delay thro wires in longer than delay

thro gates - ..
RC Transmission Line
-model as infinitesimal RC sections each representing
differential Resistance and capacitance
- a transmission line model can be used to compute
delay thro long wires
- A TL has unit resistance (r) and unit capa. (c)
-Fig.shows schematic RC TL
Symbol for distributed
Transmission line

-The Transmission Lines voltage response modelled by

diff.eqnas,

-- this model gives voltage as a fn of both x position along

the wire and of time

Delay modeling thro wires Elmore proposed a widely used metric RC WIRE
DELAY
-defined delay as first moment of the impulse response of the network

Elmore modelled transmission line as a sequence of n sections of RC (fig)

 Elmore delay computed by taking sums of RC network

where each resistance is multiplied by sum of all capacitors
downstream..
All transm.line section resistances and capacitances in an
section are identical.. So response (impulse) reduces to

Wire delay grows as square of wire length, since n ..prop to wire

length

-delay prop unit resistance to capacitances material (metal)

Should have low RC product

 Normalized voltage response of transmission

line

Where R and C - total resistance and capacitances of line

 Let Rt internal resistance of the driving gate and

Ct load cap at the opposite end of transmission line

The first order estimate of step response is given expression (sakurai)..

Where RT = Rt/R and CT = Ct/C

Analysis till now resistance with constant width

Tapered wires provide lower delay.

Consider first resistance of the elt --- ct reqd to charge all cap
must flow through this resistance
--- resistance at the end wire handles only the cap at the end
--- if head of the resistance wire is decreased we can decrease
delay of the wire (inc R by widening the wire also inc. CAP)

 OPTIMUM SHAPED WIRE EXPONENTIAL TAPER

IF source res is R0 and sink cap c0, the unit resistance and cap are Rs and Cs, the
width of wire as fn of distance is gn by eqn below..
Optimally tapered wire 3.72 ns delay . Constant width wire delay 4.04ns
Optimal wire shrinks from 30.7 um at source to 7.8 um at sink

Delay through RC trees

Analyzing complex networks harder
RC trees accurate bounds on delay computed
Wiring broken into RC tree either by representing each
branch by one RC lump / by breaking a branch into multiple
Lumps
RC tree assume that the network has one input provides
voltage step and several outputs

Transisition time thro wire can be

Analyzed voltage at O/p node
-Measuring time between 10 % and 90%
Of its value.
-Accurate measure on upper and lower
Bounds of o/p voltage related with
delay bounds

- Cap at node K --- CK

-Consider resistances along the path
mainly resistance along shared paths
- if o - is an o/p node and k is an
internal node, - the resistance along
intersection of the paths from i/p to o
and to k is called Rko fig, R1o1 = R1 only
resistor shared by path 1 and O1.

 Roo is the total resistance from input to o/p O

Rkk is the total resistance- from i/p to internal node k
The simplest time constant for the tree,
Tp = RkkCk ,
- Each term in the summation in time constant of simple
RC ckt built from the cap at k and all the resistances
from input to k.

 Two other time constants relative to the o/p O, are important to

the bounds:

TDo RkoCk
k

TRo ( RkoCk ) / Roo

k

Term TDo compute the time constant of the capacitance at each

node & resistance shared by the path to k and o available to
charge Ck
The terms TRo weight the terms of TDo against the total res.
Along the path to the output, squaring Rko to ensure the value
has units of time.

 At t=0, the upper bound of the o/p voltage is

Vo(0)= 1- TD0 .
TD0 is formed by the time constants of RC sections all
res along the path to 0, that are also connected to kth
capacitor..
Some ct thro those res will go to other o/p other than o
& so not available to charge the cap closest to o;

 Upper bound assumes that all their ct will be used

to charge cap along the path from i/p to o
The lower bound is dominated by TRo, which
compares Rko to the total resistance from the i/p to o

The ratio Rko / Roo gives a minimum resistance

available to charge the cap Ck .

Buffer insertion in RC
transmission Line
measurement of minimum delay -thro RC T.L not
modeled / obtained putting a single driver at T.Ls
source.
Put a series of buffers equally space thro the line to
restore the signal
Bakoglu derived the optimal no of repeaters and
repeater size for RC T.L

Fig. RC T.L with repeaters

Divide the T.L into k sections each of length l Each buffer will be of size h.

 Size of repeater h =1 & the line broke into k

sections
Rint and Cint total res and cap of TL
Ro drivers equivalent res and Co i/p cap
Then 50% delay formula is gn by,

 Minimum delay can be found by setting dT /dk = 0 .

This gives the no of repeaters as,

k (0.4R int C int) /(0.7 RoCo)

When size of the repeater to an arbitrary value h, the
delay equation becomes,

Min delay can be calculated by setting dT/dk =0 and dT/dh =0.

This gives the optimal values for k and h as,

The total delay at these

values is ,

Cross talk using RC wires

Cross talk slows down the signals major factorfor delay
Crosstalk noise increases the signal setting time

 Two nets are coupled by parasitic cap.

One net is the aggressor net that interferes with a
victim net thro coupling capacitance
A transition from aggressor net to victim net causes
glitch in victims net
In static combinational logic, cross talk increases the
delay across a net..
In a dynamic logic , cross talk can cause the state of
the node to flip causing a permanent error.

Delay through
Inductive Interconnect

RLC basics
Fig. Shows single RLC section
Damping factor is defined as ,
poles of RLC section are at
Ckt is overdamped ( if >1) responds to
impulse /step by monotonically approaching
the final voltage
Ckt is underdamped ( if <1) oscillates as it
converges to the steady state voltage

 Simplest form of RLC Tx.linelossless LC lineWith zero

resistance.
Signal propagates along
Tx.line with velocity of
Propagation delay thro LC
transmission line of length l
This is lower bound value of
delay introduced in Tx.line

RLC Transmission Line Delay

Rt,Lt,Ct total res.,total ind and total cap of TX line

R,L,C unit res, unit inductance and unit capacitance
Rtr- Driver resistance
CL load cap

 Delay is fn of damping
factor

50% propagation delay

Buffer Insertion in
RLC Transmission Lines

 Tx. Line divided in to k sections, each of length l/k.

All buffers are of same size
Ro Source resistance, Co- Load cap

TL / R

Lt / Rt
RoCo