IJSTE - International Journal of Science Technology & Engineering | Volume 2 | Issue 12 | June 2016

ISSN (online): 2349-784X

Design and Analysis of Low Power Johnson

Counter with Improved Performance using MTCMOS and Clock Gating
Ranjana Yadav
M. Tech. Student
Department of Electronics & Communication Engineering
Hindustan College of Science & Technology

Alka Agrawal
Assistant Professor
Department of Electronics & Communication Engineering
Hindustan College of Science & Technology

Abstract
To minimize Power dissipation is one of the major concerns in recent VLSI designing. As technology is growing our chip size is
getting reduced and many other micro-electronics reliabilities are growing slowly, minimum power designing of any system has
become priority. Computer system consists of sequential circuits mostly and that is why efficient low power design of various
sequential circuits is very important. In this paper, we have proposed a low power design scheme of Johnson Counter using
MTCMOS technique. Doing some power analysis, it is considered that our proposed system has lower power dissipation and
power delay product as compared to the conventional design.
Keywords: MTCMOS technique, Johnson Counter, Clock Gating
________________________________________________________________________________________________________
I.

INTRODUCTION

Johnson Counter:

Fig. 1: Johnson Counter

The Johnson Ring Counter is another shift registers with feedback exactly the same as the standard Ring Counter, except that the
inverted output Q of the last flip-flop is now connected back to the input D of the first flip-flop as shown above.
The main advantage of this type of ring counter is that it only needs half the number of flip-flops compared to the standard
ring counter then its modulo number is halved. So an n-stage Johnson counter will circulate a single data bit giving sequence
of 2n different states and can therefore be considered as a mod-2n counter.
II. WORKING OF JOHNSON COUNTER

Initially all the flip flops are cleared, so the time inverted output (Q) of 4th flip flop is high or logic 1.
This logic 1 is appears at the input of 1st flip flop. During the first clock pulse this logic 1 is transferred to the output of 1st
flip flop. Thus the total output of Johnson counter is 1000.

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Design and Analysis of Low Power Johnson Counter with Improved Performance using MT-CMOS and Clock Gating
(IJSTE/ Volume 2 / Issue 12 / 051)

Then input of 1st and 2nd flip flop is logic 1 and after the second clock pulse these inputs appear at the outputs of 1st and
2nd flip flop. So the total output is 1100.
Then input of 1st, 2nd and 3rd flip flop is logic 1 and after the third clock pulse these inputs appear at the outputs of 1st, 2nd
and 3rd flip flop. So the total output is 1110.
Similarly for the next clock pulse, the output will be 1111.
During this state (1111) the time inverted output (Q) is logic 0. This 0 is fed to the 1st flip flop. Then the 0 will circulate
through the flip flops as 0111,0011,0001,0000.
Table 1
Truth Table for Johnson Counter
QA QB QC QD States
0
0
0
0
State 0
1
0
0
0
State 1
1
1
0
0
State 2
1
1
1
0
State 3
1
1
1
1
State 4
0
1
1
1
State 5
0
0
1
1
State 6
0
0
0
1
State 7

After state 5, the circuit goes to state 0 and this will repeat.
III. MTCMOS TECHNOLOGY
In this technique high threshold voltage transistor are used to isolate the low threshold voltage transistor from supply and ground
during standby mode. However by including extra transistor, MTCMOS circuit faces performance penalty compared to CMOS
circuits, if the transistor are not sized properly. The high threshold voltage transistor are turned off during standby (sleep mode) ,
this result very low sub threshold passes from Vcc to ground. MTCMOS includes high Vt transistor to gate power and ground of a
low Vt logic blocks. When the high V t transistor are off resulting in a very low sub threshold leakage current. When the high V t
transistor are turned on, low V t are connected to virtual ground and Vdd.

Fig. 2: MTCMOS technique

IV. CLOCK GATING SYSTEM

In this technique, the clock signal is not connected directly to the clock port of sequential device (e.g. flip-flop in our case) as
shown in figure 3. Instead they are connected via an intermediate circuit block which is working as Clock Gating System. For
using clock gating technique, we must define clock gating logic for each of the devices in a way that each of the device receives
clock pulses only when it requires to be operated.
If the logic is true, it will be getting clock and if the logic is found to be false, the clock will be blocked for that duration for
that device. Thus it minimizes power dissipation by ensuring that only the effective clock pulses and by avoiding or blocking the
not required clock transitions.

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Design and Analysis of Low Power Johnson Counter with Improved Performance using MT-CMOS and Clock Gating
(IJSTE/ Volume 2 / Issue 12 / 051)

Fig. 3: Clock gating technique

V. PROPOSED WORK
In the proposed work, we have designed a Johnson Counter using four D-Flip Flop circuits. All flip flops are operated with
Clock Gating System. The main difference between our proposed design and conventional Johnson Counter is that we have used
MTCMOS technology along with Clock Gating technique in the circuit. The design is being operated at certain frequencies and
results have been obtained.
The schematic diagram of Johnson Counter is shown below.

Fig. 4: Schematic Design of Johnson Counter

The output waveform of the counter is shown in figure 5.

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Design and Analysis of Low Power Johnson Counter with Improved Performance using MT-CMOS and Clock Gating
(IJSTE/ Volume 2 / Issue 12 / 051)

Fig. 5: Output waveform for Johnson Counter

VI. RESULTS
To analyze the performance of the structures we have simulated the circuits at certain frequencies and output is been observed
which is presented in tabular format below. The power consumption have been obtained and compared with both the designs.
Table 1
Comparison between Conventional and Proposed Johnson Counter
Power Consumption
Frequency
(MHZ)
Conventional Johnson Counter Proposed Johnson Counter
600
161u
97u
700
187u
112u
800
218u
128u
900
241u
143u
1000
267u
157u

VII. CONCLUSION
Both the design methodologies have been compared and it is evident that there is performance improvement in the proposed
circuit. MTCMOS and Clock Gating technique are an effective way to reduce leakage current and power consumption. All the
designs have been simulated at Tanner EDA 14.11 version.
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Sani Md. Ismail, A B M Saadmaan Rahman, Farha Tamanna Islam "Low Power Design of Johnson Counter Using Clock Gating" from 978-1-4673-48362/12/$31.00 2012 IEEE
Neil H. E. Weste, David Harris and Ayan Banerjee, CMOS VLSI Design , 3rd edition, Dorling Kindersley Pvt. Ltd. 2006.
S.H. Unger, Double-edge-triggered flip-flops, IEEE transactions on Computers, 30(6): 447-451, 1981.
Mutoh S et al, 1-V Power supply high-speed digital circuit technology with multithreshold- voltage CMOS, IEEE J. Solid State Circuits, Vol. 30, pp.
847-854, August 1995.
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